From: Sachin Saxena <sachin.saxena@nxp.com>
To: dev@dpdk.org
Cc: thomas@monjalon.net, Sunil Kumar Kori <sunil.kori@nxp.com>
Subject: [dpdk-dev] [PATCH v2 30/30] net/dpaa2: add soft parser driver
Date: Thu, 29 Aug 2019 15:57:37 +0530 [thread overview]
Message-ID: <20190829102737.13267-31-sachin.saxena@nxp.com> (raw)
In-Reply-To: <20190829102737.13267-1-sachin.saxena@nxp.com>
From: Sunil Kumar Kori <sunil.kori@nxp.com>
Signed-off-by: Sunil Kumar Kori <sunil.kori@nxp.com>
---
drivers/net/dpaa2/Makefile | 1 +
drivers/net/dpaa2/dpaa2_ethdev.c | 24 +++
drivers/net/dpaa2/dpaa2_ethdev.h | 4 +
drivers/net/dpaa2/dpaa2_sparser.c | 269 ++++++++++++++++++++++++++++++
drivers/net/dpaa2/dpaa2_sparser.h | 206 +++++++++++++++++++++++
drivers/net/dpaa2/meson.build | 1 +
6 files changed, 505 insertions(+)
create mode 100644 drivers/net/dpaa2/dpaa2_sparser.c
create mode 100644 drivers/net/dpaa2/dpaa2_sparser.h
diff --git a/drivers/net/dpaa2/Makefile b/drivers/net/dpaa2/Makefile
index 0cc539dc5..7924871c8 100644
--- a/drivers/net/dpaa2/Makefile
+++ b/drivers/net/dpaa2/Makefile
@@ -34,6 +34,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_DPAA2_PMD) += dpaa2_rxtx.c
SRCS-$(CONFIG_RTE_LIBRTE_DPAA2_PMD) += dpaa2_ethdev.c
SRCS-$(CONFIG_RTE_LIBRTE_DPAA2_PMD) += dpaa2_flow.c
SRCS-$(CONFIG_RTE_LIBRTE_DPAA2_PMD) += dpaa2_mux.c
+SRCS-$(CONFIG_RTE_LIBRTE_DPAA2_PMD) += dpaa2_sparser.c
SRCS-$(CONFIG_RTE_LIBRTE_DPAA2_PMD) += mc/dpni.c
SRCS-$(CONFIG_RTE_LIBRTE_DPAA2_PMD) += mc/dpkg.c
SRCS-$(CONFIG_RTE_LIBRTE_DPAA2_PMD) += mc/dpdmux.c
diff --git a/drivers/net/dpaa2/dpaa2_ethdev.c b/drivers/net/dpaa2/dpaa2_ethdev.c
index 2fb65685d..3ae52d605 100644
--- a/drivers/net/dpaa2/dpaa2_ethdev.c
+++ b/drivers/net/dpaa2/dpaa2_ethdev.c
@@ -26,6 +26,7 @@
#include <dpaa2_hw_dpio.h>
#include <mc/fsl_dpmng.h>
#include "dpaa2_ethdev.h"
+#include "dpaa2_sparser.h"
#include <fsl_qbman_debug.h>
#define DRIVER_LOOPBACK_MODE "drv_loopback"
@@ -2499,6 +2500,29 @@ dpaa2_dev_init(struct rte_eth_dev *eth_dev)
goto init_err;
}
+ /*TODO To enable soft parser support DPAA2 driver needs to integrate
+ * with external entity to receive byte code for software sequence
+ * and same will be offload to the H/W using MC interface.
+ * Currently it is assumed that DPAA2 driver has byte code by some
+ * mean and same if offloaded to H/W.
+ */
+ if (getenv("DPAA2_ENABLE_SOFT_PARSER")) {
+ WRIOP_SS_INITIALIZER(priv);
+ ret = dpaa2_eth_load_wriop_soft_parser(priv, DPNI_SS_INGRESS);
+ if (ret < 0) {
+ DPAA2_PMD_ERR(" Error(%d) in loading softparser\n",
+ ret);
+ return ret;
+ }
+
+ ret = dpaa2_eth_enable_wriop_soft_parser(priv,
+ DPNI_SS_INGRESS);
+ if (ret < 0) {
+ DPAA2_PMD_ERR(" Error(%d) in enabling softparser\n",
+ ret);
+ return ret;
+ }
+ }
RTE_LOG(INFO, PMD, "%s: netdev created\n", eth_dev->data->name);
return 0;
init_err:
diff --git a/drivers/net/dpaa2/dpaa2_ethdev.h b/drivers/net/dpaa2/dpaa2_ethdev.h
index bcb8360be..823f9e97c 100644
--- a/drivers/net/dpaa2/dpaa2_ethdev.h
+++ b/drivers/net/dpaa2/dpaa2_ethdev.h
@@ -22,6 +22,7 @@
#define MAX_TCS DPNI_MAX_TC
#define MAX_RX_QUEUES 128
#define MAX_TX_QUEUES 16
+#define MAX_DPNI 8
/*default tc to be used for ,congestion, distribution etc configuration. */
#define DPAA2_DEF_TC 0
@@ -131,6 +132,9 @@ struct dpaa2_dev_priv {
uint64_t fs_extract_param[MAX_TCS];
} extract;
+ uint16_t ss_offset;
+ uint64_t ss_iova;
+ uint64_t ss_param_iova;
#if defined(RTE_LIBRTE_IEEE1588)
/*stores timestamp of last received packet on dev*/
uint64_t rx_timestamp;
diff --git a/drivers/net/dpaa2/dpaa2_sparser.c b/drivers/net/dpaa2/dpaa2_sparser.c
new file mode 100644
index 000000000..7e8fedd81
--- /dev/null
+++ b/drivers/net/dpaa2/dpaa2_sparser.c
@@ -0,0 +1,269 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright 2018-2019 NXP
+ */
+
+#include <rte_mbuf.h>
+#include <rte_ethdev.h>
+#include <rte_malloc.h>
+#include <rte_memcpy.h>
+#include <rte_string_fns.h>
+#include <rte_dev.h>
+
+#include <fslmc_logs.h>
+#include <fslmc_vfio.h>
+#include <dpaa2_hw_pvt.h>
+#include <dpaa2_hw_dpio.h>
+#include <dpaa2_hw_mempool.h>
+#include <dpaa2_pmd_logs.h>
+
+#include "dpaa2_ethdev.h"
+#include "dpaa2_sparser.h"
+#include "base/dpaa2_hw_dpni_annot.h"
+#define __STDC_FORMAT_MACROS
+#include <stdint.h>
+#include <inttypes.h>
+
+uint8_t wriop_bytecode[] = {
+ 0x00, 0x04, 0x29, 0x42, 0x03, 0xe0, 0x12, 0x00, 0x29, 0x02,
+ 0x18, 0x00, 0x87, 0x3c, 0x00, 0x02, 0x18, 0x00, 0x00, 0x00
+};
+
+struct frame_attr frame_attr_arr[] = {
+ /* Frame Attribute Flags 1 */
+ /* 000 */ {"Routing header present in IPv6 header 2 ", 0, 0x80000000},
+ /* 001 */ {"GTP Primed was detected ", 0, 0x40000000},
+ /* 002 */ {"VLAN with VID = 0 was detected ", 0, 0x20000000},
+ /* 003 */ {"A PTP frame was detected ", 0, 0x10000000},
+ /* 004 */ {"VXLAN was parsed ", 0, 0x08000000},
+ /* 005 */ {"A VXLAN HXS parsing error was detected ", 0, 0x04000000},
+ /* 006 */ {"Ethernet control protocol was detected ", 0, 0x02000000},
+ /* 007 */ {"IKE was detected at UDP port 4500 ", 0, 0x01000000},
+ /* 008 */ {"Shim Shell Soft Parsing Error ", 0, 0x00800000},
+ /* 009 */ {"Parsing Error ", 0, 0x00400000},
+ /* 010 */ {"Ethernet MAC Present ", 0, 0x00200000},
+ /* 011 */ {"Ethernet Unicast ", 0, 0x00100000},
+ /* 012 */ {"Ethernet Multicast ", 0, 0x00080000},
+ /* 013 */ {"Ethernet Broadcast ", 0, 0x00040000},
+ /* 014 */ {"BPDU frame (MAC DA is 01:80:C2:00:00:00)", 0, 0x00020000},
+ /* 015 */ {"FCoE detected (Ether type is 0x8906) ", 0, 0x00010000},
+ /* 016 */ {"FIP detected (Ether type is 0x8914) ", 0, 0x00008000},
+ /* 017 */ {"Ethernet Parsing Error ", 0, 0x00004000},
+ /* 018 */ {"LLC+SNAP Present ", 0, 0x00002000},
+ /* 019 */ {"Unknown LLC/OUI ", 0, 0x00001000},
+ /* 020 */ {"LLC+SNAP Error ", 0, 0x00000800},
+ /* 021 */ {"VLAN 1 Present ", 0, 0x00000400},
+ /* 022 */ {"VLAN n Present ", 0, 0x00000200},
+ /* 023 */ {"CFI bit in a \"8100\" VLAN tag is set ", 0, 0x00000100},
+ /* 024 */ {"VLAN Parsing Error ", 0, 0x00000080},
+ /* 025 */ {"PPPoE+PPP Present ", 0, 0x00000040},
+ /* 026 */ {"PPPoE+PPP Parsing Error ", 0, 0x00000020},
+ /* 027 */ {"MPLS 1 Present ", 0, 0x00000010},
+ /* 028 */ {"MPLS n Present ", 0, 0x00000008},
+ /* 029 */ {"MPLS Parsing Error ", 0, 0x00000004},
+ /* 030 */ {"ARP frame Present (Ethertype 0x0806) ", 0, 0x00000002},
+ /* 031 */ {"ARP Parsing Error ", 0, 0x00000001},
+ /* Frame Attribute Flags 2 */
+ /* 032 */ {"L2 Unknown Protocol ", 1, 0x80000000},
+ /* 033 */ {"L2 Soft Parsing Error ", 1, 0x40000000},
+ /* 034 */ {"IPv4 1 Present ", 1, 0x20000000},
+ /* 035 */ {"IPv4 1 Unicast ", 1, 0x10000000},
+ /* 036 */ {"IPv4 1 Multicast ", 1, 0x08000000},
+ /* 037 */ {"IPv4 1 Broadcast ", 1, 0x04000000},
+ /* 038 */ {"IPv4 n Present ", 1, 0x02000000},
+ /* 039 */ {"IPv4 n Unicast ", 1, 0x01000000},
+ /* 040 */ {"IPv4 n Multicast ", 1, 0x00800000},
+ /* 041 */ {"IPv4 n Broadcast ", 1, 0x00400000},
+ /* 042 */ {"IPv6 1 Present ", 1, 0x00200000},
+ /* 043 */ {"IPv6 1 Unicast ", 1, 0x00100000},
+ /* 044 */ {"IPv6 1 Multicast ", 1, 0x00080000},
+ /* 045 */ {"IPv6 n Present ", 1, 0x00040000},
+ /* 046 */ {"IPv6 n Unicast ", 1, 0x00020000},
+ /* 047 */ {"IPv6 n Multicast ", 1, 0x00010000},
+ /* 048 */ {"IP 1 option present ", 1, 0x00008000},
+ /* 049 */ {"IP 1 Unknown Protocol ", 1, 0x00004000},
+ /* 050 */ {"IP 1 Packet is a fragment ", 1, 0x00002000},
+ /* 051 */ {"IP 1 Packet is an initial fragment ", 1, 0x00001000},
+ /* 052 */ {"IP 1 Parsing Error ", 1, 0x00000800},
+ /* 053 */ {"IP n option present ", 1, 0x00000400},
+ /* 054 */ {"IP n Unknown Protocol ", 1, 0x00000200},
+ /* 055 */ {"IP n Packet is a fragment ", 1, 0x00000100},
+ /* 056 */ {"IP n Packet is an initial fragment ", 1, 0x00000080},
+ /* 057 */ {"ICMP detected (IP proto is 1) ", 1, 0x00000040},
+ /* 058 */ {"IGMP detected (IP proto is 2) ", 1, 0x00000020},
+ /* 059 */ {"ICMPv6 detected (IP proto is 3a) ", 1, 0x00000010},
+ /* 060 */ {"UDP Light detected (IP proto is 136) ", 1, 0x00000008},
+ /* 061 */ {"IP n Parsing Error ", 1, 0x00000004},
+ /* 062 */ {"Min. Encap Present ", 1, 0x00000002},
+ /* 063 */ {"Min. Encap S flag set ", 1, 0x00000001},
+ /* Frame Attribute Flags 3 */
+ /* 064 */ {"Min. Encap Parsing Error ", 2, 0x80000000},
+ /* 065 */ {"GRE Present ", 2, 0x40000000},
+ /* 066 */ {"GRE R bit set ", 2, 0x20000000},
+ /* 067 */ {"GRE Parsing Error ", 2, 0x10000000},
+ /* 068 */ {"L3 Unknown Protocol ", 2, 0x08000000},
+ /* 069 */ {"L3 Soft Parsing Error ", 2, 0x04000000},
+ /* 070 */ {"UDP Present ", 2, 0x02000000},
+ /* 071 */ {"UDP Parsing Error ", 2, 0x01000000},
+ /* 072 */ {"TCP Present ", 2, 0x00800000},
+ /* 073 */ {"TCP options present ", 2, 0x00400000},
+ /* 074 */ {"TCP Control bits 6-11 set ", 2, 0x00200000},
+ /* 075 */ {"TCP Control bits 3-5 set ", 2, 0x00100000},
+ /* 076 */ {"TCP Parsing Error ", 2, 0x00080000},
+ /* 077 */ {"IPSec Present ", 2, 0x00040000},
+ /* 078 */ {"IPSec ESP found ", 2, 0x00020000},
+ /* 079 */ {"IPSec AH found ", 2, 0x00010000},
+ /* 080 */ {"IPSec Parsing Error ", 2, 0x00008000},
+ /* 081 */ {"SCTP Present ", 2, 0x00004000},
+ /* 082 */ {"SCTP Parsing Error ", 2, 0x00002000},
+ /* 083 */ {"DCCP Present ", 2, 0x00001000},
+ /* 084 */ {"DCCP Parsing Error ", 2, 0x00000800},
+ /* 085 */ {"L4 Unknown Protocol ", 2, 0x00000400},
+ /* 086 */ {"L4 Soft Parsing Error ", 2, 0x00000200},
+ /* 087 */ {"GTP Present ", 2, 0x00000100},
+ /* 088 */ {"GTP Parsing Error ", 2, 0x00000080},
+ /* 089 */ {"ESP Present ", 2, 0x00000040},
+ /* 090 */ {"ESP Parsing Error ", 2, 0x00000020},
+ /* 091 */ {"iSCSI detected (Port# 860) ", 2, 0x00000010},
+ /* 092 */ {"Capwap-control detected (Port# 5246) ", 2, 0x00000008},
+ /* 093 */ {"Capwap-data detected (Port# 5247) ", 2, 0x00000004},
+ /* 094 */ {"L5 Soft Parsing Error ", 2, 0x00000002},
+ /* 095 */ {"IPv6 Route hdr1 present ", 2, 0x00000001},
+ /* 096 */ {NULL, 0, 0x00000000}
+};
+
+struct frame_attr_ext frame_attr_ext_arr[] = {
+ /* Frame Attribute Flags Extension */
+ /* 096 */ {"User defined soft parser bit #0 ", 0, 0x8000},
+ /* 096 */ {"User defined soft parser bit #1 ", 0, 0x4000},
+ /* 096 */ {"User defined soft parser bit #2 ", 0, 0x2000},
+ /* 096 */ {"User defined soft parser bit #3 ", 0, 0x1000},
+ /* 096 */ {"User defined soft parser bit #4 ", 0, 0x0800},
+ /* 096 */ {"User defined soft parser bit #5 ", 0, 0x0400},
+ /* 096 */ {"User defined soft parser bit #6 ", 0, 0x0200},
+ /* 096 */ {"User defined soft parser bit #7 ", 0, 0x0100},
+ /* 097 */ {"Reserved ", 0, 0x00ff},
+ /* 112 */ {NULL, 0, 0x0000}
+};
+
+#define SWAP_WORD(pr) \
+do { \
+ for (int i = 0; i < 4 ; i++) { \
+ pr[i] = pr[i] ^ pr[6 - i + 1]; \
+ pr[6 - i + 1] = pr[6 - i + 1] ^ pr[i]; \
+ pr[i] = pr[i] ^ pr[6 - i + 1]; \
+ } \
+} while (0)
+
+#define fa_print_sb() \
+do { \
+ if (rte_cpu_to_be_32(*pdw) & frm_attr->fld_mask) \
+ DPAA2_PMD_DP_DEBUG("t %s : Yes", frm_attr->fld_name); \
+} while (0)
+
+#define fa_print_sb_ext() \
+do { \
+ if (rte_cpu_to_be_16(*pw) & frm_attr_ext->fld_mask) \
+ DPAA2_PMD_DP_DEBUG("\t %s : Yes", \
+ frm_attr_ext->fld_name); \
+} while (0)
+
+#define fa_print_mb_ext() \
+do { \
+ if (rte_cpu_to_be_16(*pw) & frm_attr_ext->fld_mask) \
+ DPAA2_PMD_DP_DEBUG("\t %s : 0x%02x", \
+ frm_attr_ext->fld_name, \
+ rte_cpu_to_be_16(*pw) & frm_attr_ext->fld_mask);\
+} while (0)
+
+int dpaa2_eth_load_wriop_soft_parser(struct dpaa2_dev_priv *priv,
+ enum dpni_soft_sequence_dest dest)
+{
+ struct fsl_mc_io *dpni = priv->hw;
+ struct dpni_load_ss_cfg cfg;
+ struct dpni_drv_sparser_param sp_param;
+ uint8_t *addr;
+ int ret;
+
+ memset(&sp_param, 0, sizeof(sp_param));
+ sp_param.start_pc = priv->ss_offset;
+ sp_param.byte_code = &wriop_bytecode[0];
+ sp_param.size = sizeof(wriop_bytecode);
+
+ cfg.dest = dest;
+ cfg.ss_offset = sp_param.start_pc;
+ cfg.ss_size = sp_param.size;
+
+ addr = rte_malloc(NULL, sp_param.size, 64);
+ if (!addr) {
+ DPAA2_PMD_ERR("Memory unavailable for soft parser param\n");
+ return -1;
+ }
+
+ memcpy(addr, sp_param.byte_code, sp_param.size);
+ cfg.ss_iova = (uint64_t)(DPAA2_VADDR_TO_IOVA(addr));
+
+ ret = dpni_load_sw_sequence(dpni, CMD_PRI_LOW, priv->token, &cfg);
+ if (ret) {
+ DPAA2_PMD_ERR("dpni_load_sw_sequence failed\n");
+ rte_free(addr);
+ return ret;
+ }
+
+ priv->ss_iova = (uint64_t)(DPAA2_VADDR_TO_IOVA(addr));
+ priv->ss_offset += sp_param.size;
+ RTE_LOG(INFO, PMD, "Soft parser loaded for dpni@%d\n", priv->hw_id);
+
+ rte_free(addr);
+ return 0;
+}
+
+int dpaa2_eth_enable_wriop_soft_parser(struct dpaa2_dev_priv *priv,
+ enum dpni_soft_sequence_dest dest)
+{
+ struct fsl_mc_io *dpni = priv->hw;
+ struct dpni_enable_ss_cfg cfg;
+ uint8_t pa[3];
+ struct dpni_drv_sparser_param sp_param;
+ uint8_t *param_addr = NULL;
+ int ret;
+
+ memset(&sp_param, 0, sizeof(sp_param));
+ pa[0] = 32; /* Custom Header Length in bytes */
+ sp_param.custom_header_first = 1;
+ sp_param.param_offset = 32;
+ sp_param.param_size = 1;
+ sp_param.start_pc = priv->ss_offset;
+ sp_param.param_array = (uint8_t *)&pa[0];
+
+ cfg.dest = dest;
+ cfg.ss_offset = sp_param.start_pc;
+ cfg.set_start = sp_param.custom_header_first;
+ cfg.hxs = (uint16_t)sp_param.link_to_hard_hxs;
+ cfg.param_offset = sp_param.param_offset;
+ cfg.param_size = sp_param.param_size;
+ if (cfg.param_size) {
+ param_addr = rte_malloc(NULL, cfg.param_size, 64);
+ if (!param_addr) {
+ DPAA2_PMD_ERR("Memory unavailable for soft parser param\n");
+ return -1;
+ }
+
+ memcpy(param_addr, sp_param.param_array, cfg.param_size);
+ cfg.param_iova = (uint64_t)(DPAA2_VADDR_TO_IOVA(param_addr));
+ priv->ss_param_iova = cfg.param_iova;
+ } else {
+ cfg.param_iova = 0;
+ }
+
+ ret = dpni_enable_sw_sequence(dpni, CMD_PRI_LOW, priv->token, &cfg);
+ if (ret) {
+ DPAA2_PMD_ERR("dpni_enable_sw_sequence failed for dpni%d\n",
+ priv->hw_id);
+ rte_free(param_addr);
+ return ret;
+ }
+
+ rte_free(param_addr);
+ RTE_LOG(INFO, PMD, "Soft parser enabled for dpni@%d\n", priv->hw_id);
+ return 0;
+}
diff --git a/drivers/net/dpaa2/dpaa2_sparser.h b/drivers/net/dpaa2/dpaa2_sparser.h
new file mode 100644
index 000000000..365b8062a
--- /dev/null
+++ b/drivers/net/dpaa2/dpaa2_sparser.h
@@ -0,0 +1,206 @@
+/* * SPDX-License-Identifier: BSD-3-Clause
+ * Copyright 2018-2019 NXP
+ */
+
+/**
+ * @file dpaa2_sparser.h
+ *
+ * @brief Soft parser related macros & functions support for DPAA2 device
+ * framework based applications.
+ *
+ */
+
+#ifndef _DPAA2_SPARSER_H
+#define _DPAA2_SPARSER_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define WRIOP_SS_INITIALIZER(priv) \
+do { \
+ /* Base offset of parse profile memory in WRIOP */ \
+ (priv)->ss_offset = 0x20; \
+ (priv)->ss_iova = (size_t)NULL; \
+ (priv)->ss_param_iova = (size_t)NULL; \
+} while (0)
+
+/**************************************************************************/
+/*
+ * @enum parser_starting_hxs_code
+ * @Description PARSER Starting HXS code
+ */
+/***************************************************************************/
+enum parser_starting_hxs_code {
+ /** Ethernet Starting HXS coding */
+ PARSER_ETH_STARTING_HXS = 0x0000,
+ /** LLC+SNAP Starting HXS coding */
+ PARSER_LLC_SNAP_STARTING_HXS = 0x0001,
+ /** VLAN Starting HXS coding */
+ PARSER_VLAN_STARTING_HXS = 0x0002,
+ /** PPPoE+PPP Starting HXS coding */
+ PARSER_PPPOE_PPP_STARTING_HXS = 0x0003,
+ /** MPLS Starting HXS coding */
+ PARSER_MPLS_STARTING_HXS = 0x0004,
+ /** ARP Starting HXS coding */
+ PARSER_ARP_STARTING_HXS = 0x0005,
+ /** IP Starting HXS coding */
+ PARSER_IP_STARTING_HXS = 0x0006,
+ /** IPv4 Starting HXS coding */
+ PARSER_IPV4_STARTING_HXS = 0x0007,
+ /** IPv6 Starting HXS coding */
+ PARSER_IPV6_STARTING_HXS = 0x0008,
+ /** GRE Starting HXS coding */
+ PARSER_GRE_STARTING_HXS = 0x0009,
+ /** MinEncap Starting HXS coding */
+ PARSER_MINENCAP_STARTING_HXS = 0x000A,
+ /** Other L3 Shell Starting HXS coding */
+ PARSER_OTHER_L3_SHELL_STARTING_HXS = 0x000B,
+ /** TCP Starting HXS coding */
+ PARSER_TCP_STARTING_HXS = 0x000C,
+ /** UDP Starting HXS coding */
+ PARSER_UDP_STARTING_HXS = 0x000D,
+ /** IPSec Starting HXS coding */
+ PARSER_IPSEC_STARTING_HXS = 0x000E,
+ /** SCTP Starting HXS coding */
+ PARSER_SCTP_STARTING_HXS = 0x000F,
+ /** DCCP Starting HXS coding */
+ PARSER_DCCP_STARTING_HXS = 0x0010,
+ /** Other L4 Shell Starting HXS coding */
+ PARSER_OTHER_L4_SHELL_STARTING_HXS = 0x0011,
+ /** GTP Starting HXS coding */
+ PARSER_GTP_STARTING_HXS = 0x0012,
+ /** ESP Starting HXS coding */
+ PARSER_ESP_STARTING_HXS = 0x0013,
+ /** VXLAN Starting HXS coding */
+ PARSER_VXLAN_STARTING_HXS = 0x0014,
+ /** L5 (and above) Shell Starting HXS coding */
+ PARSER_L5_SHELL_STARTING_HXS = 0x001E,
+ /** Final Shell Starting HXS coding */
+ PARSER_FINAL_SHELL_STARTING_HXS = 0x001F
+};
+
+/**************************************************************************/
+/*
+ * @Description struct dpni_drv_sparser_param - Structure representing the
+ * information needed to activate(enable) a Soft Parser.
+ */
+/***************************************************************************/
+
+struct dpni_drv_sparser_param {
+ /* The "custom_header_first" must be set if the custom header to parse
+ * is the first header in the packet, otherwise "custom_header_first"
+ * must be cleared.
+ */
+ uint8_t custom_header_first;
+ /* Hard HXS on which a soft parser is activated. This must be
+ * configured.
+ * if the header to parse is not the first header in the packet.
+ */
+ enum parser_starting_hxs_code link_to_hard_hxs;
+ /* Soft Sequence Start PC */
+ uint16_t start_pc;
+ /* Soft Sequence byte-code */
+ uint8_t *byte_code;
+ /* Soft Sequence size */
+ uint16_t size;
+ /* Pointer to the Parameters Array of the SP */
+ uint8_t *param_array;
+ /* Parameters offset */
+ uint8_t param_offset;
+ /* Parameters size */
+ uint8_t param_size;
+};
+
+struct sp_parse_result {
+ /* Next header */
+ uint16_t nxt_hdr;
+ /* Frame Attribute Flags Extension */
+ uint16_t frame_attribute_flags_extension;
+ /* Frame Attribute Flags (part 1) */
+ uint32_t frame_attribute_flags_1;
+ /* Frame Attribute Flags (part 2) */
+ uint32_t frame_attribute_flags_2;
+ /* Frame Attribute Flags (part 3) */
+ uint32_t frame_attribute_flags_3;
+ /* Shim Offset 1 */
+ uint8_t shim_offset_1;
+ /* Shim Offset 2 */
+ uint8_t shim_offset_2;
+ /* Outer IP protocol field offset */
+ uint8_t ip_1_pid_offset;
+ /* Ethernet offset */
+ uint8_t eth_offset;
+ /* LLC+SNAP offset */
+ uint8_t llc_snap_offset;
+ /* First VLAN's TCI field offset*/
+ uint8_t vlan_tci1_offset;
+ /* Last VLAN's TCI field offset*/
+ uint8_t vlan_tcin_offset;
+ /* Last Ethertype offset*/
+ uint8_t last_etype_offset;
+ /* PPPoE offset */
+ uint8_t pppoe_offset;
+ /* First MPLS offset */
+ uint8_t mpls_offset_1;
+ /* Last MPLS offset */
+ uint8_t mpls_offset_n;
+ /* Layer 3 (Outer IP, ARP, FCoE or FIP) offset */
+ uint8_t l3_offset;
+ /* Inner IP or MinEncap offset*/
+ uint8_t ipn_or_minencap_offset;
+ /* GRE offset */
+ uint8_t gre_offset;
+ /* Layer 4 offset*/
+ uint8_t l4_offset;
+ /* Layer 5 offset */
+ uint8_t l5_offset;
+ /* Routing header offset of 1st IPv6 header */
+ uint8_t routing_hdr_offset1;
+ /* Routing header offset of 2nd IPv6 header */
+ uint8_t routing_hdr_offset2;
+ /* Next header offset */
+ uint8_t nxt_hdr_offset;
+ /* IPv6 fragmentable part offset */
+ uint8_t ipv6_frag_offset;
+ /* Frame's untouched running sum, input to parser */
+ uint16_t gross_running_sum;
+ /* Running Sum */
+ uint16_t running_sum;
+ /* Parse Error code */
+ uint8_t parse_error_code;
+ /* Offset to the next header field before IPv6 fragment extension */
+ uint8_t nxt_hdr_before_ipv6_frag_ext;
+ /* Inner IP Protocol field offset */
+ uint8_t ip_n_pid_offset;
+ /* Reserved for Soft parsing context*/
+ uint8_t soft_parsing_context[21];
+};
+
+struct frame_attr {
+ const char *fld_name;
+ uint8_t faf_offset;
+ uint32_t fld_mask;
+};
+
+struct frame_attr_ext {
+ const char *fld_name;
+ uint8_t faf_ext_offset;
+ uint16_t fld_mask;
+};
+
+
+struct parse_err {
+ uint16_t code;
+ const char *err_name;
+};
+
+/* Macro definitions */
+#define IS_ONE_BIT_FIELD(_mask) \
+(!((_mask) & ((_mask) - 1)) || (_mask == 1))
+
+int dpaa2_eth_load_wriop_soft_parser(struct dpaa2_dev_priv *priv,
+ enum dpni_soft_sequence_dest dest);
+int dpaa2_eth_enable_wriop_soft_parser(struct dpaa2_dev_priv *priv,
+ enum dpni_soft_sequence_dest dest);
+#endif /* _DPAA2_SPARSER_H_ */
diff --git a/drivers/net/dpaa2/meson.build b/drivers/net/dpaa2/meson.build
index fc311e9f7..1a4ab212c 100644
--- a/drivers/net/dpaa2/meson.build
+++ b/drivers/net/dpaa2/meson.build
@@ -14,6 +14,7 @@ sources = files('base/dpaa2_hw_dpni.c',
'dpaa2_ethdev.c',
'dpaa2_flow.c',
'dpaa2_rxtx.c',
+ 'dpaa2_sparser.c',
'mc/dpkg.c',
'mc/dpdmux.c',
'mc/dpni.c')
--
2.17.1
next prev parent reply other threads:[~2019-08-29 10:46 UTC|newest]
Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-27 7:07 [dpdk-dev] [PATCH v1 00/30] Enhancements and fixes in NXP dpaax drivers and fsl-mc bus Sachin Saxena
2019-08-27 7:07 ` [dpdk-dev] [PATCH v1 01/30] bus/dpaa: fix DPAA SEC blacklist case Sachin Saxena
2019-08-27 7:07 ` [dpdk-dev] [PATCH v1 02/30] net/dpaa: improve the Rx offload debug message Sachin Saxena
2019-08-27 7:07 ` [dpdk-dev] [PATCH v1 03/30] bus/dpaa: remove un-necessary thread affinity Sachin Saxena
2019-08-27 7:07 ` [dpdk-dev] [PATCH v1 04/30] bus/dpaa: decouple fq portal alloc and init Sachin Saxena
2019-08-27 7:07 ` [dpdk-dev] [PATCH v1 05/30] net/dpaa: support Rx interrupt handler Sachin Saxena
2019-08-27 7:07 ` [dpdk-dev] [PATCH v1 06/30] net/dpaa: support for Rx interrupt enable and disable Sachin Saxena
2019-08-27 7:07 ` [dpdk-dev] [PATCH v1 07/30] net/dpaa: add SG support in Tx for non DPAA buffer Sachin Saxena
2019-08-27 7:07 ` [dpdk-dev] [PATCH v1 08/30] net/dpaa: reduce debug messages Sachin Saxena
2019-08-27 7:07 ` [dpdk-dev] [PATCH v1 09/30] net/dpaa2: improve the Rx offload debug message Sachin Saxena
2019-08-27 7:07 ` [dpdk-dev] [PATCH v1 10/30] common/dpaax: reduce debug mesages Sachin Saxena
2019-08-27 7:07 ` [dpdk-dev] [PATCH v1 11/30] mempool/dpaa: reduce debug messages Sachin Saxena
2019-08-27 7:07 ` [dpdk-dev] [PATCH v1 12/30] net/dpaa2: realign Rx offload support types Sachin Saxena
2019-08-27 7:07 ` [dpdk-dev] [PATCH v1 13/30] net/dpaa2: enable Rx offload for timestamp Sachin Saxena
2019-08-27 7:07 ` [dpdk-dev] [PATCH v1 14/30] net/dpaa2: support L2 payload based RSS distribution Sachin Saxena
2019-08-27 7:07 ` [dpdk-dev] [PATCH v1 15/30] net/dpaa2: add optional non-prefetch Rx mode Sachin Saxena
2019-08-27 7:07 ` [dpdk-dev] [PATCH v1 16/30] net/dpaa2: add taildrop support on frame count basis Sachin Saxena
2019-08-27 7:07 ` [dpdk-dev] [PATCH v1 17/30] net/dpaa2: add cgr counters in xtra stats Sachin Saxena
2019-08-27 7:07 ` [dpdk-dev] [PATCH v1 18/30] net/dpaa2: add support for config max Rx length in HW Sachin Saxena
2019-08-27 7:07 ` [dpdk-dev] [PATCH v1 19/30] net/dpaa2: use LFQIDs in Tx instead of qdid Sachin Saxena
2019-08-27 7:07 ` [dpdk-dev] [PATCH v1 20/30] net/dpaa2: support dpdmux classification on eth type Sachin Saxena
2019-08-27 7:07 ` [dpdk-dev] [PATCH v1 21/30] net/dpaa2: add Tx confirmation mode support Sachin Saxena
2019-08-27 7:07 ` [dpdk-dev] [PATCH v1 22/30] net/dpaa2: add timestamp support Sachin Saxena
2019-08-27 7:07 ` [dpdk-dev] [PATCH v1 23/30] net/dpaa2: add dprtc sub-module Sachin Saxena
2019-08-27 7:07 ` [dpdk-dev] [PATCH v1 24/30] net/dpaa2: add ptp driver Sachin Saxena
2019-08-27 7:07 ` [dpdk-dev] [PATCH v1 25/30] bus/fslmc: update PA-VA dpaax library only in PA mode Sachin Saxena
2019-08-27 7:07 ` [dpdk-dev] [PATCH v1 26/30] bus/fslmc: check for Dma map in primary process only Sachin Saxena
2019-08-27 7:07 ` [dpdk-dev] [PATCH v1 27/30] bus/fslmc: support multi vfio group Sachin Saxena
2019-08-27 7:07 ` [dpdk-dev] [PATCH v1 28/30] net/dpaa2: support separate MC portal per process Sachin Saxena
2019-08-27 7:07 ` [dpdk-dev] [PATCH v1 29/30] net/dpaa2: add support for soft parser in MC Sachin Saxena
2019-08-27 7:07 ` [dpdk-dev] [PATCH v1 30/30] net/dpaa2: add soft parser driver Sachin Saxena
2019-08-29 10:27 ` [dpdk-dev] [PATCH v2 00/30] Enhancements and fixes in NXP dpaax drivers and fsl-mc bus Sachin Saxena
2019-08-29 10:27 ` [dpdk-dev] [PATCH v2 01/30] bus/dpaa: fix DPAA SEC blacklist case Sachin Saxena
2019-08-29 10:27 ` [dpdk-dev] [PATCH v2 02/30] net/dpaa: improve the Rx offload debug message Sachin Saxena
2019-08-29 10:27 ` [dpdk-dev] [PATCH v2 03/30] bus/dpaa: remove un-necessary thread affinity Sachin Saxena
2019-09-30 11:51 ` Hemant Agrawal
2019-08-29 10:27 ` [dpdk-dev] [PATCH v2 04/30] bus/dpaa: decouple fq portal alloc and init Sachin Saxena
2019-09-30 11:52 ` Hemant Agrawal
2019-10-03 7:52 ` Ferruh Yigit
2019-10-03 9:42 ` Nipun Gupta
2019-08-29 10:27 ` [dpdk-dev] [PATCH v2 05/30] net/dpaa: support Rx interrupt handler Sachin Saxena
2019-09-30 11:51 ` Hemant Agrawal
2019-08-29 10:27 ` [dpdk-dev] [PATCH v2 06/30] net/dpaa: support for Rx interrupt enable and disable Sachin Saxena
2019-09-30 11:52 ` Hemant Agrawal
2019-08-29 10:27 ` [dpdk-dev] [PATCH v2 07/30] net/dpaa: add SG support in Tx for non DPAA buffer Sachin Saxena
2019-10-03 8:26 ` Hemant Agrawal
2019-08-29 10:27 ` [dpdk-dev] [PATCH v2 08/30] net/dpaa: reduce debug messages Sachin Saxena
2019-08-29 10:27 ` [dpdk-dev] [PATCH v2 09/30] net/dpaa2: improve the Rx offload debug message Sachin Saxena
2019-08-29 10:27 ` [dpdk-dev] [PATCH v2 10/30] common/dpaax: reduce debug mesages Sachin Saxena
2019-08-29 10:27 ` [dpdk-dev] [PATCH v2 11/30] mempool/dpaa: reduce debug messages Sachin Saxena
2019-08-29 10:27 ` [dpdk-dev] [PATCH v2 12/30] net/dpaa2: realign Rx offload support types Sachin Saxena
2019-08-29 10:27 ` [dpdk-dev] [PATCH v2 13/30] net/dpaa2: enable Rx offload for timestamp Sachin Saxena
2019-08-29 10:27 ` [dpdk-dev] [PATCH v2 14/30] net/dpaa2: support L2 payload based RSS distribution Sachin Saxena
2019-08-29 10:27 ` [dpdk-dev] [PATCH v2 15/30] net/dpaa2: add optional non-prefetch Rx mode Sachin Saxena
2019-10-03 8:26 ` Hemant Agrawal
2019-08-29 10:27 ` [dpdk-dev] [PATCH v2 16/30] net/dpaa2: add taildrop support on frame count basis Sachin Saxena
2019-08-29 10:27 ` [dpdk-dev] [PATCH v2 17/30] net/dpaa2: add cgr counters in xtra stats Sachin Saxena
2019-08-29 10:27 ` [dpdk-dev] [PATCH v2 18/30] net/dpaa2: add support for config max Rx length in HW Sachin Saxena
2019-08-29 10:27 ` [dpdk-dev] [PATCH v2 19/30] net/dpaa2: use LFQIDs in Tx instead of qdid Sachin Saxena
2019-08-29 10:27 ` [dpdk-dev] [PATCH v2 20/30] net/dpaa2: support dpdmux classification on eth type Sachin Saxena
2019-08-29 10:27 ` [dpdk-dev] [PATCH v2 21/30] net/dpaa2: add Tx confirmation mode support Sachin Saxena
2019-09-30 11:53 ` Hemant Agrawal
2019-08-29 10:27 ` [dpdk-dev] [PATCH v2 22/30] net/dpaa2: add timestamp support Sachin Saxena
2019-09-30 11:53 ` Hemant Agrawal
2019-08-29 10:27 ` [dpdk-dev] [PATCH v2 23/30] net/dpaa2: add dprtc sub-module Sachin Saxena
2019-10-03 8:26 ` Hemant Agrawal
2019-08-29 10:27 ` [dpdk-dev] [PATCH v2 24/30] net/dpaa2: add ptp driver Sachin Saxena
2019-10-03 8:26 ` Hemant Agrawal
2019-08-29 10:27 ` [dpdk-dev] [PATCH v2 25/30] bus/fslmc: update PA-VA dpaax library only in PA mode Sachin Saxena
2019-08-29 10:27 ` [dpdk-dev] [PATCH v2 26/30] bus/fslmc: check for Dma map in primary process only Sachin Saxena
2019-08-29 10:27 ` [dpdk-dev] [PATCH v2 27/30] bus/fslmc: support multi vfio group Sachin Saxena
2019-08-29 10:27 ` [dpdk-dev] [PATCH v2 28/30] net/dpaa2: support separate MC portal per process Sachin Saxena
2019-08-29 10:27 ` [dpdk-dev] [PATCH v2 29/30] net/dpaa2: add support for soft parser in MC Sachin Saxena
2019-08-29 10:27 ` Sachin Saxena [this message]
2019-10-03 8:26 ` [dpdk-dev] [PATCH v2 30/30] net/dpaa2: add soft parser driver Hemant Agrawal
2019-10-03 11:33 ` [dpdk-dev] [PATCH v2 00/30] Enhancements and fixes in NXP dpaax drivers and fsl-mc bus Ferruh Yigit
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