From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 207A0A2E1B for ; Tue, 3 Sep 2019 12:59:58 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 2DD0D1E925; Tue, 3 Sep 2019 12:59:43 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id C5C3F1E9FA for ; Tue, 3 Sep 2019 12:59:41 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x83AxbJa028710; Tue, 3 Sep 2019 03:59:37 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=11VgNgwvigpTp1KsRAWy9Ik4NDxqn0++ccgUyH4HPU8=; b=lSPlEoytgKYoJweH6+D7VbplVpw4bm10VdrtJ3E+U2RoT8ro90gm68/yR3K6FL9Q4PkX 1yjbrVOWGZsOWExZLSDvJQNO2Z79RqgKMlEYHEl9QIkZQW3b6Wti/MTYm8A9uSL+6q9m Tp9kKMP25Ttj+I8DTu3vIX5v8gXgYFwRYpY33jBXFu5PgjtgjxCo/i0/Kx+z9OAneVCT Tp8Pp9fQqcV1+EqlhP6g7Z4yIc3zSllrFhFDWvqTkf8F52tWXH6hTjDzFL8ztqV1C2BB s80uJggwUi19glOIbDCGuzWuwqrSwBCd+RGd8GfWJg5dDW9fWPJH327UochTZv63ce37 GQ== Received: from sc-exch04.marvell.com ([199.233.58.184]) by mx0b-0016f401.pphosted.com with ESMTP id 2uqrdm957q-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Tue, 03 Sep 2019 03:59:37 -0700 Received: from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Tue, 3 Sep 2019 03:59:35 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Tue, 3 Sep 2019 03:59:35 -0700 Received: from jerin-lab.marvell.com (jerin-lab.marvell.com [10.28.34.14]) by maili.marvell.com (Postfix) with ESMTP id EEF1D3F7044; Tue, 3 Sep 2019 03:59:31 -0700 (PDT) From: To: CC: , , , , Jerin Jacob Date: Tue, 3 Sep 2019 16:29:34 +0530 Message-ID: <20190903105938.33231-5-jerinj@marvell.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20190903105938.33231-1-jerinj@marvell.com> References: <20190903105938.33231-1-jerinj@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.70,1.0.8 definitions=2019-09-03_01:2019-09-03,2019-09-03 signatures=0 Subject: [dpdk-dev] [PATCH 4/8] bpf/arm64: add logical operations X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Jerin Jacob Add OR, AND, NEG, XOR, shift operations for immediate and source register variants. Signed-off-by: Jerin Jacob --- lib/librte_bpf/bpf_jit_arm64.c | 189 +++++++++++++++++++++++++++++++++ 1 file changed, 189 insertions(+) diff --git a/lib/librte_bpf/bpf_jit_arm64.c b/lib/librte_bpf/bpf_jit_arm64.c index 5d2ce378c..fcde3583b 100644 --- a/lib/librte_bpf/bpf_jit_arm64.c +++ b/lib/librte_bpf/bpf_jit_arm64.c @@ -43,6 +43,17 @@ struct a64_jit_ctx { uint8_t foundcall; /* Found EBPF_CALL class code in eBPF pgm */ }; +static int +check_immr_imms(bool is64, uint8_t immr, uint8_t imms) +{ + const unsigned int width = is64 ? 64 : 32; + + if (immr >= width || imms >= width) + return 1; + + return 0; +} + static int check_mov_hw(bool is64, const uint8_t val) { @@ -288,6 +299,12 @@ emit_sub(struct a64_jit_ctx *ctx, bool is64, uint8_t rd, uint8_t rm) emit_add_sub(ctx, is64, rd, rd, rm, A64_SUB); } +static void +emit_neg(struct a64_jit_ctx *ctx, bool is64, uint8_t rd) +{ + emit_add_sub(ctx, is64, rd, A64_ZR, rd, A64_SUB); +} + static void emit_mul(struct a64_jit_ctx *ctx, bool is64, uint8_t rd, uint8_t rm) { @@ -304,6 +321,9 @@ emit_mul(struct a64_jit_ctx *ctx, bool is64, uint8_t rd, uint8_t rm) } #define A64_UDIV 0x2 +#define A64_LSLV 0x8 +#define A64_LSRV 0x9 +#define A64_ASRV 0xA static void emit_data_process_two_src(struct a64_jit_ctx *ctx, bool is64, uint8_t rd, uint8_t rn, uint8_t rm, uint16_t op) @@ -327,6 +347,107 @@ emit_div(struct a64_jit_ctx *ctx, bool is64, uint8_t rd, uint8_t rm) emit_data_process_two_src(ctx, is64, rd, rd, rm, A64_UDIV); } +static void +emit_lslv(struct a64_jit_ctx *ctx, bool is64, uint8_t rd, uint8_t rm) +{ + emit_data_process_two_src(ctx, is64, rd, rd, rm, A64_LSLV); +} + +static void +emit_lsrv(struct a64_jit_ctx *ctx, bool is64, uint8_t rd, uint8_t rm) +{ + emit_data_process_two_src(ctx, is64, rd, rd, rm, A64_LSRV); +} + +static void +emit_asrv(struct a64_jit_ctx *ctx, bool is64, uint8_t rd, uint8_t rm) +{ + emit_data_process_two_src(ctx, is64, rd, rd, rm, A64_ASRV); +} + +#define A64_UBFM 0x2 +#define A64_SBFM 0x0 +static void +emit_bitfield(struct a64_jit_ctx *ctx, bool is64, uint8_t rd, uint8_t rn, + uint8_t immr, uint8_t imms, uint16_t op) + +{ + uint32_t insn; + + insn = (!!is64) << 31; + if (insn) + insn |= 1 << 22; /* Set N bit when is64 is set */ + insn |= op << 29; + insn |= 0x26 << 23; + insn |= immr << 16; + insn |= imms << 10; + insn |= rn << 5; + insn |= rd; + + emit_insn(ctx, insn, check_reg(rd) || check_reg(rn) || + check_immr_imms(is64, immr, imms)); +} +static void +emit_lsl(struct a64_jit_ctx *ctx, bool is64, uint8_t rd, uint8_t imm) +{ + const unsigned int width = is64 ? 64 : 32; + uint8_t imms, immr; + + immr = (width - imm) & (width - 1); + imms = width - 1 - imm; + + emit_bitfield(ctx, is64, rd, rd, immr, imms, A64_UBFM); +} + +static void +emit_lsr(struct a64_jit_ctx *ctx, bool is64, uint8_t rd, uint8_t imm) +{ + emit_bitfield(ctx, is64, rd, rd, imm, is64 ? 63 : 31, A64_UBFM); +} + +static void +emit_asr(struct a64_jit_ctx *ctx, bool is64, uint8_t rd, uint8_t imm) +{ + emit_bitfield(ctx, is64, rd, rd, imm, is64 ? 63 : 31, A64_SBFM); +} + +#define A64_AND 0 +#define A64_OR 1 +#define A64_XOR 2 +static void +emit_logical(struct a64_jit_ctx *ctx, bool is64, uint8_t rd, + uint8_t rm, uint16_t op) +{ + uint32_t insn; + + insn = (!!is64) << 31; + insn |= op << 29; + insn |= 0x50 << 21; + insn |= rm << 16; + insn |= rd << 5; + insn |= rd; + + emit_insn(ctx, insn, check_reg(rd) || check_reg(rm)); +} + +static void +emit_or(struct a64_jit_ctx *ctx, bool is64, uint8_t rd, uint8_t rm) +{ + emit_logical(ctx, is64, rd, rm, A64_OR); +} + +static void +emit_and(struct a64_jit_ctx *ctx, bool is64, uint8_t rd, uint8_t rm) +{ + emit_logical(ctx, is64, rd, rm, A64_AND); +} + +static void +emit_xor(struct a64_jit_ctx *ctx, bool is64, uint8_t rd, uint8_t rm) +{ + emit_logical(ctx, is64, rd, rm, A64_XOR); +} + static void emit_msub(struct a64_jit_ctx *ctx, bool is64, uint8_t rd, uint8_t rn, uint8_t rm, uint8_t ra) @@ -707,6 +828,74 @@ emit(struct a64_jit_ctx *ctx, struct rte_bpf *bpf) emit_mov_imm(ctx, is64, tmp1, imm); emit_mod(ctx, is64, tmp2, dst, tmp1); break; + /* dst |= src */ + case (BPF_ALU | BPF_OR | BPF_X): + case (EBPF_ALU64 | BPF_OR | BPF_X): + emit_or(ctx, is64, dst, src); + break; + /* dst |= imm */ + case (BPF_ALU | BPF_OR | BPF_K): + case (EBPF_ALU64 | BPF_OR | BPF_K): + emit_mov_imm(ctx, is64, tmp1, imm); + emit_or(ctx, is64, dst, tmp1); + break; + /* dst &= src */ + case (BPF_ALU | BPF_AND | BPF_X): + case (EBPF_ALU64 | BPF_AND | BPF_X): + emit_and(ctx, is64, dst, src); + break; + /* dst &= imm */ + case (BPF_ALU | BPF_AND | BPF_K): + case (EBPF_ALU64 | BPF_AND | BPF_K): + emit_mov_imm(ctx, is64, tmp1, imm); + emit_and(ctx, is64, dst, tmp1); + break; + /* dst ^= src */ + case (BPF_ALU | BPF_XOR | BPF_X): + case (EBPF_ALU64 | BPF_XOR | BPF_X): + emit_xor(ctx, is64, dst, src); + break; + /* dst ^= imm */ + case (BPF_ALU | BPF_XOR | BPF_K): + case (EBPF_ALU64 | BPF_XOR | BPF_K): + emit_mov_imm(ctx, is64, tmp1, imm); + emit_xor(ctx, is64, dst, tmp1); + break; + /* dst = -dst */ + case (BPF_ALU | BPF_NEG): + case (EBPF_ALU64 | BPF_NEG): + emit_neg(ctx, is64, dst); + break; + /* dst <<= src */ + case BPF_ALU | BPF_LSH | BPF_X: + case EBPF_ALU64 | BPF_LSH | BPF_X: + emit_lslv(ctx, is64, dst, src); + break; + /* dst <<= imm */ + case BPF_ALU | BPF_LSH | BPF_K: + case EBPF_ALU64 | BPF_LSH | BPF_K: + emit_lsl(ctx, is64, dst, imm); + break; + /* dst >>= src */ + case BPF_ALU | BPF_RSH | BPF_X: + case EBPF_ALU64 | BPF_RSH | BPF_X: + emit_lsrv(ctx, is64, dst, src); + break; + /* dst >>= imm */ + case BPF_ALU | BPF_RSH | BPF_K: + case EBPF_ALU64 | BPF_RSH | BPF_K: + emit_lsr(ctx, is64, dst, imm); + break; + /* dst >>= src (arithmetic) */ + case BPF_ALU | EBPF_ARSH | BPF_X: + case EBPF_ALU64 | EBPF_ARSH | BPF_X: + emit_asrv(ctx, is64, dst, src); + break; + /* dst >>= imm (arithmetic) */ + case BPF_ALU | EBPF_ARSH | BPF_K: + case EBPF_ALU64 | EBPF_ARSH | BPF_K: + emit_asr(ctx, is64, dst, imm); + break; /* Return r0 */ case (BPF_JMP | EBPF_EXIT): emit_epilogue(ctx); -- 2.23.0