From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4E3D0A0471 for ; Mon, 9 Sep 2019 11:34:14 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 2B6F81DFF2; Mon, 9 Sep 2019 11:34:13 +0200 (CEST) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by dpdk.org (Postfix) with ESMTP id 9D6BE1DFEE for ; Mon, 9 Sep 2019 11:34:11 +0200 (CEST) X-Amp-Result: UNKNOWN X-Amp-Original-Verdict: FILE UNKNOWN X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 09 Sep 2019 02:34:10 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,484,1559545200"; d="scan'208";a="183764381" Received: from yexl-server.sh.intel.com (HELO localhost) ([10.67.117.5]) by fmsmga008.fm.intel.com with ESMTP; 09 Sep 2019 02:34:09 -0700 Date: Mon, 9 Sep 2019 17:31:59 +0800 From: Ye Xiaolong To: "Wang, Ying A" Cc: "Zhang, Qi Z" , "Yang, Qiming" , "dev@dpdk.org" , "Zhao1, Wei" Message-ID: <20190909093159.GC20737@intel.com> References: <20190903221522.151382-1-ying.a.wang@intel.com> <20190903221522.151382-3-ying.a.wang@intel.com> <20190908155541.GH110251@intel.com> <44DE8E8A53B4014CA1985CEE86C07F2A0B989E2C@SHSMSX101.ccr.corp.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <44DE8E8A53B4014CA1985CEE86C07F2A0B989E2C@SHSMSX101.ccr.corp.intel.com> User-Agent: Mutt/1.9.4 (2018-02-28) Subject: Re: [dpdk-dev] [PATCH 2/4] net/ice: rework for generic flow enabling X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On 09/09, Wang, Ying A wrote: [snip] >> >+ if (ad->devargs.pipeline_mode_support) { >> >+ if (0 == attr->priority) >> >+ ice_pipeline_stage = >> >+ ICE_FLOW_CLASSIFY_STAGE_PERMISSION; >> >+ else >> >+ ice_pipeline_stage = >> >+ ICE_FLOW_CLASSIFY_STAGE_DISTRIBUTOR; >> >+ } else { >> >+ ice_pipeline_stage = >> >+ ICE_FLOW_CLASSIFY_STAGE_DISTRIBUTOR_ONLY; >> >> Do we really this assignment? > >Yes. We use devargs.pipeline_mode_support as a hint to decide which mode to use, 1 for pipeline mode, 0 for non-pipeline mode. >By default, non-pipeline mode is used and both switch/fdir used as distributor, switch is fdir's backup. >In pipeline mode, attr->priority is enabled, 0 for permission stage and 1 for distributor stage. > I saw ice_pipeline_stage has been set to ICE_FLOW_CLASSIFY_STAGE_DISTRIBUTOR_ONLY in its initialization, do we need to reassign it every time here. The pipeline mode won't change at runtime, right? >> >> >+ /* Not supported */ >> >+ if (attr->priority) { [snip] >> > free_flow: >> >- rte_flow_error_set(error, -ret, >> >- RTE_FLOW_ERROR_TYPE_HANDLE, NULL, >> >- "Failed to create flow."); >> >+ PMD_DRV_LOG(ERR, "Failed to create flow"); >> >> Why is this change? > >For framework has passed the "error" to each filter, rte_flow_error_set() will be used within each filter (switch/fdir/rss). >If used rte_flow_error_set() here, it will cover the error set value by each filter, so PMD_DRV_LOG is used here. > I think it makes sense, thanks for the explanation. Thanks, Xiaolong