From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 3A117A2F6B for ; Tue, 8 Oct 2019 14:52:53 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 4C60C1D17C; Tue, 8 Oct 2019 14:52:43 +0200 (CEST) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by dpdk.org (Postfix) with ESMTP id 9B4A41C128 for ; Tue, 8 Oct 2019 14:52:38 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 08 Oct 2019 05:52:38 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,270,1566889200"; d="scan'208";a="206629518" Received: from adamdybx-mobl.ger.corp.intel.com (HELO addy-VirtualBox.isw.intel.com) ([10.103.104.111]) by fmsmga001.fm.intel.com with ESMTP; 08 Oct 2019 05:52:36 -0700 From: Adam Dybkowski To: dev@dpdk.org, fiona.trahe@intel.com, arkadiuszx.kusztal@intel.com, akhil.goyal@nxp.com Cc: Adam Dybkowski Date: Tue, 8 Oct 2019 14:44:32 +0200 Message-Id: <20191008124433.22304-3-adamx.dybkowski@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191008124433.22304-1-adamx.dybkowski@intel.com> References: <20190927154739.26404-1-adamx.dybkowski@intel.com> <20191008124433.22304-1-adamx.dybkowski@intel.com> Subject: [dpdk-dev] [PATCH v3 2/3] common/qat: add new QAT GEN3 definitions X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch adds few definitions specific to GEN3 QAT. Signed-off-by: Adam Dybkowski --- drivers/common/qat/qat_adf/icp_qat_fw_la.h | 19 +++++++++++++++---- drivers/common/qat/qat_adf/icp_qat_hw.h | 19 +++++++++++++++++++ 2 files changed, 34 insertions(+), 4 deletions(-) diff --git a/drivers/common/qat/qat_adf/icp_qat_fw_la.h b/drivers/common/qat/qat_adf/icp_qat_fw_la.h index c33bc3fe7..38891eb1f 100644 --- a/drivers/common/qat/qat_adf/icp_qat_fw_la.h +++ b/drivers/common/qat/qat_adf/icp_qat_fw_la.h @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) - * Copyright(c) 2015-2018 Intel Corporation + * Copyright(c) 2015-2019 Intel Corporation */ #ifndef _ICP_QAT_FW_LA_H_ #define _ICP_QAT_FW_LA_H_ @@ -34,6 +34,9 @@ struct icp_qat_fw_la_bulk_req { struct icp_qat_fw_comn_req_cd_ctrl cd_ctrl; }; +#define QAT_FW_LA_SINGLE_PASS_PROTO_FLAG_BITPOS 13 +#define ICP_QAT_FW_LA_SINGLE_PASS_PROTO 1 +#define QAT_FW_LA_SINGLE_PASS_PROTO_FLAG_MASK 0x1 #define ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS 1 #define ICP_QAT_FW_LA_GCM_IV_LEN_NOT_12_OCTETS 0 #define QAT_FW_LA_ZUC_3G_PROTO_FLAG_BITPOS 12 @@ -152,6 +155,10 @@ struct icp_qat_fw_la_bulk_req { QAT_FIELD_SET(flags, val, QAT_FW_LA_ZUC_3G_PROTO_FLAG_BITPOS, \ QAT_FW_LA_ZUC_3G_PROTO_FLAG_MASK) +#define ICP_QAT_FW_LA_SINGLE_PASS_PROTO_FLAG_SET(flags, val) \ + QAT_FIELD_SET(flags, val, QAT_FW_LA_SINGLE_PASS_PROTO_FLAG_BITPOS, \ + QAT_FW_LA_SINGLE_PASS_PROTO_FLAG_MASK) + #define ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(flags, val) \ QAT_FIELD_SET(flags, val, QAT_LA_GCM_IV_LEN_FLAG_BITPOS, \ QAT_LA_GCM_IV_LEN_FLAG_MASK) @@ -267,8 +274,7 @@ struct icp_qat_fw_cipher_auth_cd_ctrl_hdr { #define ICP_QAT_FW_AUTH_HDR_FLAG_DO_NESTED 1 #define ICP_QAT_FW_AUTH_HDR_FLAG_NO_NESTED 0 #define ICP_QAT_FW_CCM_GCM_AAD_SZ_MAX 240 -#define ICP_QAT_FW_HASH_REQUEST_PARAMETERS_OFFSET \ - (sizeof(struct icp_qat_fw_la_cipher_req_params_t)) +#define ICP_QAT_FW_HASH_REQUEST_PARAMETERS_OFFSET 24 #define ICP_QAT_FW_CIPHER_REQUEST_PARAMETERS_OFFSET (0) struct icp_qat_fw_la_cipher_req_params { @@ -281,7 +287,12 @@ struct icp_qat_fw_la_cipher_req_params { uint64_t resrvd1; } s; } u; -}; + uint64_t spc_aad_addr; + uint64_t spc_auth_res_addr; + uint16_t spc_aad_sz; + uint8_t reserved; + uint8_t spc_auth_res_sz; +} __rte_packed; struct icp_qat_fw_la_auth_req_params { uint32_t auth_off; diff --git a/drivers/common/qat/qat_adf/icp_qat_hw.h b/drivers/common/qat/qat_adf/icp_qat_hw.h index e7961dba2..cef64861f 100644 --- a/drivers/common/qat/qat_adf/icp_qat_hw.h +++ b/drivers/common/qat/qat_adf/icp_qat_hw.h @@ -212,6 +212,7 @@ enum icp_qat_hw_cipher_mode { ICP_QAT_HW_CIPHER_CBC_MODE = 1, ICP_QAT_HW_CIPHER_CTR_MODE = 2, ICP_QAT_HW_CIPHER_F8_MODE = 3, + ICP_QAT_HW_CIPHER_AEAD_MODE = 4, ICP_QAT_HW_CIPHER_XTS_MODE = 6, ICP_QAT_HW_CIPHER_MODE_DELIMITER = 7 }; @@ -244,6 +245,8 @@ enum icp_qat_hw_cipher_convert { #define QAT_CIPHER_CONVERT_MASK 0x1 #define QAT_CIPHER_DIR_BITPOS 8 #define QAT_CIPHER_DIR_MASK 0x1 +#define QAT_CIPHER_AEAD_HASH_CMP_LEN_BITPOS 10 +#define QAT_CIPHER_AEAD_HASH_CMP_LEN_MASK 0x1F #define QAT_CIPHER_MODE_F8_KEY_SZ_MULT 2 #define QAT_CIPHER_MODE_XTS_KEY_SZ_MULT 2 #define ICP_QAT_HW_CIPHER_CONFIG_BUILD(mode, algo, convert, dir) \ @@ -251,6 +254,22 @@ enum icp_qat_hw_cipher_convert { ((algo & QAT_CIPHER_ALGO_MASK) << QAT_CIPHER_ALGO_BITPOS) | \ ((convert & QAT_CIPHER_CONVERT_MASK) << QAT_CIPHER_CONVERT_BITPOS) | \ ((dir & QAT_CIPHER_DIR_MASK) << QAT_CIPHER_DIR_BITPOS)) + +#define QAT_CIPHER_AEAD_AAD_LOWER_SHIFT 24 +#define QAT_CIPHER_AEAD_AAD_UPPER_SHIFT 8 +#define QAT_CIPHER_AEAD_AAD_SIZE_LOWER_MASK 0xFF +#define QAT_CIPHER_AEAD_AAD_SIZE_UPPER_MASK 0x3F +#define QAT_CIPHER_AEAD_AAD_SIZE_BITPOS 16 +#define ICP_QAT_HW_CIPHER_CONFIG_BUILD_UPPER(aad_size) \ + ({ \ + typeof(aad_size) aad_size1 = aad_size; \ + (((((aad_size1) >> QAT_CIPHER_AEAD_AAD_UPPER_SHIFT) & \ + QAT_CIPHER_AEAD_AAD_SIZE_UPPER_MASK) << \ + QAT_CIPHER_AEAD_AAD_SIZE_BITPOS) | \ + (((aad_size1) & QAT_CIPHER_AEAD_AAD_SIZE_LOWER_MASK) << \ + QAT_CIPHER_AEAD_AAD_LOWER_SHIFT)); \ + }) + #define ICP_QAT_HW_DES_BLK_SZ 8 #define ICP_QAT_HW_3DES_BLK_SZ 8 #define ICP_QAT_HW_NULL_BLK_SZ 8 -- 2.17.1