From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1DCF7A2EFC for ; Mon, 14 Oct 2019 14:05:52 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 7F7E51C23D; Mon, 14 Oct 2019 14:05:41 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id 9C4191C211 for ; Mon, 14 Oct 2019 14:05:33 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 14 Oct 2019 05:05:33 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.67,295,1566889200"; d="scan'208";a="194204318" Received: from unknown (HELO npg-dpdk-cvl-yingwang-117d84.sh.intel.com) ([10.67.117.96]) by fmsmga008.fm.intel.com with ESMTP; 14 Oct 2019 05:05:31 -0700 From: Ying Wang To: xiaolong.ye@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, qiming.yang@intel.com, wei.zhao1@intel.com, ying.a.wang@intel.com Date: Mon, 14 Oct 2019 11:42:08 +0800 Message-Id: <20191014034211.293048-3-ying.a.wang@intel.com> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20191014034211.293048-1-ying.a.wang@intel.com> References: <20190926185524.317595-2-ying.a.wang@intel.com> <20191014034211.293048-1-ying.a.wang@intel.com> Subject: [dpdk-dev] [PATCH v4 2/5] net/ice: add devargs to control pipeline mode X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Qiming Yang Added a devarg to control the mode in generic flow API. We use none-pipeline mode by default. Signed-off-by: Qiming Yang Acked-by: Qi Zhang --- doc/guides/nics/ice.rst | 19 +++++++++++++++++++ doc/guides/rel_notes/release_19_11.rst | 2 ++ drivers/net/ice/ice_ethdev.c | 10 +++++++++- drivers/net/ice/ice_ethdev.h | 1 + 4 files changed, 31 insertions(+), 1 deletion(-) diff --git a/doc/guides/nics/ice.rst b/doc/guides/nics/ice.rst index 641f34840..933f63480 100644 --- a/doc/guides/nics/ice.rst +++ b/doc/guides/nics/ice.rst @@ -61,6 +61,25 @@ Runtime Config Options NOTE: In Safe mode, only very limited features are available, features like RSS, checksum, fdir, tunneling ... are all disabled. +- ``Generic Flow Pipeline Mode Support`` (default ``0``) + + In pipeline mode, a flow can be set at one specific stage by setting parameter + ``priority``. Currently, we support two stages: priority = 0 or !0. Flows with + priority 0 located at the first pipeline stage which typically be used as a firewall + to drop the packet on a blacklist(we called it permission stage). At this stage, + flow rules are created for the device's exact match engine: switch. Flows with priority + !0 located at the second stage, typically packets are classified here and be steered to + specific queue or queue group (we called it distribution stage), At this stage, flow + rules are created for device's flow director engine. + For none-pipeline mode, ``priority`` is ignored, a flow rule can be created as a flow director + rule or a switch rule depends on its pattern/action and the resource allocation situation, + all flows are virtually at the same pipeline stage. + By default, generic flow API is enabled in none-pipeline mode, user can choose to + use pipeline mode by setting ``devargs`` parameter ``pipeline-mode-support``, + for example:: + + -w 80:00.0,pipeline-mode-support=1 + - ``Protocol extraction for per queue`` Configure the RX queues to do protocol extraction into ``rte_mbuf::udata64`` diff --git a/doc/guides/rel_notes/release_19_11.rst b/doc/guides/rel_notes/release_19_11.rst index b93300fc6..4d1698079 100644 --- a/doc/guides/rel_notes/release_19_11.rst +++ b/doc/guides/rel_notes/release_19_11.rst @@ -94,6 +94,8 @@ New Features * Added support for handling Receive Flex Descriptor. * Added support for protocol extraction on per Rx queue. * Added support for the ``RTE_ETH_DEV_CLOSE_REMOVE`` flag. + * Generic filter enhancement + - Supported pipeline mode. * **Updated the enic driver.** diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c index 022b58c01..a4842e284 100644 --- a/drivers/net/ice/ice_ethdev.c +++ b/drivers/net/ice/ice_ethdev.c @@ -19,10 +19,12 @@ /* devargs */ #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support" +#define ICE_PIPELINE_MODE_SUPPORT_ARG "pipeline-mode-support" #define ICE_PROTO_XTR_ARG "proto_xtr" static const char * const ice_valid_args[] = { ICE_SAFE_MODE_SUPPORT_ARG, + ICE_PIPELINE_MODE_SUPPORT_ARG, ICE_PROTO_XTR_ARG, NULL }; @@ -1815,6 +1817,11 @@ static int ice_parse_devargs(struct rte_eth_dev *dev) ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG, &parse_bool, &ad->devargs.safe_mode_support); + if (ret) + goto bail; + + ret = rte_kvargs_process(kvlist, ICE_PIPELINE_MODE_SUPPORT_ARG, + &parse_bool, &ad->devargs.pipe_mode_support); bail: rte_kvargs_free(kvlist); @@ -4278,7 +4285,8 @@ RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map); RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci"); RTE_PMD_REGISTER_PARAM_STRING(net_ice, ICE_PROTO_XTR_ARG "=[queue:]" - ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>"); + ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>" + ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>"); RTE_INIT(ice_init_log) { diff --git a/drivers/net/ice/ice_ethdev.h b/drivers/net/ice/ice_ethdev.h index 182c6f611..9e0202ee6 100644 --- a/drivers/net/ice/ice_ethdev.h +++ b/drivers/net/ice/ice_ethdev.h @@ -288,6 +288,7 @@ struct ice_pf { */ struct ice_devargs { int safe_mode_support; + int pipe_mode_support; uint8_t proto_xtr[ICE_MAX_QUEUE_NUM]; }; -- 2.15.1