From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id E35C5A328D for ; Tue, 22 Oct 2019 13:55:49 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id A007D1BF25; Tue, 22 Oct 2019 13:54:49 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id A0B801BEEF for ; Tue, 22 Oct 2019 13:54:38 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x9MBdea8006226; Tue, 22 Oct 2019 04:54:38 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type : content-transfer-encoding; s=pfpt0818; bh=OD2dnjHtAjQsbUHJoI0dGlyxfDUfBSB5NH8la7/Y9Ws=; b=emf+WoQ9EUF30pts/M/bVU2NXqu/Wrx0A+3TtKrMpX3UgQaC7pKlZrzE1b0kgVtc4p6u 8rvl4gB79MHHF9I2gZE4lhPlDhE5Mz2rPbecZbqtA7w3ssk/xFCF8QG94YRoG9RYnhks 4fcRh8vIsggEOHiCuzApbqy8magdAmXUaqISCEaYEOyU6aEmkWEkRCJ6UcwvnHRpsQRw H0tqdVR0y8/9ut//npWLFqzQyDflT39X0M/AvZHq1FAkgSwXynoi3HxgXf3iV6SwVUJL nLhQlUynOXq8vTmFaPcpg7wnyNxTSlsK/dOZe/31cx66gfUKyZ3JyTmRY0C23mR8xnVJ mQ== Received: from sc-exch01.marvell.com ([199.233.58.181]) by mx0b-0016f401.pphosted.com with ESMTP id 2vsw610sud-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Tue, 22 Oct 2019 04:54:37 -0700 Received: from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Tue, 22 Oct 2019 04:54:36 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Tue, 22 Oct 2019 04:54:36 -0700 Received: from amok.marvell.com (unknown [10.95.130.40]) by maili.marvell.com (Postfix) with ESMTP id E6A1E3F7040; Tue, 22 Oct 2019 04:54:34 -0700 (PDT) From: Andrzej Ostruszka To: , Rasesh Mody , Shahed Shaikh CC: , Date: Tue, 22 Oct 2019 13:54:12 +0200 Message-ID: <20191022115412.8837-11-aostruszka@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191022115412.8837-1-aostruszka@marvell.com> References: <20190917075754.8310-1-amo@semihalf.com> <20191022115412.8837-1-aostruszka@marvell.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,1.0.8 definitions=2019-10-22_03:2019-10-22,2019-10-22 signatures=0 Subject: [dpdk-dev] [PATCH v4 10/10] net/qede: clean LTO build warnings (maybe-uninitialized) X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" During LTO build compiler reports some 'false positive' warnings about variables being possibly used uninitialized. This patch silences these warnings. Exemplary compiler warning to suppress (with LTO enabled): error: ‘transceiver_type’ may be used uninitialized in this function [-Werror=maybe-uninitialized] switch (transceiver_type) { Signed-off-by: Andrzej Ostruszka --- drivers/net/qede/base/ecore_mcp.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/net/qede/base/ecore_mcp.c b/drivers/net/qede/base/ecore_mcp.c index 6c6560688..666c0fe12 100644 --- a/drivers/net/qede/base/ecore_mcp.c +++ b/drivers/net/qede/base/ecore_mcp.c @@ -2278,7 +2278,7 @@ enum _ecore_status_t ecore_mcp_trans_speed_mask(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, u32 *p_speed_mask) { - u32 transceiver_type, transceiver_state; + u32 transceiver_type = ETH_TRANSCEIVER_TYPE_NONE, transceiver_state; ecore_mcp_get_transceiver_data(p_hwfn, p_ptt, &transceiver_state, &transceiver_type); @@ -3163,7 +3163,8 @@ enum _ecore_status_t ecore_mcp_nvm_put_file_begin(struct ecore_dev *p_dev, enum _ecore_status_t ecore_mcp_nvm_write(struct ecore_dev *p_dev, u32 cmd, u32 addr, u8 *p_buf, u32 len) { - u32 buf_idx, buf_size, nvm_cmd, nvm_offset, resp, param; + u32 buf_idx, buf_size, nvm_cmd, nvm_offset; + u32 resp = FW_MSG_CODE_ERROR, param; struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev); enum _ecore_status_t rc = ECORE_INVAL; struct ecore_ptt *p_ptt; @@ -3370,7 +3371,7 @@ enum _ecore_status_t ecore_mcp_gpio_read(struct ecore_hwfn *p_hwfn, u16 gpio, u32 *gpio_val) { enum _ecore_status_t rc = ECORE_SUCCESS; - u32 drv_mb_param = 0, rsp; + u32 drv_mb_param = 0, rsp = 0; drv_mb_param = (gpio << DRV_MB_PARAM_GPIO_NUMBER_OFFSET); @@ -3391,7 +3392,7 @@ enum _ecore_status_t ecore_mcp_gpio_write(struct ecore_hwfn *p_hwfn, u16 gpio, u16 gpio_val) { enum _ecore_status_t rc = ECORE_SUCCESS; - u32 drv_mb_param = 0, param, rsp; + u32 drv_mb_param = 0, param, rsp = 0; drv_mb_param = (gpio << DRV_MB_PARAM_GPIO_NUMBER_OFFSET) | (gpio_val << DRV_MB_PARAM_GPIO_VALUE_OFFSET); @@ -3481,7 +3482,7 @@ enum _ecore_status_t ecore_mcp_bist_clock_test(struct ecore_hwfn *p_hwfn, enum _ecore_status_t ecore_mcp_bist_nvm_test_get_num_images( struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, u32 *num_images) { - u32 drv_mb_param = 0, rsp; + u32 drv_mb_param = 0, rsp = 0; enum _ecore_status_t rc = ECORE_SUCCESS; drv_mb_param = (DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES << @@ -3865,7 +3866,7 @@ enum _ecore_status_t __ecore_mcp_resc_lock(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, struct ecore_resc_lock_params *p_params) { - u32 param = 0, mcp_resp, mcp_param; + u32 param = 0, mcp_resp = 0, mcp_param = 0; u8 opcode; enum _ecore_status_t rc; -- 2.17.1