From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 17A4DA00BE; Mon, 28 Oct 2019 15:23:36 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id CE7B01BFA2; Mon, 28 Oct 2019 15:22:33 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id BF6981BF7F for ; Mon, 28 Oct 2019 15:22:13 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x9SEKjbn005773; Mon, 28 Oct 2019 07:22:13 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type : content-transfer-encoding; s=pfpt0818; bh=2hXUR5T8rVrq832LQOtqGEb/zCGdTKkniqomGqQYu1I=; b=fNWyvxY6sVxLqcxfhCoK393WjvTeKbdeL+GyfHwTOs82EO+ZXXbrFdIsE5X+SZdgc/hE fXd97DhrpGp/l/G4wB/Z0oXDzKCCji53HFx+Ky92FDh/zVSBcJSYhv+k50/A/AXqIT7P IJOaJQv0Sp4T7weeBWGYAXVAp4oauisFSi5S9QdaBVHhtbaZ97DgCys/9Vj3CFuJbtgf 19y2VnzjARI0u+zTtS7P0Icmn3xwBI2cYr0X3Wcz5kSFktAfSrCuX6XJrq4S+papVwO6 6p78ZgYeNtAnlwizHPhNuPATxk/u2mZdr5/F0YuL05Bq4m15jCxgedWmDHcN42cHQceA Jw== Received: from sc-exch04.marvell.com ([199.233.58.184]) by mx0b-0016f401.pphosted.com with ESMTP id 2vvnnnwnfw-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 28 Oct 2019 07:22:13 -0700 Received: from SC-EXCH03.marvell.com (10.93.176.83) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Mon, 28 Oct 2019 07:22:11 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Mon, 28 Oct 2019 07:22:11 -0700 Received: from amok.marvell.com (unknown [10.95.130.103]) by maili.marvell.com (Postfix) with ESMTP id C432A3F703F; Mon, 28 Oct 2019 07:22:09 -0700 (PDT) From: Andrzej Ostruszka To: , Rasesh Mody , Shahed Shaikh CC: , Date: Mon, 28 Oct 2019 15:21:45 +0100 Message-ID: <20191028142145.3758-12-aostruszka@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191028142145.3758-1-aostruszka@marvell.com> References: <20191022115412.8837-1-aostruszka@marvell.com> <20191028142145.3758-1-aostruszka@marvell.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,1.0.8 definitions=2019-10-28_05:2019-10-25,2019-10-28 signatures=0 Subject: [dpdk-dev] [PATCH v5 11/11] net/qede: clean LTO build warnings (maybe-uninitialized) X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" During LTO build compiler reports some 'false positive' warnings about variables being possibly used uninitialized. This patch silences these warnings. Exemplary compiler warning to suppress (with LTO enabled): error: ‘transceiver_type’ may be used uninitialized in this function [-Werror=maybe-uninitialized] switch (transceiver_type) { Signed-off-by: Andrzej Ostruszka --- drivers/net/qede/base/ecore_mcp.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/net/qede/base/ecore_mcp.c b/drivers/net/qede/base/ecore_mcp.c index a5aa07438..7518765a0 100644 --- a/drivers/net/qede/base/ecore_mcp.c +++ b/drivers/net/qede/base/ecore_mcp.c @@ -2328,7 +2328,7 @@ enum _ecore_status_t ecore_mcp_trans_speed_mask(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, u32 *p_speed_mask) { - u32 transceiver_type, transceiver_state; + u32 transceiver_type = ETH_TRANSCEIVER_TYPE_NONE, transceiver_state; ecore_mcp_get_transceiver_data(p_hwfn, p_ptt, &transceiver_state, &transceiver_type); @@ -3223,7 +3223,8 @@ enum _ecore_status_t ecore_mcp_nvm_put_file_begin(struct ecore_dev *p_dev, enum _ecore_status_t ecore_mcp_nvm_write(struct ecore_dev *p_dev, u32 cmd, u32 addr, u8 *p_buf, u32 len) { - u32 buf_idx, buf_size, nvm_cmd, nvm_offset, resp, param; + u32 buf_idx, buf_size, nvm_cmd, nvm_offset; + u32 resp = FW_MSG_CODE_ERROR, param; struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev); enum _ecore_status_t rc = ECORE_INVAL; struct ecore_ptt *p_ptt; @@ -3322,7 +3323,7 @@ enum _ecore_status_t ecore_mcp_nvm_set_secure_mode(struct ecore_dev *p_dev, { struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev); struct ecore_ptt *p_ptt; - u32 resp, param; + u32 resp = 0, param; enum _ecore_status_t rc; p_ptt = ecore_ptt_acquire(p_hwfn); @@ -3430,7 +3431,7 @@ enum _ecore_status_t ecore_mcp_gpio_read(struct ecore_hwfn *p_hwfn, u16 gpio, u32 *gpio_val) { enum _ecore_status_t rc = ECORE_SUCCESS; - u32 drv_mb_param = 0, rsp; + u32 drv_mb_param = 0, rsp = 0; drv_mb_param = (gpio << DRV_MB_PARAM_GPIO_NUMBER_OFFSET); @@ -3451,7 +3452,7 @@ enum _ecore_status_t ecore_mcp_gpio_write(struct ecore_hwfn *p_hwfn, u16 gpio, u16 gpio_val) { enum _ecore_status_t rc = ECORE_SUCCESS; - u32 drv_mb_param = 0, param, rsp; + u32 drv_mb_param = 0, param, rsp = 0; drv_mb_param = (gpio << DRV_MB_PARAM_GPIO_NUMBER_OFFSET) | (gpio_val << DRV_MB_PARAM_GPIO_VALUE_OFFSET); @@ -3541,7 +3542,7 @@ enum _ecore_status_t ecore_mcp_bist_clock_test(struct ecore_hwfn *p_hwfn, enum _ecore_status_t ecore_mcp_bist_nvm_test_get_num_images( struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, u32 *num_images) { - u32 drv_mb_param = 0, rsp; + u32 drv_mb_param = 0, rsp = 0; enum _ecore_status_t rc = ECORE_SUCCESS; drv_mb_param = (DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES << @@ -3925,7 +3926,7 @@ enum _ecore_status_t __ecore_mcp_resc_lock(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, struct ecore_resc_lock_params *p_params) { - u32 param = 0, mcp_resp, mcp_param; + u32 param = 0, mcp_resp = 0, mcp_param = 0; u8 opcode; enum _ecore_status_t rc; -- 2.17.1