From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5A2BBA04C1; Tue, 12 Nov 2019 14:40:40 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id B2CAD2AB; Tue, 12 Nov 2019 14:40:38 +0100 (CET) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by dpdk.org (Postfix) with ESMTP id 52DF627D for ; Tue, 12 Nov 2019 14:40:36 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Nov 2019 05:40:35 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.68,296,1569308400"; d="scan'208";a="194316452" Received: from silpixa00399126.ir.intel.com (HELO silpixa00399126.ger.corp.intel.com) ([10.237.223.2]) by orsmga007.jf.intel.com with ESMTP; 12 Nov 2019 05:40:33 -0800 From: Bruce Richardson To: dev@dpdk.org Cc: Bruce Richardson , harry.van.haaren@intel.com Date: Tue, 12 Nov 2019 13:40:23 +0000 Message-Id: <20191112134023.52623-1-bruce.richardson@intel.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH] net/i40e: fix clang build error with 16B descriptors X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When compiling with 16B descriptor support enabled, clang compiles gave an error, complaining that the final parameter of _mm256_blend_epi32() had to be an immediate value (i.e. compile-time constant). While it appears that GCC was able to convert the constant variable value "fdir_blend_mask" into the blend call, clang was not doing so. To guarantee the use of an immediate we convert the variable value to a #define. Fixes: 7d087a0a8b8e ("net/i40e: support flow director on AVX Rx") Cc: harry.van.haaren@intel.com Signed-off-by: Bruce Richardson --- drivers/net/i40e/i40e_rxtx_vec_avx2.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/net/i40e/i40e_rxtx_vec_avx2.c b/drivers/net/i40e/i40e_rxtx_vec_avx2.c index b9f1a240c..3bcef1363 100644 --- a/drivers/net/i40e/i40e_rxtx_vec_avx2.c +++ b/drivers/net/i40e/i40e_rxtx_vec_avx2.c @@ -529,6 +529,7 @@ _recv_raw_pkts_vec_avx2(struct i40e_rx_queue *rxq, struct rte_mbuf **rx_pkts, * identifies an FDIR ID match, and zeros the RSS value * in the mbuf on FDIR match to keep mbuf data clean. */ +#define FDIR_BLEND_MASK ((1 << 3) | (1 << 7)) /* Flags: * - Take flags, shift bits to null out @@ -557,9 +558,8 @@ _recv_raw_pkts_vec_avx2(struct i40e_rx_queue *rxq, struct rte_mbuf **rx_pkts, * otherwise the mb0_1 register RSS field is zeroed. */ const __m256i fdir_zero_mask = _mm256_setzero_si256(); - const uint32_t fdir_blend_mask = (1 << 3) | (1 << 7); __m256i tmp0_1 = _mm256_blend_epi32(fdir_zero_mask, - fdir_mask, fdir_blend_mask); + fdir_mask, FDIR_BLEND_MASK); __m256i fdir_mb0_1 = _mm256_and_si256(mb0_1, fdir_mask); mb0_1 = _mm256_andnot_si256(tmp0_1, mb0_1); @@ -575,7 +575,7 @@ _recv_raw_pkts_vec_avx2(struct i40e_rx_queue *rxq, struct rte_mbuf **rx_pkts, __m256i tmp2_3 = _mm256_alignr_epi8(fdir_mask, fdir_mask, 12); __m256i fdir_mb2_3 = _mm256_and_si256(mb2_3, tmp2_3); tmp2_3 = _mm256_blend_epi32(fdir_zero_mask, tmp2_3, - fdir_blend_mask); + FDIR_BLEND_MASK); mb2_3 = _mm256_andnot_si256(tmp2_3, mb2_3); rx_pkts[i + 2]->hash.fdir.hi = _mm256_extract_epi32(fdir_mb2_3, 3); rx_pkts[i + 3]->hash.fdir.hi = _mm256_extract_epi32(fdir_mb2_3, 7); @@ -583,7 +583,7 @@ _recv_raw_pkts_vec_avx2(struct i40e_rx_queue *rxq, struct rte_mbuf **rx_pkts, __m256i tmp4_5 = _mm256_alignr_epi8(fdir_mask, fdir_mask, 8); __m256i fdir_mb4_5 = _mm256_and_si256(mb4_5, tmp4_5); tmp4_5 = _mm256_blend_epi32(fdir_zero_mask, tmp4_5, - fdir_blend_mask); + FDIR_BLEND_MASK); mb4_5 = _mm256_andnot_si256(tmp4_5, mb4_5); rx_pkts[i + 4]->hash.fdir.hi = _mm256_extract_epi32(fdir_mb4_5, 3); rx_pkts[i + 5]->hash.fdir.hi = _mm256_extract_epi32(fdir_mb4_5, 7); @@ -591,7 +591,7 @@ _recv_raw_pkts_vec_avx2(struct i40e_rx_queue *rxq, struct rte_mbuf **rx_pkts, __m256i tmp6_7 = _mm256_alignr_epi8(fdir_mask, fdir_mask, 4); __m256i fdir_mb6_7 = _mm256_and_si256(mb6_7, tmp6_7); tmp6_7 = _mm256_blend_epi32(fdir_zero_mask, tmp6_7, - fdir_blend_mask); + FDIR_BLEND_MASK); mb6_7 = _mm256_andnot_si256(tmp6_7, mb6_7); rx_pkts[i + 6]->hash.fdir.hi = _mm256_extract_epi32(fdir_mb6_7, 3); rx_pkts[i + 7]->hash.fdir.hi = _mm256_extract_epi32(fdir_mb6_7, 7); -- 2.21.0