From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 2C509A04C1; Wed, 20 Nov 2019 04:49:04 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 0B31F1BC25; Wed, 20 Nov 2019 04:48:29 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id A02782C6D for ; Wed, 20 Nov 2019 04:48:27 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id xAK3kd2L029360 for ; Tue, 19 Nov 2019 19:48:26 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=sKvBKfLxrxVZBCS6nS63ZXSnyLcbhpxIu/DCPzRKeZc=; b=I2NCHC4MCc9cGh3YmhOoQtvu8fZ2xpgOmnQ0r+ug9dx+Zckp3OzzXqxQS82VdhKxy1bT FKESQoZlAlIr4BG1lhbxo35l0Tv78UD2+7z4rT4mIa79roicJzNZCtIqIVU/9hUf1XR8 +/f92WNsHh/V+N4gyF+oSEL0Ic13QhUQk3cMldAkWCZmOAVRx+93o2SzBr/2M9+0iiBA IgdbUVzmIcFFTYP8i2j9KkOXCFFCID0Q0HEpdrgTefmRVNXGmU3iO8rpqDlXLLwTR8Gg 1dbopEfrw4ajRHPFCfH4XP7x+6U+ps1FOajUr1hqKZUeCA362qv2uH4tDEk3wUh7bOev Hg== Received: from sc-exch03.marvell.com ([199.233.58.183]) by mx0a-0016f401.pphosted.com with ESMTP id 2wc8425sv4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Tue, 19 Nov 2019 19:48:26 -0800 Received: from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Tue, 19 Nov 2019 19:48:25 -0800 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Tue, 19 Nov 2019 19:48:25 -0800 Received: from BG-LT7430.marvell.com (unknown [10.28.17.72]) by maili.marvell.com (Postfix) with ESMTP id 9E5503F703F; Tue, 19 Nov 2019 19:48:23 -0800 (PST) From: To: , Pavan Nikhilesh CC: Date: Wed, 20 Nov 2019 09:18:06 +0530 Message-ID: <20191120034808.2760-6-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191120034808.2760-1-pbhagavatula@marvell.com> References: <20191120034808.2760-1-pbhagavatula@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,18.0.572 definitions=2019-11-19_08:2019-11-15,2019-11-19 signatures=0 Subject: [dpdk-dev] [PATCH v2 5/6] event/octeontx: add appication domain validation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Add applicaton domain validation for OCTEON TX TIM vfs aka Event timer. Signed-off-by: Pavan Nikhilesh --- drivers/event/octeontx/timvf_evdev.c | 12 ++--- drivers/event/octeontx/timvf_evdev.h | 8 +--- drivers/event/octeontx/timvf_probe.c | 65 ++++++++++++++++++---------- 3 files changed, 49 insertions(+), 36 deletions(-) diff --git a/drivers/event/octeontx/timvf_evdev.c b/drivers/event/octeontx/timvf_evdev.c index abbc9a775..caa129087 100644 --- a/drivers/event/octeontx/timvf_evdev.c +++ b/drivers/event/octeontx/timvf_evdev.c @@ -231,17 +231,15 @@ timvf_ring_create(struct rte_event_timer_adapter *adptr) { char pool_name[25]; int ret; + uint8_t tim_ring_id; uint64_t nb_timers; struct rte_event_timer_adapter_conf *rcfg = &adptr->data->conf; struct timvf_ring *timr; - struct timvf_info tinfo; const char *mempool_ops; unsigned int mp_flags = 0; - if (timvf_info(&tinfo) < 0) - return -ENODEV; - - if (adptr->data->id >= tinfo.total_timvfs) + tim_ring_id = timvf_get_ring(); + if (tim_ring_id == UINT8_MAX) return -ENODEV; timr = rte_zmalloc("octeontx_timvf_priv", @@ -259,7 +257,7 @@ timvf_ring_create(struct rte_event_timer_adapter *adptr) } timr->clk_src = (int) rcfg->clk_src; - timr->tim_ring_id = adptr->data->id; + timr->tim_ring_id = tim_ring_id; timr->tck_nsec = RTE_ALIGN_MUL_CEIL(rcfg->timer_tick_ns, 10); timr->max_tout = rcfg->max_tmo_ns; timr->nb_bkts = (timr->max_tout / timr->tck_nsec); @@ -337,8 +335,10 @@ static int timvf_ring_free(struct rte_event_timer_adapter *adptr) { struct timvf_ring *timr = adptr->data->adapter_priv; + rte_mempool_free(timr->chunk_pool); rte_free(timr->bkt); + timvf_release_ring(timr->tim_ring_id); rte_free(adptr->data->adapter_priv); return 0; } diff --git a/drivers/event/octeontx/timvf_evdev.h b/drivers/event/octeontx/timvf_evdev.h index 0185593f1..d0e5921db 100644 --- a/drivers/event/octeontx/timvf_evdev.h +++ b/drivers/event/octeontx/timvf_evdev.h @@ -115,11 +115,6 @@ extern int otx_logtype_timvf; static const uint16_t nb_chunk_slots = (TIM_CHUNK_SIZE / 16) - 1; -struct timvf_info { - uint16_t domain; /* Domain id */ - uint8_t total_timvfs; /* Total timvf available in domain */ -}; - enum timvf_clk_src { TIM_CLK_SRC_SCLK = RTE_EVENT_TIMER_ADAPTER_CPU_CLK, TIM_CLK_SRC_GPIO = RTE_EVENT_TIMER_ADAPTER_EXT_CLK0, @@ -196,7 +191,8 @@ bkt_and(uint32_t rel_bkt, uint32_t nb_bkts) return rel_bkt & (nb_bkts - 1); } -int timvf_info(struct timvf_info *tinfo); +uint8_t timvf_get_ring(void); +void timvf_release_ring(uint8_t vfid); void *timvf_bar(uint8_t id, uint8_t bar); int timvf_timer_adapter_caps_get(const struct rte_eventdev *dev, uint64_t flags, uint32_t *caps, const struct rte_event_timer_adapter_ops **ops, diff --git a/drivers/event/octeontx/timvf_probe.c b/drivers/event/octeontx/timvf_probe.c index af87625fd..59bba31e8 100644 --- a/drivers/event/octeontx/timvf_probe.c +++ b/drivers/event/octeontx/timvf_probe.c @@ -20,6 +20,7 @@ #define TIM_MAX_RINGS (64) struct timvf_res { + uint8_t in_use; uint16_t domain; uint16_t vfid; void *bar0; @@ -34,50 +35,65 @@ struct timdev { static struct timdev tdev; -int -timvf_info(struct timvf_info *tinfo) +uint8_t +timvf_get_ring(void) { + uint16_t global_domain = octeontx_get_global_domain(); int i; - struct ssovf_info info; - if (tinfo == NULL) - return -EINVAL; + for (i = 0; i < tdev.total_timvfs; i++) { + if (tdev.rings[i].domain != global_domain) + continue; + if (tdev.rings[i].in_use) + continue; - if (!tdev.total_timvfs) - return -ENODEV; + tdev.rings[i].in_use = true; + return tdev.rings[i].vfid; + } - if (ssovf_info(&info) < 0) - return -EINVAL; + return UINT8_MAX; +} + +void +timvf_release_ring(uint8_t tim_ring_id) +{ + uint16_t global_domain = octeontx_get_global_domain(); + int i; for (i = 0; i < tdev.total_timvfs; i++) { - if (info.domain != tdev.rings[i].domain) { - timvf_log_err("GRP error, vfid=%d/%d domain=%d/%d %p", - i, tdev.rings[i].vfid, - info.domain, tdev.rings[i].domain, - tdev.rings[i].bar0); - return -EINVAL; - } + if (tdev.rings[i].domain != global_domain) + continue; + if (tdev.rings[i].vfid == tim_ring_id) + tdev.rings[i].in_use = false; } - - tinfo->total_timvfs = tdev.total_timvfs; - tinfo->domain = info.domain; - return 0; } void* -timvf_bar(uint8_t id, uint8_t bar) +timvf_bar(uint8_t vfid, uint8_t bar) { + uint16_t global_domain = octeontx_get_global_domain(); + struct timvf_res *res = NULL; + int i; + if (rte_eal_process_type() != RTE_PROC_PRIMARY) return NULL; - if (id > tdev.total_timvfs) + for (i = 0; i < tdev.total_timvfs; i++) { + if (tdev.rings[i].domain != global_domain) + continue; + if (tdev.rings[i].vfid == vfid) + res = &tdev.rings[i]; + + } + + if (res == NULL) return NULL; switch (bar) { case 0: - return tdev.rings[id].bar0; + return res->bar0; case 4: - return tdev.rings[id].bar4; + return res->bar4; default: return NULL; } @@ -118,6 +134,7 @@ timvf_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev) res->bar2 = pci_dev->mem_resource[2].addr; res->bar4 = pci_dev->mem_resource[4].addr; res->domain = (val >> 7) & 0xffff; + res->in_use = false; tdev.total_timvfs++; rte_wmb(); -- 2.17.1