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From: <pbhagavatula@marvell.com>
To: <jerinj@marvell.com>, Pavan Nikhilesh <pbhagavatula@marvell.com>
Cc: <dev@dpdk.org>
Subject: [dpdk-dev] [PATCH v3 5/5] event/octeontx2: update start timestamp periodically
Date: Fri, 22 Nov 2019 21:14:30 +0530
Message-ID: <20191122154431.17416-5-pbhagavatula@marvell.com> (raw)
In-Reply-To: <20191122154431.17416-1-pbhagavatula@marvell.com>

From: Pavan Nikhilesh <pbhagavatula@marvell.com>

Update start timestamp periodically to prevent drift.

Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
---
 drivers/event/octeontx2/otx2_tim_evdev.c  | 28 +++++++++++++++++++++++
 drivers/event/octeontx2/otx2_tim_evdev.h  |  7 ++++--
 drivers/event/octeontx2/otx2_tim_worker.c | 19 +++++++++++++++
 3 files changed, 52 insertions(+), 2 deletions(-)

diff --git a/drivers/event/octeontx2/otx2_tim_evdev.c b/drivers/event/octeontx2/otx2_tim_evdev.c
index 5f0233f44..b275c6922 100644
--- a/drivers/event/octeontx2/otx2_tim_evdev.c
+++ b/drivers/event/octeontx2/otx2_tim_evdev.c
@@ -389,6 +389,31 @@ otx2_tim_ring_create(struct rte_event_timer_adapter *adptr)
 	return rc;
 }
 
+static void
+otx2_tim_calibrate_start_tsc(struct otx2_tim_ring *tim_ring)
+{
+#define OTX2_TIM_CALIB_ITER	1E6
+	uint32_t real_bkt, bucket;
+	int icount, ecount = 0;
+	uint64_t bkt_cyc;
+
+	for (icount = 0; icount < OTX2_TIM_CALIB_ITER; icount++) {
+		real_bkt = otx2_read64(tim_ring->base + TIM_LF_RING_REL) >> 44;
+		bkt_cyc = rte_rdtsc();
+		bucket = (bkt_cyc - tim_ring->ring_start_cyc) /
+							tim_ring->tck_int;
+		bucket = bucket % (tim_ring->nb_bkts);
+		tim_ring->ring_start_cyc = bkt_cyc - (real_bkt *
+							tim_ring->tck_int);
+		if (bucket != real_bkt)
+			ecount++;
+	}
+	tim_ring->last_updt_cyc = bkt_cyc;
+	otx2_tim_dbg("Bucket mispredict %3.2f distance %d\n",
+		     100 - (((double)(icount - ecount) / (double)icount) * 100),
+		     bucket - real_bkt);
+}
+
 static int
 otx2_tim_ring_start(const struct rte_event_timer_adapter *adptr)
 {
@@ -423,8 +448,11 @@ otx2_tim_ring_start(const struct rte_event_timer_adapter *adptr)
 	tim_ring->ring_start_cyc = rsp->timestarted;
 #endif
 	tim_ring->tck_int = NSEC2TICK(tim_ring->tck_nsec, rte_get_timer_hz());
+	tim_ring->tot_int = tim_ring->tck_int * tim_ring->nb_bkts;
 	tim_ring->fast_div = rte_reciprocal_value_u64(tim_ring->tck_int);
 
+	otx2_tim_calibrate_start_tsc(tim_ring);
+
 fail:
 	return rc;
 }
diff --git a/drivers/event/octeontx2/otx2_tim_evdev.h b/drivers/event/octeontx2/otx2_tim_evdev.h
index f3fe9697a..56895dcbf 100644
--- a/drivers/event/octeontx2/otx2_tim_evdev.h
+++ b/drivers/event/octeontx2/otx2_tim_evdev.h
@@ -25,6 +25,7 @@
 #define TIM_LF_RAS_INT_W1S		(0x308)
 #define TIM_LF_RAS_INT_ENA_W1S		(0x310)
 #define TIM_LF_RAS_INT_ENA_W1C		(0x318)
+#define TIM_LF_RING_REL			(0x400)
 
 #define TIM_BUCKET_W1_S_CHUNK_REMAINDER	(48)
 #define TIM_BUCKET_W1_M_CHUNK_REMAINDER	((1ULL << (64 - \
@@ -139,13 +140,15 @@ struct otx2_tim_evdev {
 
 struct otx2_tim_ring {
 	uintptr_t base;
-	struct rte_reciprocal_u64 fast_div;
 	uint16_t nb_chunk_slots;
 	uint32_t nb_bkts;
+	uint64_t last_updt_cyc;
 	uint64_t ring_start_cyc;
+	uint64_t tck_int;
+	uint64_t tot_int;
 	struct otx2_tim_bkt *bkt;
 	struct rte_mempool *chunk_pool;
-	uint64_t tck_int;
+	struct rte_reciprocal_u64 fast_div;
 	rte_atomic64_t arm_cnt;
 	uint8_t prod_type_sp;
 	uint8_t enable_stats;
diff --git a/drivers/event/octeontx2/otx2_tim_worker.c b/drivers/event/octeontx2/otx2_tim_worker.c
index feba61cd4..104674c79 100644
--- a/drivers/event/octeontx2/otx2_tim_worker.c
+++ b/drivers/event/octeontx2/otx2_tim_worker.c
@@ -38,6 +38,23 @@ tim_format_event(const struct rte_event_timer * const tim,
 	entry->wqe = tim->ev.u64;
 }
 
+static inline void
+tim_sync_start_cyc(struct otx2_tim_ring *tim_ring)
+{
+	uint64_t cur_cyc = rte_rdtsc();
+	uint32_t real_bkt;
+
+	if (cur_cyc - tim_ring->last_updt_cyc > tim_ring->tot_int) {
+		real_bkt = otx2_read64(tim_ring->base + TIM_LF_RING_REL) >> 44;
+		cur_cyc = rte_rdtsc();
+
+		tim_ring->ring_start_cyc = cur_cyc -
+						(real_bkt * tim_ring->tck_int);
+		tim_ring->last_updt_cyc = cur_cyc;
+	}
+
+}
+
 static __rte_always_inline uint16_t
 tim_timer_arm_burst(const struct rte_event_timer_adapter *adptr,
 		    struct rte_event_timer **tim,
@@ -49,6 +66,7 @@ tim_timer_arm_burst(const struct rte_event_timer_adapter *adptr,
 	uint16_t index;
 	int ret;
 
+	tim_sync_start_cyc(tim_ring);
 	for (index = 0; index < nb_timers; index++) {
 		if (tim_arm_checks(tim_ring, tim[index]))
 			break;
@@ -99,6 +117,7 @@ tim_timer_arm_tmo_brst(const struct rte_event_timer_adapter *adptr,
 		return 0;
 	}
 
+	tim_sync_start_cyc(tim_ring);
 	while (arr_idx < nb_timers) {
 		for (idx = 0; idx < OTX2_TIM_MAX_BURST && (arr_idx < nb_timers);
 		     idx++, arr_idx++) {
-- 
2.17.1


  parent reply index

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-11-22 15:44 [dpdk-dev] [PATCH v3 1/5] event/octeontx2: fix TIM HW race condition pbhagavatula
2019-11-22 15:44 ` [dpdk-dev] [PATCH v3 2/5] event/octeontx2: use opposite bucket to store current chunk pbhagavatula
2019-11-22 15:44 ` [dpdk-dev] [PATCH v3 3/5] event/octeontx2: improve chunk pool performance pbhagavatula
2019-11-22 15:44 ` [dpdk-dev] [PATCH v3 4/5] event/octeontx2: update SSO buffers based on timer count pbhagavatula
2019-11-22 15:44 ` pbhagavatula [this message]
2019-11-22 16:07 ` [dpdk-dev] [PATCH v3 1/5] event/octeontx2: fix TIM HW race condition Pavan Nikhilesh Bhagavatula
2019-11-23  9:00   ` Jerin Jacob

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