From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id A090CA04C3; Fri, 22 Nov 2019 16:45:16 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 5A46A1BE97; Fri, 22 Nov 2019 16:44:50 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id B78CE1BE80 for ; Fri, 22 Nov 2019 16:44:45 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id xAMFe0j5026093 for ; Fri, 22 Nov 2019 07:44:45 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=IvJyUK+I55vl3uBkxOwCgCs3rdrDrufLEqScmYndYhk=; b=IGcFl+55EKQ17pkbk9lrfDwIvMpU++4LRoqiuDcHNrLWE+9VItd9iM4AGArfqj3hHDoy KfKEg1EYf0IRJxx7gUD9/FlD2GsCUJASq/b2w1A3Bba1ia3NtAc3gUATbJBi2ilCg80a g48OXzfxTr5T7XlsmKzpJIbtJTLwX9RVML/cm+AFJ3y9CB2rV3XW0ZCallqDPoQ7ei35 dDUV7zO1yGrO171UiosSuPkE0m4t3/k1X78ThIDJQ8jtNeqF3zPMilHLVj1rOzVhZqyV 5Cq8GdDEMgcTA5YcGTE6wPzFi+bLJdMdmImc8xI1hyZeqMBpUSJmjcSjzhUvqBufnfnj Jw== Received: from sc-exch04.marvell.com ([199.233.58.184]) by mx0b-0016f401.pphosted.com with ESMTP id 2wearf1vyy-3 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Fri, 22 Nov 2019 07:44:45 -0800 Received: from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Fri, 22 Nov 2019 07:44:43 -0800 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend Transport; Fri, 22 Nov 2019 07:44:43 -0800 Received: from BG-LT7430.marvell.com (unknown [10.28.17.72]) by maili.marvell.com (Postfix) with ESMTP id 295273F7040; Fri, 22 Nov 2019 07:44:41 -0800 (PST) From: To: , Pavan Nikhilesh CC: Date: Fri, 22 Nov 2019 21:14:30 +0530 Message-ID: <20191122154431.17416-5-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191122154431.17416-1-pbhagavatula@marvell.com> References: <20191122154431.17416-1-pbhagavatula@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,18.0.572 definitions=2019-11-22_03:2019-11-21,2019-11-22 signatures=0 Subject: [dpdk-dev] [PATCH v3 5/5] event/octeontx2: update start timestamp periodically X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Update start timestamp periodically to prevent drift. Signed-off-by: Pavan Nikhilesh --- drivers/event/octeontx2/otx2_tim_evdev.c | 28 +++++++++++++++++++++++ drivers/event/octeontx2/otx2_tim_evdev.h | 7 ++++-- drivers/event/octeontx2/otx2_tim_worker.c | 19 +++++++++++++++ 3 files changed, 52 insertions(+), 2 deletions(-) diff --git a/drivers/event/octeontx2/otx2_tim_evdev.c b/drivers/event/octeontx2/otx2_tim_evdev.c index 5f0233f44..b275c6922 100644 --- a/drivers/event/octeontx2/otx2_tim_evdev.c +++ b/drivers/event/octeontx2/otx2_tim_evdev.c @@ -389,6 +389,31 @@ otx2_tim_ring_create(struct rte_event_timer_adapter *adptr) return rc; } +static void +otx2_tim_calibrate_start_tsc(struct otx2_tim_ring *tim_ring) +{ +#define OTX2_TIM_CALIB_ITER 1E6 + uint32_t real_bkt, bucket; + int icount, ecount = 0; + uint64_t bkt_cyc; + + for (icount = 0; icount < OTX2_TIM_CALIB_ITER; icount++) { + real_bkt = otx2_read64(tim_ring->base + TIM_LF_RING_REL) >> 44; + bkt_cyc = rte_rdtsc(); + bucket = (bkt_cyc - tim_ring->ring_start_cyc) / + tim_ring->tck_int; + bucket = bucket % (tim_ring->nb_bkts); + tim_ring->ring_start_cyc = bkt_cyc - (real_bkt * + tim_ring->tck_int); + if (bucket != real_bkt) + ecount++; + } + tim_ring->last_updt_cyc = bkt_cyc; + otx2_tim_dbg("Bucket mispredict %3.2f distance %d\n", + 100 - (((double)(icount - ecount) / (double)icount) * 100), + bucket - real_bkt); +} + static int otx2_tim_ring_start(const struct rte_event_timer_adapter *adptr) { @@ -423,8 +448,11 @@ otx2_tim_ring_start(const struct rte_event_timer_adapter *adptr) tim_ring->ring_start_cyc = rsp->timestarted; #endif tim_ring->tck_int = NSEC2TICK(tim_ring->tck_nsec, rte_get_timer_hz()); + tim_ring->tot_int = tim_ring->tck_int * tim_ring->nb_bkts; tim_ring->fast_div = rte_reciprocal_value_u64(tim_ring->tck_int); + otx2_tim_calibrate_start_tsc(tim_ring); + fail: return rc; } diff --git a/drivers/event/octeontx2/otx2_tim_evdev.h b/drivers/event/octeontx2/otx2_tim_evdev.h index f3fe9697a..56895dcbf 100644 --- a/drivers/event/octeontx2/otx2_tim_evdev.h +++ b/drivers/event/octeontx2/otx2_tim_evdev.h @@ -25,6 +25,7 @@ #define TIM_LF_RAS_INT_W1S (0x308) #define TIM_LF_RAS_INT_ENA_W1S (0x310) #define TIM_LF_RAS_INT_ENA_W1C (0x318) +#define TIM_LF_RING_REL (0x400) #define TIM_BUCKET_W1_S_CHUNK_REMAINDER (48) #define TIM_BUCKET_W1_M_CHUNK_REMAINDER ((1ULL << (64 - \ @@ -139,13 +140,15 @@ struct otx2_tim_evdev { struct otx2_tim_ring { uintptr_t base; - struct rte_reciprocal_u64 fast_div; uint16_t nb_chunk_slots; uint32_t nb_bkts; + uint64_t last_updt_cyc; uint64_t ring_start_cyc; + uint64_t tck_int; + uint64_t tot_int; struct otx2_tim_bkt *bkt; struct rte_mempool *chunk_pool; - uint64_t tck_int; + struct rte_reciprocal_u64 fast_div; rte_atomic64_t arm_cnt; uint8_t prod_type_sp; uint8_t enable_stats; diff --git a/drivers/event/octeontx2/otx2_tim_worker.c b/drivers/event/octeontx2/otx2_tim_worker.c index feba61cd4..104674c79 100644 --- a/drivers/event/octeontx2/otx2_tim_worker.c +++ b/drivers/event/octeontx2/otx2_tim_worker.c @@ -38,6 +38,23 @@ tim_format_event(const struct rte_event_timer * const tim, entry->wqe = tim->ev.u64; } +static inline void +tim_sync_start_cyc(struct otx2_tim_ring *tim_ring) +{ + uint64_t cur_cyc = rte_rdtsc(); + uint32_t real_bkt; + + if (cur_cyc - tim_ring->last_updt_cyc > tim_ring->tot_int) { + real_bkt = otx2_read64(tim_ring->base + TIM_LF_RING_REL) >> 44; + cur_cyc = rte_rdtsc(); + + tim_ring->ring_start_cyc = cur_cyc - + (real_bkt * tim_ring->tck_int); + tim_ring->last_updt_cyc = cur_cyc; + } + +} + static __rte_always_inline uint16_t tim_timer_arm_burst(const struct rte_event_timer_adapter *adptr, struct rte_event_timer **tim, @@ -49,6 +66,7 @@ tim_timer_arm_burst(const struct rte_event_timer_adapter *adptr, uint16_t index; int ret; + tim_sync_start_cyc(tim_ring); for (index = 0; index < nb_timers; index++) { if (tim_arm_checks(tim_ring, tim[index])) break; @@ -99,6 +117,7 @@ tim_timer_arm_tmo_brst(const struct rte_event_timer_adapter *adptr, return 0; } + tim_sync_start_cyc(tim_ring); while (arr_idx < nb_timers) { for (idx = 0; idx < OTX2_TIM_MAX_BURST && (arr_idx < nb_timers); idx++, arr_idx++) { -- 2.17.1