* [dpdk-dev] [PATCH 01/17] net/iavf/base: remove unnecessary header file
2019-12-03 7:03 [dpdk-dev] [PATCH 00/17] iavf base code update Qi Zhang
@ 2019-12-03 7:03 ` Qi Zhang
2019-12-03 7:03 ` [dpdk-dev] [PATCH 02/17] net/iavf/base: rename error code enum Qi Zhang
` (16 subsequent siblings)
17 siblings, 0 replies; 21+ messages in thread
From: Qi Zhang @ 2019-12-03 7:03 UTC (permalink / raw)
To: xiaolong.ye; +Cc: haiyue.wang, dev, Qi Zhang, Paul M Stillwell Jr
Delete iavf_hmc.h and iavf_lan_hmc.h since its not necessary.
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/iavf/base/iavf_hmc.h | 216 -----------------------------------
drivers/net/iavf/base/iavf_lan_hmc.h | 171 ---------------------------
drivers/net/iavf/base/iavf_type.h | 7 +-
3 files changed, 2 insertions(+), 392 deletions(-)
delete mode 100644 drivers/net/iavf/base/iavf_hmc.h
delete mode 100644 drivers/net/iavf/base/iavf_lan_hmc.h
diff --git a/drivers/net/iavf/base/iavf_hmc.h b/drivers/net/iavf/base/iavf_hmc.h
deleted file mode 100644
index d861db04a..000000000
--- a/drivers/net/iavf/base/iavf_hmc.h
+++ /dev/null
@@ -1,216 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2013 - 2015 Intel Corporation
- */
-
-#ifndef _IAVF_HMC_H_
-#define _IAVF_HMC_H_
-
-#define IAVF_HMC_MAX_BP_COUNT 512
-
-/* forward-declare the HW struct for the compiler */
-struct iavf_hw;
-
-#define IAVF_HMC_INFO_SIGNATURE 0x484D5347 /* HMSG */
-#define IAVF_HMC_PD_CNT_IN_SD 512
-#define IAVF_HMC_DIRECT_BP_SIZE 0x200000 /* 2M */
-#define IAVF_HMC_PAGED_BP_SIZE 4096
-#define IAVF_HMC_PD_BP_BUF_ALIGNMENT 4096
-#define IAVF_FIRST_VF_FPM_ID 16
-
-struct iavf_hmc_obj_info {
- u64 base; /* base addr in FPM */
- u32 max_cnt; /* max count available for this hmc func */
- u32 cnt; /* count of objects driver actually wants to create */
- u64 size; /* size in bytes of one object */
-};
-
-enum iavf_sd_entry_type {
- IAVF_SD_TYPE_INVALID = 0,
- IAVF_SD_TYPE_PAGED = 1,
- IAVF_SD_TYPE_DIRECT = 2
-};
-
-struct iavf_hmc_bp {
- enum iavf_sd_entry_type entry_type;
- struct iavf_dma_mem addr; /* populate to be used by hw */
- u32 sd_pd_index;
- u32 ref_cnt;
-};
-
-struct iavf_hmc_pd_entry {
- struct iavf_hmc_bp bp;
- u32 sd_index;
- bool rsrc_pg;
- bool valid;
-};
-
-struct iavf_hmc_pd_table {
- struct iavf_dma_mem pd_page_addr; /* populate to be used by hw */
- struct iavf_hmc_pd_entry *pd_entry; /* [512] for sw book keeping */
- struct iavf_virt_mem pd_entry_virt_mem; /* virt mem for pd_entry */
-
- u32 ref_cnt;
- u32 sd_index;
-};
-
-struct iavf_hmc_sd_entry {
- enum iavf_sd_entry_type entry_type;
- bool valid;
-
- union {
- struct iavf_hmc_pd_table pd_table;
- struct iavf_hmc_bp bp;
- } u;
-};
-
-struct iavf_hmc_sd_table {
- struct iavf_virt_mem addr; /* used to track sd_entry allocations */
- u32 sd_cnt;
- u32 ref_cnt;
- struct iavf_hmc_sd_entry *sd_entry; /* (sd_cnt*512) entries max */
-};
-
-struct iavf_hmc_info {
- u32 signature;
- /* equals to pci func num for PF and dynamically allocated for VFs */
- u8 hmc_fn_id;
- u16 first_sd_index; /* index of the first available SD */
-
- /* hmc objects */
- struct iavf_hmc_obj_info *hmc_obj;
- struct iavf_virt_mem hmc_obj_virt_mem;
- struct iavf_hmc_sd_table sd_table;
-};
-
-#define IAVF_INC_SD_REFCNT(sd_table) ((sd_table)->ref_cnt++)
-#define IAVF_INC_PD_REFCNT(pd_table) ((pd_table)->ref_cnt++)
-#define IAVF_INC_BP_REFCNT(bp) ((bp)->ref_cnt++)
-
-#define IAVF_DEC_SD_REFCNT(sd_table) ((sd_table)->ref_cnt--)
-#define IAVF_DEC_PD_REFCNT(pd_table) ((pd_table)->ref_cnt--)
-#define IAVF_DEC_BP_REFCNT(bp) ((bp)->ref_cnt--)
-
-/**
- * IAVF_SET_PF_SD_ENTRY - marks the sd entry as valid in the hardware
- * @hw: pointer to our hw struct
- * @pa: pointer to physical address
- * @sd_index: segment descriptor index
- * @type: if sd entry is direct or paged
- **/
-#define IAVF_SET_PF_SD_ENTRY(hw, pa, sd_index, type) \
-{ \
- u32 val1, val2, val3; \
- val1 = (u32)(IAVF_HI_DWORD(pa)); \
- val2 = (u32)(pa) | (IAVF_HMC_MAX_BP_COUNT << \
- IAVF_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT) | \
- ((((type) == IAVF_SD_TYPE_PAGED) ? 0 : 1) << \
- IAVF_PFHMC_SDDATALOW_PMSDTYPE_SHIFT) | \
- BIT(IAVF_PFHMC_SDDATALOW_PMSDVALID_SHIFT); \
- val3 = (sd_index) | BIT_ULL(IAVF_PFHMC_SDCMD_PMSDWR_SHIFT); \
- wr32((hw), IAVF_PFHMC_SDDATAHIGH, val1); \
- wr32((hw), IAVF_PFHMC_SDDATALOW, val2); \
- wr32((hw), IAVF_PFHMC_SDCMD, val3); \
-}
-
-/**
- * IAVF_CLEAR_PF_SD_ENTRY - marks the sd entry as invalid in the hardware
- * @hw: pointer to our hw struct
- * @sd_index: segment descriptor index
- * @type: if sd entry is direct or paged
- **/
-#define IAVF_CLEAR_PF_SD_ENTRY(hw, sd_index, type) \
-{ \
- u32 val2, val3; \
- val2 = (IAVF_HMC_MAX_BP_COUNT << \
- IAVF_PFHMC_SDDATALOW_PMSDBPCOUNT_SHIFT) | \
- ((((type) == IAVF_SD_TYPE_PAGED) ? 0 : 1) << \
- IAVF_PFHMC_SDDATALOW_PMSDTYPE_SHIFT); \
- val3 = (sd_index) | BIT_ULL(IAVF_PFHMC_SDCMD_PMSDWR_SHIFT); \
- wr32((hw), IAVF_PFHMC_SDDATAHIGH, 0); \
- wr32((hw), IAVF_PFHMC_SDDATALOW, val2); \
- wr32((hw), IAVF_PFHMC_SDCMD, val3); \
-}
-
-/**
- * IAVF_INVALIDATE_PF_HMC_PD - Invalidates the pd cache in the hardware
- * @hw: pointer to our hw struct
- * @sd_idx: segment descriptor index
- * @pd_idx: page descriptor index
- **/
-#define IAVF_INVALIDATE_PF_HMC_PD(hw, sd_idx, pd_idx) \
- wr32((hw), IAVF_PFHMC_PDINV, \
- (((sd_idx) << IAVF_PFHMC_PDINV_PMSDIDX_SHIFT) | \
- ((pd_idx) << IAVF_PFHMC_PDINV_PMPDIDX_SHIFT)))
-
-/**
- * IAVF_FIND_SD_INDEX_LIMIT - finds segment descriptor index limit
- * @hmc_info: pointer to the HMC configuration information structure
- * @type: type of HMC resources we're searching
- * @index: starting index for the object
- * @cnt: number of objects we're trying to create
- * @sd_idx: pointer to return index of the segment descriptor in question
- * @sd_limit: pointer to return the maximum number of segment descriptors
- *
- * This function calculates the segment descriptor index and index limit
- * for the resource defined by iavf_hmc_rsrc_type.
- **/
-#define IAVF_FIND_SD_INDEX_LIMIT(hmc_info, type, index, cnt, sd_idx, sd_limit)\
-{ \
- u64 fpm_addr, fpm_limit; \
- fpm_addr = (hmc_info)->hmc_obj[(type)].base + \
- (hmc_info)->hmc_obj[(type)].size * (index); \
- fpm_limit = fpm_addr + (hmc_info)->hmc_obj[(type)].size * (cnt);\
- *(sd_idx) = (u32)(fpm_addr / IAVF_HMC_DIRECT_BP_SIZE); \
- *(sd_limit) = (u32)((fpm_limit - 1) / IAVF_HMC_DIRECT_BP_SIZE); \
- /* add one more to the limit to correct our range */ \
- *(sd_limit) += 1; \
-}
-
-/**
- * IAVF_FIND_PD_INDEX_LIMIT - finds page descriptor index limit
- * @hmc_info: pointer to the HMC configuration information struct
- * @type: HMC resource type we're examining
- * @idx: starting index for the object
- * @cnt: number of objects we're trying to create
- * @pd_index: pointer to return page descriptor index
- * @pd_limit: pointer to return page descriptor index limit
- *
- * Calculates the page descriptor index and index limit for the resource
- * defined by iavf_hmc_rsrc_type.
- **/
-#define IAVF_FIND_PD_INDEX_LIMIT(hmc_info, type, idx, cnt, pd_index, pd_limit)\
-{ \
- u64 fpm_adr, fpm_limit; \
- fpm_adr = (hmc_info)->hmc_obj[(type)].base + \
- (hmc_info)->hmc_obj[(type)].size * (idx); \
- fpm_limit = fpm_adr + (hmc_info)->hmc_obj[(type)].size * (cnt); \
- *(pd_index) = (u32)(fpm_adr / IAVF_HMC_PAGED_BP_SIZE); \
- *(pd_limit) = (u32)((fpm_limit - 1) / IAVF_HMC_PAGED_BP_SIZE); \
- /* add one more to the limit to correct our range */ \
- *(pd_limit) += 1; \
-}
-enum iavf_status_code iavf_add_sd_table_entry(struct iavf_hw *hw,
- struct iavf_hmc_info *hmc_info,
- u32 sd_index,
- enum iavf_sd_entry_type type,
- u64 direct_mode_sz);
-
-enum iavf_status_code iavf_add_pd_table_entry(struct iavf_hw *hw,
- struct iavf_hmc_info *hmc_info,
- u32 pd_index,
- struct iavf_dma_mem *rsrc_pg);
-enum iavf_status_code iavf_remove_pd_bp(struct iavf_hw *hw,
- struct iavf_hmc_info *hmc_info,
- u32 idx);
-enum iavf_status_code iavf_prep_remove_sd_bp(struct iavf_hmc_info *hmc_info,
- u32 idx);
-enum iavf_status_code iavf_remove_sd_bp_new(struct iavf_hw *hw,
- struct iavf_hmc_info *hmc_info,
- u32 idx, bool is_pf);
-enum iavf_status_code iavf_prep_remove_pd_page(struct iavf_hmc_info *hmc_info,
- u32 idx);
-enum iavf_status_code iavf_remove_pd_page_new(struct iavf_hw *hw,
- struct iavf_hmc_info *hmc_info,
- u32 idx, bool is_pf);
-
-#endif /* _IAVF_HMC_H_ */
diff --git a/drivers/net/iavf/base/iavf_lan_hmc.h b/drivers/net/iavf/base/iavf_lan_hmc.h
deleted file mode 100644
index 8e8752c79..000000000
--- a/drivers/net/iavf/base/iavf_lan_hmc.h
+++ /dev/null
@@ -1,171 +0,0 @@
-/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2013 - 2015 Intel Corporation
- */
-
-#ifndef _IAVF_LAN_HMC_H_
-#define _IAVF_LAN_HMC_H_
-
-/* forward-declare the HW struct for the compiler */
-struct iavf_hw;
-
-/* HMC element context information */
-
-/* Rx queue context data
- *
- * The sizes of the variables may be larger than needed due to crossing byte
- * boundaries. If we do not have the width of the variable set to the correct
- * size then we could end up shifting bits off the top of the variable when the
- * variable is at the top of a byte and crosses over into the next byte.
- */
-struct iavf_hmc_obj_rxq {
- u16 head;
- u16 cpuid; /* bigger than needed, see above for reason */
- u64 base;
- u16 qlen;
-#define IAVF_RXQ_CTX_DBUFF_SHIFT 7
- u16 dbuff; /* bigger than needed, see above for reason */
-#define IAVF_RXQ_CTX_HBUFF_SHIFT 6
- u16 hbuff; /* bigger than needed, see above for reason */
- u8 dtype;
- u8 dsize;
- u8 crcstrip;
- u8 fc_ena;
- u8 l2tsel;
- u8 hsplit_0;
- u8 hsplit_1;
- u8 showiv;
- u32 rxmax; /* bigger than needed, see above for reason */
- u8 tphrdesc_ena;
- u8 tphwdesc_ena;
- u8 tphdata_ena;
- u8 tphhead_ena;
- u16 lrxqthresh; /* bigger than needed, see above for reason */
- u8 prefena; /* NOTE: normally must be set to 1 at init */
-};
-
-/* Tx queue context data
-*
-* The sizes of the variables may be larger than needed due to crossing byte
-* boundaries. If we do not have the width of the variable set to the correct
-* size then we could end up shifting bits off the top of the variable when the
-* variable is at the top of a byte and crosses over into the next byte.
-*/
-struct iavf_hmc_obj_txq {
- u16 head;
- u8 new_context;
- u64 base;
- u8 fc_ena;
- u8 timesync_ena;
- u8 fd_ena;
- u8 alt_vlan_ena;
- u16 thead_wb;
- u8 cpuid;
- u8 head_wb_ena;
- u16 qlen;
- u8 tphrdesc_ena;
- u8 tphrpacket_ena;
- u8 tphwdesc_ena;
- u64 head_wb_addr;
- u32 crc;
- u16 rdylist;
- u8 rdylist_act;
-};
-
-/* for hsplit_0 field of Rx HMC context */
-enum iavf_hmc_obj_rx_hsplit_0 {
- IAVF_HMC_OBJ_RX_HSPLIT_0_NO_SPLIT = 0,
- IAVF_HMC_OBJ_RX_HSPLIT_0_SPLIT_L2 = 1,
- IAVF_HMC_OBJ_RX_HSPLIT_0_SPLIT_IP = 2,
- IAVF_HMC_OBJ_RX_HSPLIT_0_SPLIT_TCP_UDP = 4,
- IAVF_HMC_OBJ_RX_HSPLIT_0_SPLIT_SCTP = 8,
-};
-
-/* fcoe_cntx and fcoe_filt are for debugging purpose only */
-struct iavf_hmc_obj_fcoe_cntx {
- u32 rsv[32];
-};
-
-struct iavf_hmc_obj_fcoe_filt {
- u32 rsv[8];
-};
-
-/* Context sizes for LAN objects */
-enum iavf_hmc_lan_object_size {
- IAVF_HMC_LAN_OBJ_SZ_8 = 0x3,
- IAVF_HMC_LAN_OBJ_SZ_16 = 0x4,
- IAVF_HMC_LAN_OBJ_SZ_32 = 0x5,
- IAVF_HMC_LAN_OBJ_SZ_64 = 0x6,
- IAVF_HMC_LAN_OBJ_SZ_128 = 0x7,
- IAVF_HMC_LAN_OBJ_SZ_256 = 0x8,
- IAVF_HMC_LAN_OBJ_SZ_512 = 0x9,
-};
-
-#define IAVF_HMC_L2OBJ_BASE_ALIGNMENT 512
-#define IAVF_HMC_OBJ_SIZE_TXQ 128
-#define IAVF_HMC_OBJ_SIZE_RXQ 32
-#define IAVF_HMC_OBJ_SIZE_FCOE_CNTX 64
-#define IAVF_HMC_OBJ_SIZE_FCOE_FILT 64
-
-enum iavf_hmc_lan_rsrc_type {
- IAVF_HMC_LAN_FULL = 0,
- IAVF_HMC_LAN_TX = 1,
- IAVF_HMC_LAN_RX = 2,
- IAVF_HMC_FCOE_CTX = 3,
- IAVF_HMC_FCOE_FILT = 4,
- IAVF_HMC_LAN_MAX = 5
-};
-
-enum iavf_hmc_model {
- IAVF_HMC_MODEL_DIRECT_PREFERRED = 0,
- IAVF_HMC_MODEL_DIRECT_ONLY = 1,
- IAVF_HMC_MODEL_PAGED_ONLY = 2,
- IAVF_HMC_MODEL_UNKNOWN,
-};
-
-struct iavf_hmc_lan_create_obj_info {
- struct iavf_hmc_info *hmc_info;
- u32 rsrc_type;
- u32 start_idx;
- u32 count;
- enum iavf_sd_entry_type entry_type;
- u64 direct_mode_sz;
-};
-
-struct iavf_hmc_lan_delete_obj_info {
- struct iavf_hmc_info *hmc_info;
- u32 rsrc_type;
- u32 start_idx;
- u32 count;
-};
-
-enum iavf_status_code iavf_init_lan_hmc(struct iavf_hw *hw, u32 txq_num,
- u32 rxq_num, u32 fcoe_cntx_num,
- u32 fcoe_filt_num);
-enum iavf_status_code iavf_configure_lan_hmc(struct iavf_hw *hw,
- enum iavf_hmc_model model);
-enum iavf_status_code iavf_shutdown_lan_hmc(struct iavf_hw *hw);
-
-u64 iavf_calculate_l2fpm_size(u32 txq_num, u32 rxq_num,
- u32 fcoe_cntx_num, u32 fcoe_filt_num);
-enum iavf_status_code iavf_get_lan_tx_queue_context(struct iavf_hw *hw,
- u16 queue,
- struct iavf_hmc_obj_txq *s);
-enum iavf_status_code iavf_clear_lan_tx_queue_context(struct iavf_hw *hw,
- u16 queue);
-enum iavf_status_code iavf_set_lan_tx_queue_context(struct iavf_hw *hw,
- u16 queue,
- struct iavf_hmc_obj_txq *s);
-enum iavf_status_code iavf_get_lan_rx_queue_context(struct iavf_hw *hw,
- u16 queue,
- struct iavf_hmc_obj_rxq *s);
-enum iavf_status_code iavf_clear_lan_rx_queue_context(struct iavf_hw *hw,
- u16 queue);
-enum iavf_status_code iavf_set_lan_rx_queue_context(struct iavf_hw *hw,
- u16 queue,
- struct iavf_hmc_obj_rxq *s);
-enum iavf_status_code iavf_create_lan_hmc_object(struct iavf_hw *hw,
- struct iavf_hmc_lan_create_obj_info *info);
-enum iavf_status_code iavf_delete_lan_hmc_object(struct iavf_hw *hw,
- struct iavf_hmc_lan_delete_obj_info *info);
-
-#endif /* _IAVF_LAN_HMC_H_ */
diff --git a/drivers/net/iavf/base/iavf_type.h b/drivers/net/iavf/base/iavf_type.h
index eb0eaa4f2..4ccde31a2 100644
--- a/drivers/net/iavf/base/iavf_type.h
+++ b/drivers/net/iavf/base/iavf_type.h
@@ -9,10 +9,10 @@
#include "iavf_osdep.h"
#include "iavf_register.h"
#include "iavf_adminq.h"
-#include "iavf_hmc.h"
-#include "iavf_lan_hmc.h"
#include "iavf_devids.h"
+#define IAVF_RXQ_CTX_DBUFF_SHIFT 7
+
#define UNREFERENCED_XPARAMETER
#define UNREFERENCED_1PARAMETER(_p) (_p);
#define UNREFERENCED_2PARAMETER(_p, _q) (_p); (_q);
@@ -683,9 +683,6 @@ struct iavf_hw {
bool nvm_release_on_done;
u16 nvm_wait_opcode;
- /* HMC info */
- struct iavf_hmc_info hmc; /* HMC info struct */
-
/* LLDP/DCBX Status */
u16 dcbx_status;
--
2.13.6
^ permalink raw reply [flat|nested] 21+ messages in thread* [dpdk-dev] [PATCH 02/17] net/iavf/base: rename error code enum
2019-12-03 7:03 [dpdk-dev] [PATCH 00/17] iavf base code update Qi Zhang
2019-12-03 7:03 ` [dpdk-dev] [PATCH 01/17] net/iavf/base: remove unnecessary header file Qi Zhang
@ 2019-12-03 7:03 ` Qi Zhang
2019-12-03 7:03 ` [dpdk-dev] [PATCH 03/17] net/iavf/base: rename register macro Qi Zhang
` (15 subsequent siblings)
17 siblings, 0 replies; 21+ messages in thread
From: Qi Zhang @ 2019-12-03 7:03 UTC (permalink / raw)
To: xiaolong.ye; +Cc: haiyue.wang, dev, Qi Zhang, Paul M Stillwell Jr
Rename iavf_status_code to iavf_status to align with kernel
driver's implementation.
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/iavf/base/iavf_adminq.c | 56 ++++++++---------
drivers/net/iavf/base/iavf_alloc.h | 8 +--
drivers/net/iavf/base/iavf_common.c | 106 ++++++++++++++++-----------------
drivers/net/iavf/base/iavf_prototype.h | 90 ++++++++++++++--------------
drivers/net/iavf/base/iavf_status.h | 2 +-
drivers/net/iavf/iavf_ethdev.c | 8 +--
drivers/net/iavf/iavf_vchnl.c | 8 +--
7 files changed, 139 insertions(+), 139 deletions(-)
diff --git a/drivers/net/iavf/base/iavf_adminq.c b/drivers/net/iavf/base/iavf_adminq.c
index 1ba8b5221..ae8150e4f 100644
--- a/drivers/net/iavf/base/iavf_adminq.c
+++ b/drivers/net/iavf/base/iavf_adminq.c
@@ -35,9 +35,9 @@ STATIC void iavf_adminq_init_regs(struct iavf_hw *hw)
* iavf_alloc_adminq_asq_ring - Allocate Admin Queue send rings
* @hw: pointer to the hardware structure
**/
-enum iavf_status_code iavf_alloc_adminq_asq_ring(struct iavf_hw *hw)
+enum iavf_status iavf_alloc_adminq_asq_ring(struct iavf_hw *hw)
{
- enum iavf_status_code ret_code;
+ enum iavf_status ret_code;
ret_code = iavf_allocate_dma_mem(hw, &hw->aq.asq.desc_buf,
iavf_mem_atq_ring,
@@ -62,9 +62,9 @@ enum iavf_status_code iavf_alloc_adminq_asq_ring(struct iavf_hw *hw)
* iavf_alloc_adminq_arq_ring - Allocate Admin Queue receive rings
* @hw: pointer to the hardware structure
**/
-enum iavf_status_code iavf_alloc_adminq_arq_ring(struct iavf_hw *hw)
+enum iavf_status iavf_alloc_adminq_arq_ring(struct iavf_hw *hw)
{
- enum iavf_status_code ret_code;
+ enum iavf_status ret_code;
ret_code = iavf_allocate_dma_mem(hw, &hw->aq.arq.desc_buf,
iavf_mem_arq_ring,
@@ -103,9 +103,9 @@ void iavf_free_adminq_arq(struct iavf_hw *hw)
* iavf_alloc_arq_bufs - Allocate pre-posted buffers for the receive queue
* @hw: pointer to the hardware structure
**/
-STATIC enum iavf_status_code iavf_alloc_arq_bufs(struct iavf_hw *hw)
+STATIC enum iavf_status iavf_alloc_arq_bufs(struct iavf_hw *hw)
{
- enum iavf_status_code ret_code;
+ enum iavf_status ret_code;
struct iavf_aq_desc *desc;
struct iavf_dma_mem *bi;
int i;
@@ -170,9 +170,9 @@ STATIC enum iavf_status_code iavf_alloc_arq_bufs(struct iavf_hw *hw)
* iavf_alloc_asq_bufs - Allocate empty buffer structs for the send queue
* @hw: pointer to the hardware structure
**/
-STATIC enum iavf_status_code iavf_alloc_asq_bufs(struct iavf_hw *hw)
+STATIC enum iavf_status iavf_alloc_asq_bufs(struct iavf_hw *hw)
{
- enum iavf_status_code ret_code;
+ enum iavf_status ret_code;
struct iavf_dma_mem *bi;
int i;
@@ -254,9 +254,9 @@ STATIC void iavf_free_asq_bufs(struct iavf_hw *hw)
*
* Configure base address and length registers for the transmit queue
**/
-STATIC enum iavf_status_code iavf_config_asq_regs(struct iavf_hw *hw)
+STATIC enum iavf_status iavf_config_asq_regs(struct iavf_hw *hw)
{
- enum iavf_status_code ret_code = IAVF_SUCCESS;
+ enum iavf_status ret_code = IAVF_SUCCESS;
u32 reg = 0;
/* Clear Head and Tail */
@@ -289,9 +289,9 @@ STATIC enum iavf_status_code iavf_config_asq_regs(struct iavf_hw *hw)
*
* Configure base address and length registers for the receive (event queue)
**/
-STATIC enum iavf_status_code iavf_config_arq_regs(struct iavf_hw *hw)
+STATIC enum iavf_status iavf_config_arq_regs(struct iavf_hw *hw)
{
- enum iavf_status_code ret_code = IAVF_SUCCESS;
+ enum iavf_status ret_code = IAVF_SUCCESS;
u32 reg = 0;
/* Clear Head and Tail */
@@ -334,9 +334,9 @@ STATIC enum iavf_status_code iavf_config_arq_regs(struct iavf_hw *hw)
* Do *NOT* hold the lock when calling this as the memory allocation routines
* called are not going to be atomic context safe
**/
-enum iavf_status_code iavf_init_asq(struct iavf_hw *hw)
+enum iavf_status iavf_init_asq(struct iavf_hw *hw)
{
- enum iavf_status_code ret_code = IAVF_SUCCESS;
+ enum iavf_status ret_code = IAVF_SUCCESS;
if (hw->aq.asq.count > 0) {
/* queue already initialized */
@@ -393,9 +393,9 @@ enum iavf_status_code iavf_init_asq(struct iavf_hw *hw)
* Do *NOT* hold the lock when calling this as the memory allocation routines
* called are not going to be atomic context safe
**/
-enum iavf_status_code iavf_init_arq(struct iavf_hw *hw)
+enum iavf_status iavf_init_arq(struct iavf_hw *hw)
{
- enum iavf_status_code ret_code = IAVF_SUCCESS;
+ enum iavf_status ret_code = IAVF_SUCCESS;
if (hw->aq.arq.count > 0) {
/* queue already initialized */
@@ -445,9 +445,9 @@ enum iavf_status_code iavf_init_arq(struct iavf_hw *hw)
*
* The main shutdown routine for the Admin Send Queue
**/
-enum iavf_status_code iavf_shutdown_asq(struct iavf_hw *hw)
+enum iavf_status iavf_shutdown_asq(struct iavf_hw *hw)
{
- enum iavf_status_code ret_code = IAVF_SUCCESS;
+ enum iavf_status ret_code = IAVF_SUCCESS;
iavf_acquire_spinlock(&hw->aq.asq_spinlock);
@@ -479,9 +479,9 @@ enum iavf_status_code iavf_shutdown_asq(struct iavf_hw *hw)
*
* The main shutdown routine for the Admin Receive Queue
**/
-enum iavf_status_code iavf_shutdown_arq(struct iavf_hw *hw)
+enum iavf_status iavf_shutdown_arq(struct iavf_hw *hw)
{
- enum iavf_status_code ret_code = IAVF_SUCCESS;
+ enum iavf_status ret_code = IAVF_SUCCESS;
iavf_acquire_spinlock(&hw->aq.arq_spinlock);
@@ -518,9 +518,9 @@ enum iavf_status_code iavf_shutdown_arq(struct iavf_hw *hw)
* - hw->aq.arq_buf_size
* - hw->aq.asq_buf_size
**/
-enum iavf_status_code iavf_init_adminq(struct iavf_hw *hw)
+enum iavf_status iavf_init_adminq(struct iavf_hw *hw)
{
- enum iavf_status_code ret_code;
+ enum iavf_status ret_code;
/* verify input for valid configuration */
if ((hw->aq.num_arq_entries == 0) ||
@@ -568,9 +568,9 @@ enum iavf_status_code iavf_init_adminq(struct iavf_hw *hw)
* iavf_shutdown_adminq - shutdown routine for the Admin Queue
* @hw: pointer to the hardware structure
**/
-enum iavf_status_code iavf_shutdown_adminq(struct iavf_hw *hw)
+enum iavf_status iavf_shutdown_adminq(struct iavf_hw *hw)
{
- enum iavf_status_code ret_code = IAVF_SUCCESS;
+ enum iavf_status ret_code = IAVF_SUCCESS;
if (iavf_check_asq_alive(hw))
iavf_aq_queue_shutdown(hw, true);
@@ -654,13 +654,13 @@ bool iavf_asq_done(struct iavf_hw *hw)
* This is the main send command driver routine for the Admin Queue send
* queue. It runs the queue, cleans the queue, etc
**/
-enum iavf_status_code iavf_asq_send_command(struct iavf_hw *hw,
+enum iavf_status iavf_asq_send_command(struct iavf_hw *hw,
struct iavf_aq_desc *desc,
void *buff, /* can be NULL */
u16 buff_size,
struct iavf_asq_cmd_details *cmd_details)
{
- enum iavf_status_code status = IAVF_SUCCESS;
+ enum iavf_status status = IAVF_SUCCESS;
struct iavf_dma_mem *dma_buff = NULL;
struct iavf_asq_cmd_details *details;
struct iavf_aq_desc *desc_on_ring;
@@ -877,11 +877,11 @@ void iavf_fill_default_direct_cmd_desc(struct iavf_aq_desc *desc,
* the contents through e. It can also return how many events are
* left to process through 'pending'
**/
-enum iavf_status_code iavf_clean_arq_element(struct iavf_hw *hw,
+enum iavf_status iavf_clean_arq_element(struct iavf_hw *hw,
struct iavf_arq_event_info *e,
u16 *pending)
{
- enum iavf_status_code ret_code = IAVF_SUCCESS;
+ enum iavf_status ret_code = IAVF_SUCCESS;
u16 ntc = hw->aq.arq.next_to_clean;
struct iavf_aq_desc *desc;
struct iavf_dma_mem *bi;
diff --git a/drivers/net/iavf/base/iavf_alloc.h b/drivers/net/iavf/base/iavf_alloc.h
index 4ff307d23..da872bdbb 100644
--- a/drivers/net/iavf/base/iavf_alloc.h
+++ b/drivers/net/iavf/base/iavf_alloc.h
@@ -21,16 +21,16 @@ enum iavf_memory_type {
};
/* prototype for functions used for dynamic memory allocation */
-enum iavf_status_code iavf_allocate_dma_mem(struct iavf_hw *hw,
+enum iavf_status iavf_allocate_dma_mem(struct iavf_hw *hw,
struct iavf_dma_mem *mem,
enum iavf_memory_type type,
u64 size, u32 alignment);
-enum iavf_status_code iavf_free_dma_mem(struct iavf_hw *hw,
+enum iavf_status iavf_free_dma_mem(struct iavf_hw *hw,
struct iavf_dma_mem *mem);
-enum iavf_status_code iavf_allocate_virt_mem(struct iavf_hw *hw,
+enum iavf_status iavf_allocate_virt_mem(struct iavf_hw *hw,
struct iavf_virt_mem *mem,
u32 size);
-enum iavf_status_code iavf_free_virt_mem(struct iavf_hw *hw,
+enum iavf_status iavf_free_virt_mem(struct iavf_hw *hw,
struct iavf_virt_mem *mem);
#endif /* _IAVF_ALLOC_H_ */
diff --git a/drivers/net/iavf/base/iavf_common.c b/drivers/net/iavf/base/iavf_common.c
index 916a8388b..0b9f83415 100644
--- a/drivers/net/iavf/base/iavf_common.c
+++ b/drivers/net/iavf/base/iavf_common.c
@@ -15,9 +15,9 @@
* This function sets the mac type of the adapter based on the
* vendor ID and device ID stored in the hw structure.
**/
-enum iavf_status_code iavf_set_mac_type(struct iavf_hw *hw)
+enum iavf_status iavf_set_mac_type(struct iavf_hw *hw)
{
- enum iavf_status_code status = IAVF_SUCCESS;
+ enum iavf_status status = IAVF_SUCCESS;
DEBUGFUNC("iavf_set_mac_type\n");
@@ -107,7 +107,7 @@ const char *iavf_aq_str(struct iavf_hw *hw, enum iavf_admin_queue_err aq_err)
* @hw: pointer to the HW structure
* @stat_err: the status error code to convert
**/
-const char *iavf_stat_str(struct iavf_hw *hw, enum iavf_status_code stat_err)
+const char *iavf_stat_str(struct iavf_hw *hw, enum iavf_status stat_err)
{
switch (stat_err) {
case IAVF_SUCCESS:
@@ -348,13 +348,13 @@ bool iavf_check_asq_alive(struct iavf_hw *hw)
* Tell the Firmware that we're shutting down the AdminQ and whether
* or not the driver is unloading as well.
**/
-enum iavf_status_code iavf_aq_queue_shutdown(struct iavf_hw *hw,
+enum iavf_status iavf_aq_queue_shutdown(struct iavf_hw *hw,
bool unloading)
{
struct iavf_aq_desc desc;
struct iavf_aqc_queue_shutdown *cmd =
(struct iavf_aqc_queue_shutdown *)&desc.params.raw;
- enum iavf_status_code status;
+ enum iavf_status status;
iavf_fill_default_direct_cmd_desc(&desc,
iavf_aqc_opc_queue_shutdown);
@@ -377,12 +377,12 @@ enum iavf_status_code iavf_aq_queue_shutdown(struct iavf_hw *hw,
*
* Internal function to get or set RSS look up table
**/
-STATIC enum iavf_status_code iavf_aq_get_set_rss_lut(struct iavf_hw *hw,
+STATIC enum iavf_status iavf_aq_get_set_rss_lut(struct iavf_hw *hw,
u16 vsi_id, bool pf_lut,
u8 *lut, u16 lut_size,
bool set)
{
- enum iavf_status_code status;
+ enum iavf_status status;
struct iavf_aq_desc desc;
struct iavf_aqc_get_set_rss_lut *cmd_resp =
(struct iavf_aqc_get_set_rss_lut *)&desc.params.raw;
@@ -430,7 +430,7 @@ STATIC enum iavf_status_code iavf_aq_get_set_rss_lut(struct iavf_hw *hw,
*
* get the RSS lookup table, PF or VSI type
**/
-enum iavf_status_code iavf_aq_get_rss_lut(struct iavf_hw *hw, u16 vsi_id,
+enum iavf_status iavf_aq_get_rss_lut(struct iavf_hw *hw, u16 vsi_id,
bool pf_lut, u8 *lut, u16 lut_size)
{
return iavf_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
@@ -447,7 +447,7 @@ enum iavf_status_code iavf_aq_get_rss_lut(struct iavf_hw *hw, u16 vsi_id,
*
* set the RSS lookup table, PF or VSI type
**/
-enum iavf_status_code iavf_aq_set_rss_lut(struct iavf_hw *hw, u16 vsi_id,
+enum iavf_status iavf_aq_set_rss_lut(struct iavf_hw *hw, u16 vsi_id,
bool pf_lut, u8 *lut, u16 lut_size)
{
return iavf_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
@@ -462,12 +462,12 @@ enum iavf_status_code iavf_aq_set_rss_lut(struct iavf_hw *hw, u16 vsi_id,
*
* get the RSS key per VSI
**/
-STATIC enum iavf_status_code iavf_aq_get_set_rss_key(struct iavf_hw *hw,
+STATIC enum iavf_status iavf_aq_get_set_rss_key(struct iavf_hw *hw,
u16 vsi_id,
struct iavf_aqc_get_set_rss_key_data *key,
bool set)
{
- enum iavf_status_code status;
+ enum iavf_status status;
struct iavf_aq_desc desc;
struct iavf_aqc_get_set_rss_key *cmd_resp =
(struct iavf_aqc_get_set_rss_key *)&desc.params.raw;
@@ -502,7 +502,7 @@ STATIC enum iavf_status_code iavf_aq_get_set_rss_key(struct iavf_hw *hw,
* @key: pointer to key info struct
*
**/
-enum iavf_status_code iavf_aq_get_rss_key(struct iavf_hw *hw,
+enum iavf_status iavf_aq_get_rss_key(struct iavf_hw *hw,
u16 vsi_id,
struct iavf_aqc_get_set_rss_key_data *key)
{
@@ -517,7 +517,7 @@ enum iavf_status_code iavf_aq_get_rss_key(struct iavf_hw *hw,
*
* set the RSS key per VSI
**/
-enum iavf_status_code iavf_aq_set_rss_key(struct iavf_hw *hw,
+enum iavf_status iavf_aq_set_rss_key(struct iavf_hw *hw,
u16 vsi_id,
struct iavf_aqc_get_set_rss_key_data *key)
{
@@ -896,9 +896,9 @@ struct iavf_rx_ptype_decoded iavf_ptype_lookup[] = {
*
* Tests a MAC address to ensure it is a valid Individual Address
**/
-enum iavf_status_code iavf_validate_mac_addr(u8 *mac_addr)
+enum iavf_status iavf_validate_mac_addr(u8 *mac_addr)
{
- enum iavf_status_code status = IAVF_SUCCESS;
+ enum iavf_status status = IAVF_SUCCESS;
DEBUGFUNC("iavf_validate_mac_addr");
@@ -924,14 +924,14 @@ enum iavf_status_code iavf_validate_mac_addr(u8 *mac_addr)
* Use the firmware to read the Rx control register,
* especially useful if the Rx unit is under heavy pressure
**/
-enum iavf_status_code iavf_aq_rx_ctl_read_register(struct iavf_hw *hw,
+enum iavf_status iavf_aq_rx_ctl_read_register(struct iavf_hw *hw,
u32 reg_addr, u32 *reg_val,
struct iavf_asq_cmd_details *cmd_details)
{
struct iavf_aq_desc desc;
struct iavf_aqc_rx_ctl_reg_read_write *cmd_resp =
(struct iavf_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
- enum iavf_status_code status;
+ enum iavf_status status;
if (reg_val == NULL)
return IAVF_ERR_PARAM;
@@ -955,7 +955,7 @@ enum iavf_status_code iavf_aq_rx_ctl_read_register(struct iavf_hw *hw,
**/
u32 iavf_read_rx_ctl(struct iavf_hw *hw, u32 reg_addr)
{
- enum iavf_status_code status = IAVF_SUCCESS;
+ enum iavf_status status = IAVF_SUCCESS;
bool use_register;
int retry = 5;
u32 val = 0;
@@ -990,14 +990,14 @@ u32 iavf_read_rx_ctl(struct iavf_hw *hw, u32 reg_addr)
* Use the firmware to write to an Rx control register,
* especially useful if the Rx unit is under heavy pressure
**/
-enum iavf_status_code iavf_aq_rx_ctl_write_register(struct iavf_hw *hw,
+enum iavf_status iavf_aq_rx_ctl_write_register(struct iavf_hw *hw,
u32 reg_addr, u32 reg_val,
struct iavf_asq_cmd_details *cmd_details)
{
struct iavf_aq_desc desc;
struct iavf_aqc_rx_ctl_reg_read_write *cmd =
(struct iavf_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
- enum iavf_status_code status;
+ enum iavf_status status;
iavf_fill_default_direct_cmd_desc(&desc, iavf_aqc_opc_rx_ctl_reg_write);
@@ -1017,7 +1017,7 @@ enum iavf_status_code iavf_aq_rx_ctl_write_register(struct iavf_hw *hw,
**/
void iavf_write_rx_ctl(struct iavf_hw *hw, u32 reg_addr, u32 reg_val)
{
- enum iavf_status_code status = IAVF_SUCCESS;
+ enum iavf_status status = IAVF_SUCCESS;
bool use_register;
int retry = 5;
@@ -1051,7 +1051,7 @@ void iavf_write_rx_ctl(struct iavf_hw *hw, u32 reg_addr, u32 reg_val)
*
* Write the external PHY register.
**/
-enum iavf_status_code iavf_aq_set_phy_register(struct iavf_hw *hw,
+enum iavf_status iavf_aq_set_phy_register(struct iavf_hw *hw,
u8 phy_select, u8 dev_addr,
u32 reg_addr, u32 reg_val,
struct iavf_asq_cmd_details *cmd_details)
@@ -1059,7 +1059,7 @@ enum iavf_status_code iavf_aq_set_phy_register(struct iavf_hw *hw,
struct iavf_aq_desc desc;
struct iavf_aqc_phy_register_access *cmd =
(struct iavf_aqc_phy_register_access *)&desc.params.raw;
- enum iavf_status_code status;
+ enum iavf_status status;
iavf_fill_default_direct_cmd_desc(&desc,
iavf_aqc_opc_set_phy_register);
@@ -1085,7 +1085,7 @@ enum iavf_status_code iavf_aq_set_phy_register(struct iavf_hw *hw,
*
* Read the external PHY register.
**/
-enum iavf_status_code iavf_aq_get_phy_register(struct iavf_hw *hw,
+enum iavf_status iavf_aq_get_phy_register(struct iavf_hw *hw,
u8 phy_select, u8 dev_addr,
u32 reg_addr, u32 *reg_val,
struct iavf_asq_cmd_details *cmd_details)
@@ -1093,7 +1093,7 @@ enum iavf_status_code iavf_aq_get_phy_register(struct iavf_hw *hw,
struct iavf_aq_desc desc;
struct iavf_aqc_phy_register_access *cmd =
(struct iavf_aqc_phy_register_access *)&desc.params.raw;
- enum iavf_status_code status;
+ enum iavf_status status;
iavf_fill_default_direct_cmd_desc(&desc,
iavf_aqc_opc_get_phy_register);
@@ -1123,15 +1123,15 @@ enum iavf_status_code iavf_aq_get_phy_register(struct iavf_hw *hw,
* is sent asynchronously, i.e. iavf_asq_send_command() does not wait for
* completion before returning.
**/
-enum iavf_status_code iavf_aq_send_msg_to_pf(struct iavf_hw *hw,
+enum iavf_status iavf_aq_send_msg_to_pf(struct iavf_hw *hw,
enum virtchnl_ops v_opcode,
- enum iavf_status_code v_retval,
+ enum iavf_status v_retval,
u8 *msg, u16 msglen,
struct iavf_asq_cmd_details *cmd_details)
{
struct iavf_aq_desc desc;
struct iavf_asq_cmd_details details;
- enum iavf_status_code status;
+ enum iavf_status status;
iavf_fill_default_direct_cmd_desc(&desc, iavf_aqc_opc_send_msg_to_pf);
desc.flags |= CPU_TO_LE16((u16)IAVF_AQ_FLAG_SI);
@@ -1200,7 +1200,7 @@ void iavf_parse_hw_config(struct iavf_hw *hw,
* as none will be forthcoming. Immediately after calling this function,
* the admin queue should be shut down and (optionally) reinitialized.
**/
-enum iavf_status_code iavf_reset(struct iavf_hw *hw)
+enum iavf_status iavf_reset(struct iavf_hw *hw)
{
return iavf_aq_send_msg_to_pf(hw, VIRTCHNL_OP_RESET_VF,
IAVF_SUCCESS, NULL, 0, NULL);
@@ -1215,12 +1215,12 @@ enum iavf_status_code iavf_reset(struct iavf_hw *hw)
* Set ARP offload parameters from pre-populated
* iavf_aqc_arp_proxy_data struct
**/
-enum iavf_status_code iavf_aq_set_arp_proxy_config(struct iavf_hw *hw,
+enum iavf_status iavf_aq_set_arp_proxy_config(struct iavf_hw *hw,
struct iavf_aqc_arp_proxy_data *proxy_config,
struct iavf_asq_cmd_details *cmd_details)
{
struct iavf_aq_desc desc;
- enum iavf_status_code status;
+ enum iavf_status status;
if (!proxy_config)
return IAVF_ERR_PARAM;
@@ -1251,12 +1251,12 @@ enum iavf_status_code iavf_aq_set_arp_proxy_config(struct iavf_hw *hw,
* Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
* from pre-populated iavf_aqc_ns_proxy_data struct
**/
-enum iavf_status_code iavf_aq_set_ns_proxy_table_entry(struct iavf_hw *hw,
+enum iavf_status iavf_aq_set_ns_proxy_table_entry(struct iavf_hw *hw,
struct iavf_aqc_ns_proxy_data *ns_proxy_table_entry,
struct iavf_asq_cmd_details *cmd_details)
{
struct iavf_aq_desc desc;
- enum iavf_status_code status;
+ enum iavf_status status;
if (!ns_proxy_table_entry)
return IAVF_ERR_PARAM;
@@ -1293,7 +1293,7 @@ enum iavf_status_code iavf_aq_set_ns_proxy_table_entry(struct iavf_hw *hw,
*
* Set or clear WoL filter for port attached to the PF
**/
-enum iavf_status_code iavf_aq_set_clear_wol_filter(struct iavf_hw *hw,
+enum iavf_status iavf_aq_set_clear_wol_filter(struct iavf_hw *hw,
u8 filter_index,
struct iavf_aqc_set_wol_filter_data *filter,
bool set_filter, bool no_wol_tco,
@@ -1303,7 +1303,7 @@ enum iavf_status_code iavf_aq_set_clear_wol_filter(struct iavf_hw *hw,
struct iavf_aq_desc desc;
struct iavf_aqc_set_wol_filter *cmd =
(struct iavf_aqc_set_wol_filter *)&desc.params.raw;
- enum iavf_status_code status;
+ enum iavf_status status;
u16 cmd_flags = 0;
u16 valid_flags = 0;
u16 buff_len = 0;
@@ -1355,14 +1355,14 @@ enum iavf_status_code iavf_aq_set_clear_wol_filter(struct iavf_hw *hw,
*
* Get information for the reason of a Wake Up event
**/
-enum iavf_status_code iavf_aq_get_wake_event_reason(struct iavf_hw *hw,
+enum iavf_status iavf_aq_get_wake_event_reason(struct iavf_hw *hw,
u16 *wake_reason,
struct iavf_asq_cmd_details *cmd_details)
{
struct iavf_aq_desc desc;
struct iavf_aqc_get_wake_reason_completion *resp =
(struct iavf_aqc_get_wake_reason_completion *)&desc.params.raw;
- enum iavf_status_code status;
+ enum iavf_status status;
iavf_fill_default_direct_cmd_desc(&desc, iavf_aqc_opc_get_wake_reason);
@@ -1381,11 +1381,11 @@ enum iavf_status_code iavf_aq_get_wake_event_reason(struct iavf_hw *hw,
*
* Get information for the reason of a Wake Up event
**/
-enum iavf_status_code iavf_aq_clear_all_wol_filters(struct iavf_hw *hw,
+enum iavf_status iavf_aq_clear_all_wol_filters(struct iavf_hw *hw,
struct iavf_asq_cmd_details *cmd_details)
{
struct iavf_aq_desc desc;
- enum iavf_status_code status;
+ enum iavf_status status;
iavf_fill_default_direct_cmd_desc(&desc,
iavf_aqc_opc_clear_all_wol_filters);
@@ -1406,7 +1406,7 @@ enum iavf_status_code iavf_aq_clear_all_wol_filters(struct iavf_hw *hw,
* @cmd_details: pointer to command details structure or NULL
**/
enum
-iavf_status_code iavf_aq_write_ddp(struct iavf_hw *hw, void *buff,
+iavf_status iavf_aq_write_ddp(struct iavf_hw *hw, void *buff,
u16 buff_size, u32 track_id,
u32 *error_offset, u32 *error_info,
struct iavf_asq_cmd_details *cmd_details)
@@ -1416,7 +1416,7 @@ iavf_status_code iavf_aq_write_ddp(struct iavf_hw *hw, void *buff,
(struct iavf_aqc_write_personalization_profile *)
&desc.params.raw;
struct iavf_aqc_write_ddp_resp *resp;
- enum iavf_status_code status;
+ enum iavf_status status;
iavf_fill_default_direct_cmd_desc(&desc,
iavf_aqc_opc_write_personalization_profile);
@@ -1450,14 +1450,14 @@ iavf_status_code iavf_aq_write_ddp(struct iavf_hw *hw, void *buff,
* @cmd_details: pointer to command details structure or NULL
**/
enum
-iavf_status_code iavf_aq_get_ddp_list(struct iavf_hw *hw, void *buff,
+iavf_status iavf_aq_get_ddp_list(struct iavf_hw *hw, void *buff,
u16 buff_size, u8 flags,
struct iavf_asq_cmd_details *cmd_details)
{
struct iavf_aq_desc desc;
struct iavf_aqc_get_applied_profiles *cmd =
(struct iavf_aqc_get_applied_profiles *)&desc.params.raw;
- enum iavf_status_code status;
+ enum iavf_status status;
iavf_fill_default_direct_cmd_desc(&desc,
iavf_aqc_opc_get_personalization_profile_list);
@@ -1557,10 +1557,10 @@ iavf_find_section_in_profile(u32 section_type,
* @aq: command buffer containing all data to execute AQ
**/
STATIC enum
-iavf_status_code iavf_ddp_exec_aq_section(struct iavf_hw *hw,
+iavf_status iavf_ddp_exec_aq_section(struct iavf_hw *hw,
struct iavf_profile_aq_section *aq)
{
- enum iavf_status_code status;
+ enum iavf_status status;
struct iavf_aq_desc desc;
u8 *msg = NULL;
u16 msglen;
@@ -1605,12 +1605,12 @@ iavf_status_code iavf_ddp_exec_aq_section(struct iavf_hw *hw,
*
* Validates supported devices and profile's sections.
*/
-STATIC enum iavf_status_code
+STATIC enum iavf_status
iavf_validate_profile(struct iavf_hw *hw, struct iavf_profile_segment *profile,
u32 track_id, bool rollback)
{
struct iavf_profile_section_header *sec = NULL;
- enum iavf_status_code status = IAVF_SUCCESS;
+ enum iavf_status status = IAVF_SUCCESS;
struct iavf_section_table *sec_tbl;
u32 vendor_dev_id;
u32 dev_cnt;
@@ -1670,11 +1670,11 @@ iavf_validate_profile(struct iavf_hw *hw, struct iavf_profile_segment *profile,
*
* Handles the download of a complete package.
*/
-enum iavf_status_code
+enum iavf_status
iavf_write_profile(struct iavf_hw *hw, struct iavf_profile_segment *profile,
u32 track_id)
{
- enum iavf_status_code status = IAVF_SUCCESS;
+ enum iavf_status status = IAVF_SUCCESS;
struct iavf_section_table *sec_tbl;
struct iavf_profile_section_header *sec = NULL;
struct iavf_profile_aq_section *ddp_aq;
@@ -1733,12 +1733,12 @@ iavf_write_profile(struct iavf_hw *hw, struct iavf_profile_segment *profile,
*
* Rolls back previously loaded package.
*/
-enum iavf_status_code
+enum iavf_status
iavf_rollback_profile(struct iavf_hw *hw, struct iavf_profile_segment *profile,
u32 track_id)
{
struct iavf_profile_section_header *sec = NULL;
- enum iavf_status_code status = IAVF_SUCCESS;
+ enum iavf_status status = IAVF_SUCCESS;
struct iavf_section_table *sec_tbl;
u32 offset = 0, info = 0;
u32 section_size = 0;
@@ -1785,12 +1785,12 @@ iavf_rollback_profile(struct iavf_hw *hw, struct iavf_profile_segment *profile,
*
* Register a profile to the list of loaded profiles.
*/
-enum iavf_status_code
+enum iavf_status
iavf_add_pinfo_to_list(struct iavf_hw *hw,
struct iavf_profile_segment *profile,
u8 *profile_info_sec, u32 track_id)
{
- enum iavf_status_code status = IAVF_SUCCESS;
+ enum iavf_status status = IAVF_SUCCESS;
struct iavf_profile_section_header *sec = NULL;
struct iavf_profile_info *pinfo;
u32 offset = 0, info = 0;
diff --git a/drivers/net/iavf/base/iavf_prototype.h b/drivers/net/iavf/base/iavf_prototype.h
index fbc2b2382..4b428b8d9 100644
--- a/drivers/net/iavf/base/iavf_prototype.h
+++ b/drivers/net/iavf/base/iavf_prototype.h
@@ -17,23 +17,23 @@
*/
/* adminq functions */
-enum iavf_status_code iavf_init_adminq(struct iavf_hw *hw);
-enum iavf_status_code iavf_shutdown_adminq(struct iavf_hw *hw);
-enum iavf_status_code iavf_init_asq(struct iavf_hw *hw);
-enum iavf_status_code iavf_init_arq(struct iavf_hw *hw);
-enum iavf_status_code iavf_alloc_adminq_asq_ring(struct iavf_hw *hw);
-enum iavf_status_code iavf_alloc_adminq_arq_ring(struct iavf_hw *hw);
-enum iavf_status_code iavf_shutdown_asq(struct iavf_hw *hw);
-enum iavf_status_code iavf_shutdown_arq(struct iavf_hw *hw);
+enum iavf_status iavf_init_adminq(struct iavf_hw *hw);
+enum iavf_status iavf_shutdown_adminq(struct iavf_hw *hw);
+enum iavf_status iavf_init_asq(struct iavf_hw *hw);
+enum iavf_status iavf_init_arq(struct iavf_hw *hw);
+enum iavf_status iavf_alloc_adminq_asq_ring(struct iavf_hw *hw);
+enum iavf_status iavf_alloc_adminq_arq_ring(struct iavf_hw *hw);
+enum iavf_status iavf_shutdown_asq(struct iavf_hw *hw);
+enum iavf_status iavf_shutdown_arq(struct iavf_hw *hw);
u16 iavf_clean_asq(struct iavf_hw *hw);
void iavf_free_adminq_asq(struct iavf_hw *hw);
void iavf_free_adminq_arq(struct iavf_hw *hw);
-enum iavf_status_code iavf_validate_mac_addr(u8 *mac_addr);
+enum iavf_status iavf_validate_mac_addr(u8 *mac_addr);
void iavf_adminq_init_ring_data(struct iavf_hw *hw);
-enum iavf_status_code iavf_clean_arq_element(struct iavf_hw *hw,
+enum iavf_status iavf_clean_arq_element(struct iavf_hw *hw,
struct iavf_arq_event_info *e,
u16 *events_pending);
-enum iavf_status_code iavf_asq_send_command(struct iavf_hw *hw,
+enum iavf_status iavf_asq_send_command(struct iavf_hw *hw,
struct iavf_aq_desc *desc,
void *buff, /* can be NULL */
u16 buff_size,
@@ -46,23 +46,23 @@ void iavf_debug_aq(struct iavf_hw *hw, enum iavf_debug_mask mask,
void iavf_idle_aq(struct iavf_hw *hw);
bool iavf_check_asq_alive(struct iavf_hw *hw);
-enum iavf_status_code iavf_aq_queue_shutdown(struct iavf_hw *hw, bool unloading);
+enum iavf_status iavf_aq_queue_shutdown(struct iavf_hw *hw, bool unloading);
-enum iavf_status_code iavf_aq_get_rss_lut(struct iavf_hw *hw, u16 seid,
+enum iavf_status iavf_aq_get_rss_lut(struct iavf_hw *hw, u16 seid,
bool pf_lut, u8 *lut, u16 lut_size);
-enum iavf_status_code iavf_aq_set_rss_lut(struct iavf_hw *hw, u16 seid,
+enum iavf_status iavf_aq_set_rss_lut(struct iavf_hw *hw, u16 seid,
bool pf_lut, u8 *lut, u16 lut_size);
-enum iavf_status_code iavf_aq_get_rss_key(struct iavf_hw *hw,
+enum iavf_status iavf_aq_get_rss_key(struct iavf_hw *hw,
u16 seid,
struct iavf_aqc_get_set_rss_key_data *key);
-enum iavf_status_code iavf_aq_set_rss_key(struct iavf_hw *hw,
+enum iavf_status iavf_aq_set_rss_key(struct iavf_hw *hw,
u16 seid,
struct iavf_aqc_get_set_rss_key_data *key);
const char *iavf_aq_str(struct iavf_hw *hw, enum iavf_admin_queue_err aq_err);
-const char *iavf_stat_str(struct iavf_hw *hw, enum iavf_status_code stat_err);
+const char *iavf_stat_str(struct iavf_hw *hw, enum iavf_status stat_err);
-enum iavf_status_code iavf_set_mac_type(struct iavf_hw *hw);
+enum iavf_status iavf_set_mac_type(struct iavf_hw *hw);
extern struct iavf_rx_ptype_decoded iavf_ptype_lookup[];
@@ -80,81 +80,81 @@ void iavf_destroy_spinlock(struct iavf_spinlock *sp);
/* iavf_common for VF drivers*/
void iavf_parse_hw_config(struct iavf_hw *hw,
struct virtchnl_vf_resource *msg);
-enum iavf_status_code iavf_reset(struct iavf_hw *hw);
-enum iavf_status_code iavf_aq_send_msg_to_pf(struct iavf_hw *hw,
+enum iavf_status iavf_reset(struct iavf_hw *hw);
+enum iavf_status iavf_aq_send_msg_to_pf(struct iavf_hw *hw,
enum virtchnl_ops v_opcode,
- enum iavf_status_code v_retval,
+ enum iavf_status v_retval,
u8 *msg, u16 msglen,
struct iavf_asq_cmd_details *cmd_details);
-enum iavf_status_code iavf_set_filter_control(struct iavf_hw *hw,
+enum iavf_status iavf_set_filter_control(struct iavf_hw *hw,
struct iavf_filter_control_settings *settings);
-enum iavf_status_code iavf_aq_add_rem_control_packet_filter(struct iavf_hw *hw,
+enum iavf_status iavf_aq_add_rem_control_packet_filter(struct iavf_hw *hw,
u8 *mac_addr, u16 ethtype, u16 flags,
u16 vsi_seid, u16 queue, bool is_add,
struct iavf_control_filter_stats *stats,
struct iavf_asq_cmd_details *cmd_details);
-enum iavf_status_code iavf_aq_debug_dump(struct iavf_hw *hw, u8 cluster_id,
+enum iavf_status iavf_aq_debug_dump(struct iavf_hw *hw, u8 cluster_id,
u8 table_id, u32 start_index, u16 buff_size,
void *buff, u16 *ret_buff_size,
u8 *ret_next_table, u32 *ret_next_index,
struct iavf_asq_cmd_details *cmd_details);
void iavf_add_filter_to_drop_tx_flow_control_frames(struct iavf_hw *hw,
u16 vsi_seid);
-enum iavf_status_code iavf_aq_rx_ctl_read_register(struct iavf_hw *hw,
+enum iavf_status iavf_aq_rx_ctl_read_register(struct iavf_hw *hw,
u32 reg_addr, u32 *reg_val,
struct iavf_asq_cmd_details *cmd_details);
u32 iavf_read_rx_ctl(struct iavf_hw *hw, u32 reg_addr);
-enum iavf_status_code iavf_aq_rx_ctl_write_register(struct iavf_hw *hw,
+enum iavf_status iavf_aq_rx_ctl_write_register(struct iavf_hw *hw,
u32 reg_addr, u32 reg_val,
struct iavf_asq_cmd_details *cmd_details);
void iavf_write_rx_ctl(struct iavf_hw *hw, u32 reg_addr, u32 reg_val);
-enum iavf_status_code iavf_aq_set_phy_register(struct iavf_hw *hw,
+enum iavf_status iavf_aq_set_phy_register(struct iavf_hw *hw,
u8 phy_select, u8 dev_addr,
u32 reg_addr, u32 reg_val,
struct iavf_asq_cmd_details *cmd_details);
-enum iavf_status_code iavf_aq_get_phy_register(struct iavf_hw *hw,
+enum iavf_status iavf_aq_get_phy_register(struct iavf_hw *hw,
u8 phy_select, u8 dev_addr,
u32 reg_addr, u32 *reg_val,
struct iavf_asq_cmd_details *cmd_details);
-enum iavf_status_code iavf_aq_set_arp_proxy_config(struct iavf_hw *hw,
+enum iavf_status iavf_aq_set_arp_proxy_config(struct iavf_hw *hw,
struct iavf_aqc_arp_proxy_data *proxy_config,
struct iavf_asq_cmd_details *cmd_details);
-enum iavf_status_code iavf_aq_set_ns_proxy_table_entry(struct iavf_hw *hw,
+enum iavf_status iavf_aq_set_ns_proxy_table_entry(struct iavf_hw *hw,
struct iavf_aqc_ns_proxy_data *ns_proxy_table_entry,
struct iavf_asq_cmd_details *cmd_details);
-enum iavf_status_code iavf_aq_set_clear_wol_filter(struct iavf_hw *hw,
+enum iavf_status iavf_aq_set_clear_wol_filter(struct iavf_hw *hw,
u8 filter_index,
struct iavf_aqc_set_wol_filter_data *filter,
bool set_filter, bool no_wol_tco,
bool filter_valid, bool no_wol_tco_valid,
struct iavf_asq_cmd_details *cmd_details);
-enum iavf_status_code iavf_aq_get_wake_event_reason(struct iavf_hw *hw,
+enum iavf_status iavf_aq_get_wake_event_reason(struct iavf_hw *hw,
u16 *wake_reason,
struct iavf_asq_cmd_details *cmd_details);
-enum iavf_status_code iavf_aq_clear_all_wol_filters(struct iavf_hw *hw,
+enum iavf_status iavf_aq_clear_all_wol_filters(struct iavf_hw *hw,
struct iavf_asq_cmd_details *cmd_details);
-enum iavf_status_code iavf_read_phy_register_clause22(struct iavf_hw *hw,
+enum iavf_status iavf_read_phy_register_clause22(struct iavf_hw *hw,
u16 reg, u8 phy_addr, u16 *value);
-enum iavf_status_code iavf_write_phy_register_clause22(struct iavf_hw *hw,
+enum iavf_status iavf_write_phy_register_clause22(struct iavf_hw *hw,
u16 reg, u8 phy_addr, u16 value);
-enum iavf_status_code iavf_read_phy_register_clause45(struct iavf_hw *hw,
+enum iavf_status iavf_read_phy_register_clause45(struct iavf_hw *hw,
u8 page, u16 reg, u8 phy_addr, u16 *value);
-enum iavf_status_code iavf_write_phy_register_clause45(struct iavf_hw *hw,
+enum iavf_status iavf_write_phy_register_clause45(struct iavf_hw *hw,
u8 page, u16 reg, u8 phy_addr, u16 value);
-enum iavf_status_code iavf_read_phy_register(struct iavf_hw *hw,
+enum iavf_status iavf_read_phy_register(struct iavf_hw *hw,
u8 page, u16 reg, u8 phy_addr, u16 *value);
-enum iavf_status_code iavf_write_phy_register(struct iavf_hw *hw,
+enum iavf_status iavf_write_phy_register(struct iavf_hw *hw,
u8 page, u16 reg, u8 phy_addr, u16 value);
u8 iavf_get_phy_address(struct iavf_hw *hw, u8 dev_num);
-enum iavf_status_code iavf_blink_phy_link_led(struct iavf_hw *hw,
+enum iavf_status iavf_blink_phy_link_led(struct iavf_hw *hw,
u32 time, u32 interval);
-enum iavf_status_code iavf_aq_write_ddp(struct iavf_hw *hw, void *buff,
+enum iavf_status iavf_aq_write_ddp(struct iavf_hw *hw, void *buff,
u16 buff_size, u32 track_id,
u32 *error_offset, u32 *error_info,
struct iavf_asq_cmd_details *
cmd_details);
-enum iavf_status_code iavf_aq_get_ddp_list(struct iavf_hw *hw, void *buff,
+enum iavf_status iavf_aq_get_ddp_list(struct iavf_hw *hw, void *buff,
u16 buff_size, u8 flags,
struct iavf_asq_cmd_details *
cmd_details);
@@ -164,13 +164,13 @@ iavf_find_segment_in_package(u32 segment_type,
struct iavf_profile_section_header *
iavf_find_section_in_profile(u32 section_type,
struct iavf_profile_segment *profile);
-enum iavf_status_code
+enum iavf_status
iavf_write_profile(struct iavf_hw *hw, struct iavf_profile_segment *iavf_seg,
u32 track_id);
-enum iavf_status_code
+enum iavf_status
iavf_rollback_profile(struct iavf_hw *hw, struct iavf_profile_segment *iavf_seg,
u32 track_id);
-enum iavf_status_code
+enum iavf_status
iavf_add_pinfo_to_list(struct iavf_hw *hw,
struct iavf_profile_segment *profile,
u8 *profile_info_sec, u32 track_id);
diff --git a/drivers/net/iavf/base/iavf_status.h b/drivers/net/iavf/base/iavf_status.h
index cb91afb01..32b391589 100644
--- a/drivers/net/iavf/base/iavf_status.h
+++ b/drivers/net/iavf/base/iavf_status.h
@@ -6,7 +6,7 @@
#define _IAVF_STATUS_H_
/* Error Codes */
-enum iavf_status_code {
+enum iavf_status {
IAVF_SUCCESS = 0,
IAVF_ERR_NVM = -1,
IAVF_ERR_NVM_CHECKSUM = -2,
diff --git a/drivers/net/iavf/iavf_ethdev.c b/drivers/net/iavf/iavf_ethdev.c
index a39ba1466..4f80113ae 100644
--- a/drivers/net/iavf/iavf_ethdev.c
+++ b/drivers/net/iavf/iavf_ethdev.c
@@ -1470,7 +1470,7 @@ RTE_INIT(iavf_init_log)
}
/* memory func for base code */
-enum iavf_status_code
+enum iavf_status
iavf_allocate_dma_mem_d(__rte_unused struct iavf_hw *hw,
struct iavf_dma_mem *mem,
u64 size,
@@ -1499,7 +1499,7 @@ iavf_allocate_dma_mem_d(__rte_unused struct iavf_hw *hw,
return IAVF_SUCCESS;
}
-enum iavf_status_code
+enum iavf_status
iavf_free_dma_mem_d(__rte_unused struct iavf_hw *hw,
struct iavf_dma_mem *mem)
{
@@ -1517,7 +1517,7 @@ iavf_free_dma_mem_d(__rte_unused struct iavf_hw *hw,
return IAVF_SUCCESS;
}
-enum iavf_status_code
+enum iavf_status
iavf_allocate_virt_mem_d(__rte_unused struct iavf_hw *hw,
struct iavf_virt_mem *mem,
u32 size)
@@ -1534,7 +1534,7 @@ iavf_allocate_virt_mem_d(__rte_unused struct iavf_hw *hw,
return IAVF_ERR_NO_MEMORY;
}
-enum iavf_status_code
+enum iavf_status
iavf_free_virt_mem_d(__rte_unused struct iavf_hw *hw,
struct iavf_virt_mem *mem)
{
diff --git a/drivers/net/iavf/iavf_vchnl.c b/drivers/net/iavf/iavf_vchnl.c
index 14395fed3..4320a7f91 100644
--- a/drivers/net/iavf/iavf_vchnl.c
+++ b/drivers/net/iavf/iavf_vchnl.c
@@ -31,7 +31,7 @@
#define ASQ_DELAY_MS 10
/* Read data in admin queue to get msg from pf driver */
-static enum iavf_status_code
+static enum iavf_status
iavf_read_msg_from_pf(struct iavf_adapter *adapter, uint16_t buf_len,
uint8_t *buf)
{
@@ -69,7 +69,7 @@ iavf_execute_vf_cmd(struct iavf_adapter *adapter, struct iavf_cmd_info *args)
{
struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(adapter);
struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(adapter);
- enum iavf_status_code ret;
+ enum iavf_status ret;
int err = 0;
int i = 0;
@@ -175,7 +175,7 @@ iavf_handle_virtchnl_msg(struct rte_eth_dev *dev)
struct iavf_arq_event_info info;
uint16_t pending, aq_opc;
enum virtchnl_ops msg_opc;
- enum iavf_status_code msg_ret;
+ enum iavf_status msg_ret;
int ret;
info.buf_len = IAVF_AQ_BUF_SZ;
@@ -201,7 +201,7 @@ iavf_handle_virtchnl_msg(struct rte_eth_dev *dev)
*/
msg_opc = (enum virtchnl_ops)rte_le_to_cpu_32(
info.desc.cookie_high);
- msg_ret = (enum iavf_status_code)rte_le_to_cpu_32(
+ msg_ret = (enum iavf_status)rte_le_to_cpu_32(
info.desc.cookie_low);
switch (aq_opc) {
case iavf_aqc_opc_send_msg_to_vf:
--
2.13.6
^ permalink raw reply [flat|nested] 21+ messages in thread* [dpdk-dev] [PATCH 03/17] net/iavf/base: rename register macro
2019-12-03 7:03 [dpdk-dev] [PATCH 00/17] iavf base code update Qi Zhang
2019-12-03 7:03 ` [dpdk-dev] [PATCH 01/17] net/iavf/base: remove unnecessary header file Qi Zhang
2019-12-03 7:03 ` [dpdk-dev] [PATCH 02/17] net/iavf/base: rename error code enum Qi Zhang
@ 2019-12-03 7:03 ` Qi Zhang
2019-12-03 7:03 ` [dpdk-dev] [PATCH 04/17] net/iavf/base: update device id Qi Zhang
` (14 subsequent siblings)
17 siblings, 0 replies; 21+ messages in thread
From: Qi Zhang @ 2019-12-03 7:03 UTC (permalink / raw)
To: xiaolong.ye; +Cc: haiyue.wang, dev, Qi Zhang, Paul M Stillwell Jr
Rename all register macro to align with kernel driver's
implementation.
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/iavf/base/iavf_adminq.c | 34 +--
drivers/net/iavf/base/iavf_common.c | 4 +-
drivers/net/iavf/base/iavf_osdep.h | 2 +-
drivers/net/iavf/base/iavf_register.h | 388 +++++++---------------------------
drivers/net/iavf/iavf_ethdev.c | 59 +++---
5 files changed, 134 insertions(+), 353 deletions(-)
diff --git a/drivers/net/iavf/base/iavf_adminq.c b/drivers/net/iavf/base/iavf_adminq.c
index ae8150e4f..193e2e7d1 100644
--- a/drivers/net/iavf/base/iavf_adminq.c
+++ b/drivers/net/iavf/base/iavf_adminq.c
@@ -18,16 +18,16 @@ STATIC void iavf_adminq_init_regs(struct iavf_hw *hw)
{
/* set head and tail registers in our local struct */
if (iavf_is_vf(hw)) {
- hw->aq.asq.tail = IAVF_ATQT1;
- hw->aq.asq.head = IAVF_ATQH1;
- hw->aq.asq.len = IAVF_ATQLEN1;
- hw->aq.asq.bal = IAVF_ATQBAL1;
- hw->aq.asq.bah = IAVF_ATQBAH1;
- hw->aq.arq.tail = IAVF_ARQT1;
- hw->aq.arq.head = IAVF_ARQH1;
- hw->aq.arq.len = IAVF_ARQLEN1;
- hw->aq.arq.bal = IAVF_ARQBAL1;
- hw->aq.arq.bah = IAVF_ARQBAH1;
+ hw->aq.asq.tail = IAVF_VF_ATQT1;
+ hw->aq.asq.head = IAVF_VF_ATQH1;
+ hw->aq.asq.len = IAVF_VF_ATQLEN1;
+ hw->aq.asq.bal = IAVF_VF_ATQBAL1;
+ hw->aq.asq.bah = IAVF_VF_ATQBAH1;
+ hw->aq.arq.tail = IAVF_VF_ARQT1;
+ hw->aq.arq.head = IAVF_VF_ARQH1;
+ hw->aq.arq.len = IAVF_VF_ARQLEN1;
+ hw->aq.arq.bal = IAVF_VF_ARQBAL1;
+ hw->aq.arq.bah = IAVF_VF_ARQBAH1;
}
}
@@ -267,10 +267,10 @@ STATIC enum iavf_status iavf_config_asq_regs(struct iavf_hw *hw)
#ifdef INTEGRATED_VF
if (iavf_is_vf(hw))
wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries |
- IAVF_ATQLEN1_ATQENABLE_MASK));
+ IAVF_VF_ATQLEN1_ATQENABLE_MASK));
#else
wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries |
- IAVF_ATQLEN1_ATQENABLE_MASK));
+ IAVF_VF_ATQLEN1_ATQENABLE_MASK));
#endif /* INTEGRATED_VF */
wr32(hw, hw->aq.asq.bal, IAVF_LO_DWORD(hw->aq.asq.desc_buf.pa));
wr32(hw, hw->aq.asq.bah, IAVF_HI_DWORD(hw->aq.asq.desc_buf.pa));
@@ -302,10 +302,10 @@ STATIC enum iavf_status iavf_config_arq_regs(struct iavf_hw *hw)
#ifdef INTEGRATED_VF
if (iavf_is_vf(hw))
wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries |
- IAVF_ARQLEN1_ARQENABLE_MASK));
+ IAVF_VF_ARQLEN1_ARQENABLE_MASK));
#else
wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries |
- IAVF_ARQLEN1_ARQENABLE_MASK));
+ IAVF_VF_ARQLEN1_ARQENABLE_MASK));
#endif /* INTEGRATED_VF */
wr32(hw, hw->aq.arq.bal, IAVF_LO_DWORD(hw->aq.arq.desc_buf.pa));
wr32(hw, hw->aq.arq.bah, IAVF_HI_DWORD(hw->aq.arq.desc_buf.pa));
@@ -834,7 +834,7 @@ enum iavf_status iavf_asq_send_command(struct iavf_hw *hw,
/* update the error if time out occurred */
if ((!cmd_completed) &&
(!details->async && !details->postpone)) {
- if (rd32(hw, hw->aq.asq.len) & IAVF_ATQLEN1_ATQCRIT_MASK) {
+ if (rd32(hw, hw->aq.asq.len) & IAVF_VF_ATQLEN1_ATQCRIT_MASK) {
iavf_debug(hw, IAVF_DEBUG_AQ_MESSAGE,
"AQTX: AQ Critical error.\n");
status = IAVF_ERR_ADMIN_QUEUE_CRITICAL_ERROR;
@@ -908,9 +908,9 @@ enum iavf_status iavf_clean_arq_element(struct iavf_hw *hw,
if (!iavf_is_vf(hw))
ntu = rd32(hw, hw->aq.arq.head) & IAVF_PF_ARQH_ARQH_MASK;
else
- ntu = rd32(hw, hw->aq.arq.head) & IAVF_ARQH1_ARQH_MASK;
+ ntu = rd32(hw, hw->aq.arq.head) & IAVF_VF_ARQH1_ARQH_MASK;
#else
- ntu = rd32(hw, hw->aq.arq.head) & IAVF_ARQH1_ARQH_MASK;
+ ntu = rd32(hw, hw->aq.arq.head) & IAVF_VF_ARQH1_ARQH_MASK;
#endif /* INTEGRATED_VF */
if (ntu == ntc) {
/* nothing to do - shouldn't need to update ring's values */
diff --git a/drivers/net/iavf/base/iavf_common.c b/drivers/net/iavf/base/iavf_common.c
index 0b9f83415..5df4410e0 100644
--- a/drivers/net/iavf/base/iavf_common.c
+++ b/drivers/net/iavf/base/iavf_common.c
@@ -332,10 +332,10 @@ bool iavf_check_asq_alive(struct iavf_hw *hw)
#ifdef INTEGRATED_VF
if (iavf_is_vf(hw))
return !!(rd32(hw, hw->aq.asq.len) &
- IAVF_ATQLEN1_ATQENABLE_MASK);
+ IAVF_VF_ATQLEN1_ATQENABLE_MASK);
#else
return !!(rd32(hw, hw->aq.asq.len) &
- IAVF_ATQLEN1_ATQENABLE_MASK);
+ IAVF_VF_ATQLEN1_ATQENABLE_MASK);
#endif /* INTEGRATED_VF */
return false;
}
diff --git a/drivers/net/iavf/base/iavf_osdep.h b/drivers/net/iavf/base/iavf_osdep.h
index 648026693..1b22f9fbc 100644
--- a/drivers/net/iavf/base/iavf_osdep.h
+++ b/drivers/net/iavf/base/iavf_osdep.h
@@ -115,7 +115,7 @@ uint32_t iavf_read_addr(volatile void *addr)
#define IAVF_WRITE_REG(hw, reg, value) \
IAVF_PCI_REG_WRITE(IAVF_PCI_REG_ADDR((hw), (reg)), (value))
#define IAVF_WRITE_FLUSH(a) \
- IAVF_READ_REG(a, IAVFGEN_RSTAT)
+ IAVF_READ_REG(a, IAVF_VFGEN_RSTAT)
#define rd32(a, reg) iavf_read_addr(IAVF_PCI_REG_ADDR((a), (reg)))
#define wr32(a, reg, value) \
diff --git a/drivers/net/iavf/base/iavf_register.h b/drivers/net/iavf/base/iavf_register.h
index b66d88c44..7d2b20710 100644
--- a/drivers/net/iavf/base/iavf_register.h
+++ b/drivers/net/iavf/base/iavf_register.h
@@ -5,313 +5,89 @@
#ifndef _IAVF_REGISTER_H_
#define _IAVF_REGISTER_H_
-
-#define IAVFMSIX_PBA1(_i) (0x00002000 + ((_i) * 4)) /* _i=0...19 */ /* Reset: VFLR */
-#define IAVFMSIX_PBA1_MAX_INDEX 19
-#define IAVFMSIX_PBA1_PENBIT_SHIFT 0
-#define IAVFMSIX_PBA1_PENBIT_MASK IAVF_MASK(0xFFFFFFFF, IAVFMSIX_PBA1_PENBIT_SHIFT)
-#define IAVFMSIX_TADD1(_i) (0x00002100 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */
-#define IAVFMSIX_TADD1_MAX_INDEX 639
-#define IAVFMSIX_TADD1_MSIXTADD10_SHIFT 0
-#define IAVFMSIX_TADD1_MSIXTADD10_MASK IAVF_MASK(0x3, IAVFMSIX_TADD1_MSIXTADD10_SHIFT)
-#define IAVFMSIX_TADD1_MSIXTADD_SHIFT 2
-#define IAVFMSIX_TADD1_MSIXTADD_MASK IAVF_MASK(0x3FFFFFFF, IAVFMSIX_TADD1_MSIXTADD_SHIFT)
-#define IAVFMSIX_TMSG1(_i) (0x00002108 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */
-#define IAVFMSIX_TMSG1_MAX_INDEX 639
-#define IAVFMSIX_TMSG1_MSIXTMSG_SHIFT 0
-#define IAVFMSIX_TMSG1_MSIXTMSG_MASK IAVF_MASK(0xFFFFFFFF, IAVFMSIX_TMSG1_MSIXTMSG_SHIFT)
-#define IAVFMSIX_TUADD1(_i) (0x00002104 + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */
-#define IAVFMSIX_TUADD1_MAX_INDEX 639
-#define IAVFMSIX_TUADD1_MSIXTUADD_SHIFT 0
-#define IAVFMSIX_TUADD1_MSIXTUADD_MASK IAVF_MASK(0xFFFFFFFF, IAVFMSIX_TUADD1_MSIXTUADD_SHIFT)
-#define IAVFMSIX_TVCTRL1(_i) (0x0000210C + ((_i) * 16)) /* _i=0...639 */ /* Reset: VFLR */
-#define IAVFMSIX_TVCTRL1_MAX_INDEX 639
-#define IAVFMSIX_TVCTRL1_MASK_SHIFT 0
-#define IAVFMSIX_TVCTRL1_MASK_MASK IAVF_MASK(0x1, IAVFMSIX_TVCTRL1_MASK_SHIFT)
-#define IAVF_ARQBAH1 0x00006000 /* Reset: EMPR */
-#define IAVF_ARQBAH1_ARQBAH_SHIFT 0
-#define IAVF_ARQBAH1_ARQBAH_MASK IAVF_MASK(0xFFFFFFFF, IAVF_ARQBAH1_ARQBAH_SHIFT)
-#define IAVF_ARQBAL1 0x00006C00 /* Reset: EMPR */
-#define IAVF_ARQBAL1_ARQBAL_SHIFT 0
-#define IAVF_ARQBAL1_ARQBAL_MASK IAVF_MASK(0xFFFFFFFF, IAVF_ARQBAL1_ARQBAL_SHIFT)
-#define IAVF_ARQH1 0x00007400 /* Reset: EMPR */
-#define IAVF_ARQH1_ARQH_SHIFT 0
-#define IAVF_ARQH1_ARQH_MASK IAVF_MASK(0x3FF, IAVF_ARQH1_ARQH_SHIFT)
-#define IAVF_ARQLEN1 0x00008000 /* Reset: EMPR */
-#define IAVF_ARQLEN1_ARQLEN_SHIFT 0
-#define IAVF_ARQLEN1_ARQLEN_MASK IAVF_MASK(0x3FF, IAVF_ARQLEN1_ARQLEN_SHIFT)
-#define IAVF_ARQLEN1_ARQVFE_SHIFT 28
-#define IAVF_ARQLEN1_ARQVFE_MASK IAVF_MASK(0x1, IAVF_ARQLEN1_ARQVFE_SHIFT)
-#define IAVF_ARQLEN1_ARQOVFL_SHIFT 29
-#define IAVF_ARQLEN1_ARQOVFL_MASK IAVF_MASK(0x1, IAVF_ARQLEN1_ARQOVFL_SHIFT)
-#define IAVF_ARQLEN1_ARQCRIT_SHIFT 30
-#define IAVF_ARQLEN1_ARQCRIT_MASK IAVF_MASK(0x1, IAVF_ARQLEN1_ARQCRIT_SHIFT)
-#define IAVF_ARQLEN1_ARQENABLE_SHIFT 31
-#define IAVF_ARQLEN1_ARQENABLE_MASK IAVF_MASK(0x1U, IAVF_ARQLEN1_ARQENABLE_SHIFT)
-#define IAVF_ARQT1 0x00007000 /* Reset: EMPR */
-#define IAVF_ARQT1_ARQT_SHIFT 0
-#define IAVF_ARQT1_ARQT_MASK IAVF_MASK(0x3FF, IAVF_ARQT1_ARQT_SHIFT)
-#define IAVF_ATQBAH1 0x00007800 /* Reset: EMPR */
-#define IAVF_ATQBAH1_ATQBAH_SHIFT 0
-#define IAVF_ATQBAH1_ATQBAH_MASK IAVF_MASK(0xFFFFFFFF, IAVF_ATQBAH1_ATQBAH_SHIFT)
-#define IAVF_ATQBAL1 0x00007C00 /* Reset: EMPR */
-#define IAVF_ATQBAL1_ATQBAL_SHIFT 0
-#define IAVF_ATQBAL1_ATQBAL_MASK IAVF_MASK(0xFFFFFFFF, IAVF_ATQBAL1_ATQBAL_SHIFT)
-#define IAVF_ATQH1 0x00006400 /* Reset: EMPR */
-#define IAVF_ATQH1_ATQH_SHIFT 0
-#define IAVF_ATQH1_ATQH_MASK IAVF_MASK(0x3FF, IAVF_ATQH1_ATQH_SHIFT)
-#define IAVF_ATQLEN1 0x00006800 /* Reset: EMPR */
-#define IAVF_ATQLEN1_ATQLEN_SHIFT 0
-#define IAVF_ATQLEN1_ATQLEN_MASK IAVF_MASK(0x3FF, IAVF_ATQLEN1_ATQLEN_SHIFT)
-#define IAVF_ATQLEN1_ATQVFE_SHIFT 28
-#define IAVF_ATQLEN1_ATQVFE_MASK IAVF_MASK(0x1, IAVF_ATQLEN1_ATQVFE_SHIFT)
-#define IAVF_ATQLEN1_ATQOVFL_SHIFT 29
-#define IAVF_ATQLEN1_ATQOVFL_MASK IAVF_MASK(0x1, IAVF_ATQLEN1_ATQOVFL_SHIFT)
-#define IAVF_ATQLEN1_ATQCRIT_SHIFT 30
-#define IAVF_ATQLEN1_ATQCRIT_MASK IAVF_MASK(0x1, IAVF_ATQLEN1_ATQCRIT_SHIFT)
-#define IAVF_ATQLEN1_ATQENABLE_SHIFT 31
-#define IAVF_ATQLEN1_ATQENABLE_MASK IAVF_MASK(0x1U, IAVF_ATQLEN1_ATQENABLE_SHIFT)
-#define IAVF_ATQT1 0x00008400 /* Reset: EMPR */
-#define IAVF_ATQT1_ATQT_SHIFT 0
-#define IAVF_ATQT1_ATQT_MASK IAVF_MASK(0x3FF, IAVF_ATQT1_ATQT_SHIFT)
-#define IAVFGEN_RSTAT 0x00008800 /* Reset: VFR */
-#define IAVFGEN_RSTAT_VFR_STATE_SHIFT 0
-#define IAVFGEN_RSTAT_VFR_STATE_MASK IAVF_MASK(0x3, IAVFGEN_RSTAT_VFR_STATE_SHIFT)
-#define IAVFINT_DYN_CTL01 0x00005C00 /* Reset: VFR */
-#define IAVFINT_DYN_CTL01_INTENA_SHIFT 0
-#define IAVFINT_DYN_CTL01_INTENA_MASK IAVF_MASK(0x1, IAVFINT_DYN_CTL01_INTENA_SHIFT)
-#define IAVFINT_DYN_CTL01_CLEARPBA_SHIFT 1
-#define IAVFINT_DYN_CTL01_CLEARPBA_MASK IAVF_MASK(0x1, IAVFINT_DYN_CTL01_CLEARPBA_SHIFT)
-#define IAVFINT_DYN_CTL01_SWINT_TRIG_SHIFT 2
-#define IAVFINT_DYN_CTL01_SWINT_TRIG_MASK IAVF_MASK(0x1, IAVFINT_DYN_CTL01_SWINT_TRIG_SHIFT)
-#define IAVFINT_DYN_CTL01_ITR_INDX_SHIFT 3
-#define IAVFINT_DYN_CTL01_ITR_INDX_MASK IAVF_MASK(0x3, IAVFINT_DYN_CTL01_ITR_INDX_SHIFT)
-#define IAVFINT_DYN_CTL01_INTERVAL_SHIFT 5
-#define IAVFINT_DYN_CTL01_INTERVAL_MASK IAVF_MASK(0xFFF, IAVFINT_DYN_CTL01_INTERVAL_SHIFT)
-#define IAVFINT_DYN_CTL01_SW_ITR_INDX_ENA_SHIFT 24
-#define IAVFINT_DYN_CTL01_SW_ITR_INDX_ENA_MASK IAVF_MASK(0x1, IAVFINT_DYN_CTL01_SW_ITR_INDX_ENA_SHIFT)
-#define IAVFINT_DYN_CTL01_SW_ITR_INDX_SHIFT 25
-#define IAVFINT_DYN_CTL01_SW_ITR_INDX_MASK IAVF_MASK(0x3, IAVFINT_DYN_CTL01_SW_ITR_INDX_SHIFT)
-#define IAVFINT_DYN_CTL01_INTENA_MSK_SHIFT 31
-#define IAVFINT_DYN_CTL01_INTENA_MSK_MASK IAVF_MASK(0x1, IAVFINT_DYN_CTL01_INTENA_MSK_SHIFT)
-#define IAVFINT_DYN_CTLN1(_INTVF) (0x00003800 + ((_INTVF) * 4)) /* _i=0...15 */ /* Reset: VFR */
-#define IAVFINT_DYN_CTLN1_MAX_INDEX 15
-#define IAVFINT_DYN_CTLN1_INTENA_SHIFT 0
-#define IAVFINT_DYN_CTLN1_INTENA_MASK IAVF_MASK(0x1, IAVFINT_DYN_CTLN1_INTENA_SHIFT)
-#define IAVFINT_DYN_CTLN1_CLEARPBA_SHIFT 1
-#define IAVFINT_DYN_CTLN1_CLEARPBA_MASK IAVF_MASK(0x1, IAVFINT_DYN_CTLN1_CLEARPBA_SHIFT)
-#define IAVFINT_DYN_CTLN1_SWINT_TRIG_SHIFT 2
-#define IAVFINT_DYN_CTLN1_SWINT_TRIG_MASK IAVF_MASK(0x1, IAVFINT_DYN_CTLN1_SWINT_TRIG_SHIFT)
-#define IAVFINT_DYN_CTLN1_ITR_INDX_SHIFT 3
-#define IAVFINT_DYN_CTLN1_ITR_INDX_MASK IAVF_MASK(0x3, IAVFINT_DYN_CTLN1_ITR_INDX_SHIFT)
-#define IAVFINT_DYN_CTLN1_INTERVAL_SHIFT 5
-#define IAVFINT_DYN_CTLN1_INTERVAL_MASK IAVF_MASK(0xFFF, IAVFINT_DYN_CTLN1_INTERVAL_SHIFT)
-#define IAVFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT 24
-#define IAVFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK IAVF_MASK(0x1, IAVFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT)
-#define IAVFINT_DYN_CTLN1_SW_ITR_INDX_SHIFT 25
-#define IAVFINT_DYN_CTLN1_SW_ITR_INDX_MASK IAVF_MASK(0x3, IAVFINT_DYN_CTLN1_SW_ITR_INDX_SHIFT)
-#define IAVFINT_DYN_CTLN1_INTENA_MSK_SHIFT 31
-#define IAVFINT_DYN_CTLN1_INTENA_MSK_MASK IAVF_MASK(0x1, IAVFINT_DYN_CTLN1_INTENA_MSK_SHIFT)
-#define IAVFINT_ICR0_ENA1 0x00005000 /* Reset: CORER */
-#define IAVFINT_ICR0_ENA1_LINK_STAT_CHANGE_SHIFT 25
-#define IAVFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK IAVF_MASK(0x1, IAVFINT_ICR0_ENA1_LINK_STAT_CHANGE_SHIFT)
-#define IAVFINT_ICR0_ENA1_ADMINQ_SHIFT 30
-#define IAVFINT_ICR0_ENA1_ADMINQ_MASK IAVF_MASK(0x1, IAVFINT_ICR0_ENA1_ADMINQ_SHIFT)
-#define IAVFINT_ICR0_ENA1_RSVD_SHIFT 31
-#define IAVFINT_ICR0_ENA1_RSVD_MASK IAVF_MASK(0x1, IAVFINT_ICR0_ENA1_RSVD_SHIFT)
-#define IAVFINT_ICR01 0x00004800 /* Reset: CORER */
-#define IAVFINT_ICR01_INTEVENT_SHIFT 0
-#define IAVFINT_ICR01_INTEVENT_MASK IAVF_MASK(0x1, IAVFINT_ICR01_INTEVENT_SHIFT)
-#define IAVFINT_ICR01_QUEUE_0_SHIFT 1
-#define IAVFINT_ICR01_QUEUE_0_MASK IAVF_MASK(0x1, IAVFINT_ICR01_QUEUE_0_SHIFT)
-#define IAVFINT_ICR01_QUEUE_1_SHIFT 2
-#define IAVFINT_ICR01_QUEUE_1_MASK IAVF_MASK(0x1, IAVFINT_ICR01_QUEUE_1_SHIFT)
-#define IAVFINT_ICR01_QUEUE_2_SHIFT 3
-#define IAVFINT_ICR01_QUEUE_2_MASK IAVF_MASK(0x1, IAVFINT_ICR01_QUEUE_2_SHIFT)
-#define IAVFINT_ICR01_QUEUE_3_SHIFT 4
-#define IAVFINT_ICR01_QUEUE_3_MASK IAVF_MASK(0x1, IAVFINT_ICR01_QUEUE_3_SHIFT)
-#define IAVFINT_ICR01_LINK_STAT_CHANGE_SHIFT 25
-#define IAVFINT_ICR01_LINK_STAT_CHANGE_MASK IAVF_MASK(0x1, IAVFINT_ICR01_LINK_STAT_CHANGE_SHIFT)
-#define IAVFINT_ICR01_ADMINQ_SHIFT 30
-#define IAVFINT_ICR01_ADMINQ_MASK IAVF_MASK(0x1, IAVFINT_ICR01_ADMINQ_SHIFT)
-#define IAVFINT_ICR01_SWINT_SHIFT 31
-#define IAVFINT_ICR01_SWINT_MASK IAVF_MASK(0x1, IAVFINT_ICR01_SWINT_SHIFT)
-#define IAVFINT_ITR01(_i) (0x00004C00 + ((_i) * 4)) /* _i=0...2 */ /* Reset: VFR */
-#define IAVFINT_ITR01_MAX_INDEX 2
-#define IAVFINT_ITR01_INTERVAL_SHIFT 0
-#define IAVFINT_ITR01_INTERVAL_MASK IAVF_MASK(0xFFF, IAVFINT_ITR01_INTERVAL_SHIFT)
-#define IAVFINT_ITRN1(_i, _INTVF) (0x00002800 + ((_i) * 64 + (_INTVF) * 4)) /* _i=0...2, _INTVF=0...15 */ /* Reset: VFR */
-#define IAVFINT_ITRN1_MAX_INDEX 2
-#define IAVFINT_ITRN1_INTERVAL_SHIFT 0
-#define IAVFINT_ITRN1_INTERVAL_MASK IAVF_MASK(0xFFF, IAVFINT_ITRN1_INTERVAL_SHIFT)
-#define IAVFINT_STAT_CTL01 0x00005400 /* Reset: CORER */
-#define IAVFINT_STAT_CTL01_OTHER_ITR_INDX_SHIFT 2
-#define IAVFINT_STAT_CTL01_OTHER_ITR_INDX_MASK IAVF_MASK(0x3, IAVFINT_STAT_CTL01_OTHER_ITR_INDX_SHIFT)
+#define IAVF_VF_ARQBAH1 0x00006000 /* Reset: EMPR */
+#define IAVF_VF_ARQBAL1 0x00006C00 /* Reset: EMPR */
+#define IAVF_VF_ARQH1 0x00007400 /* Reset: EMPR */
+#define IAVF_VF_ARQH1_ARQH_SHIFT 0
+#define IAVF_VF_ARQH1_ARQH_MASK IAVF_MASK(0x3FF, IAVF_VF_ARQH1_ARQH_SHIFT)
+#define IAVF_VF_ARQLEN1 0x00008000 /* Reset: EMPR */
+#define IAVF_VF_ARQLEN1_ARQVFE_SHIFT 28
+#define IAVF_VF_ARQLEN1_ARQVFE_MASK IAVF_MASK(1UL, IAVF_VF_ARQLEN1_ARQVFE_SHIFT)
+#define IAVF_VF_ARQLEN1_ARQOVFL_SHIFT 29
+#define IAVF_VF_ARQLEN1_ARQOVFL_MASK IAVF_MASK(1UL, IAVF_VF_ARQLEN1_ARQOVFL_SHIFT)
+#define IAVF_VF_ARQLEN1_ARQCRIT_SHIFT 30
+#define IAVF_VF_ARQLEN1_ARQCRIT_MASK IAVF_MASK(1UL, IAVF_VF_ARQLEN1_ARQCRIT_SHIFT)
+#define IAVF_VF_ARQLEN1_ARQENABLE_SHIFT 31
+#define IAVF_VF_ARQLEN1_ARQENABLE_MASK IAVF_MASK(1UL, IAVF_VF_ARQLEN1_ARQENABLE_SHIFT)
+#define IAVF_VF_ARQT1 0x00007000 /* Reset: EMPR */
+#define IAVF_VF_ATQBAH1 0x00007800 /* Reset: EMPR */
+#define IAVF_VF_ATQBAL1 0x00007C00 /* Reset: EMPR */
+#define IAVF_VF_ATQH1 0x00006400 /* Reset: EMPR */
+#define IAVF_VF_ATQLEN1 0x00006800 /* Reset: EMPR */
+#define IAVF_VF_ATQLEN1_ATQVFE_SHIFT 28
+#define IAVF_VF_ATQLEN1_ATQVFE_MASK IAVF_MASK(1UL, IAVF_VF_ATQLEN1_ATQVFE_SHIFT)
+#define IAVF_VF_ATQLEN1_ATQOVFL_SHIFT 29
+#define IAVF_VF_ATQLEN1_ATQOVFL_MASK IAVF_MASK(1UL, IAVF_VF_ATQLEN1_ATQOVFL_SHIFT)
+#define IAVF_VF_ATQLEN1_ATQCRIT_SHIFT 30
+#define IAVF_VF_ATQLEN1_ATQCRIT_MASK IAVF_MASK(1UL, IAVF_VF_ATQLEN1_ATQCRIT_SHIFT)
+#define IAVF_VF_ATQLEN1_ATQENABLE_SHIFT 31
+#define IAVF_VF_ATQLEN1_ATQENABLE_MASK IAVF_MASK(1UL, IAVF_VF_ATQLEN1_ATQENABLE_SHIFT)
+#define IAVF_VF_ATQT1 0x00008400 /* Reset: EMPR */
+#define IAVF_VFGEN_RSTAT 0x00008800 /* Reset: VFR */
+#define IAVF_VFGEN_RSTAT_VFR_STATE_SHIFT 0
+#define IAVF_VFGEN_RSTAT_VFR_STATE_MASK IAVF_MASK(0x3, IAVF_VFGEN_RSTAT_VFR_STATE_SHIFT)
+#define IAVF_VFINT_DYN_CTL01 0x00005C00 /* Reset: VFR */
+#define IAVF_VFINT_DYN_CTL01_INTENA_SHIFT 0
+#define IAVF_VFINT_DYN_CTL01_INTENA_MASK IAVF_MASK(1UL, IAVF_VFINT_DYN_CTL01_INTENA_SHIFT)
+#define IAVF_VFINT_DYN_CTL01_CLEARPBA_SHIFT 1
+#define IAVF_VFINT_DYN_CTL01_CLEARPBA_MASK IAVF_MASK(1UL, IAVF_VFINT_DYN_CTL01_CLEARPBA_SHIFT)
+#define IAVF_VFINT_DYN_CTL01_SWINT_TRIG_SHIFT 2
+#define IAVF_VFINT_DYN_CTL01_SWINT_TRIG_MASK IAVF_MASK(1UL, IAVF_VFINT_DYN_CTL01_SWINT_TRIG_SHIFT)
+#define IAVF_VFINT_DYN_CTL01_ITR_INDX_SHIFT 3
+#define IAVF_VFINT_DYN_CTL01_ITR_INDX_MASK IAVF_MASK(0x3, IAVF_VFINT_DYN_CTL01_ITR_INDX_SHIFT)
+#define IAVF_VFINT_DYN_CTL01_INTERVAL_SHIFT 5
+#define IAVF_VFINT_DYN_CTL01_INTERVAL_MASK IAVF_MASK(0xFFF, IAVF_VFINT_DYN_CTL01_INTERVAL_SHIFT)
+#define IAVF_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_SHIFT 24
+#define IAVF_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_MASK IAVF_MASK(1UL, IAVF_VFINT_DYN_CTL01_SW_ITR_INDX_ENA_SHIFT)
+#define IAVF_VFINT_DYN_CTL01_SW_ITR_INDX_SHIFT 25
+#define IAVF_VFINT_DYN_CTL01_SW_ITR_INDX_MASK IAVF_MASK(0x3, IAVF_VFINT_DYN_CTL01_SW_ITR_INDX_SHIFT)
+#define IAVF_VFINT_DYN_CTLN1(_INTVF) (0x00003800 + ((_INTVF) * 4)) /* _i=0...15 */ /* Reset: VFR */
+#define IAVF_VFINT_DYN_CTLN1_INTENA_SHIFT 0
+#define IAVF_VFINT_DYN_CTLN1_INTENA_MASK IAVF_MASK(1UL, IAVF_VFINT_DYN_CTLN1_INTENA_SHIFT)
+#define IAVF_VFINT_DYN_CTLN1_CLEARPBA_SHIFT 1
+#define IAVF_VFINT_DYN_CTLN1_CLEARPBA_MASK IAVF_MASK(1UL, IAVF_VFINT_DYN_CTLN1_CLEARPBA_SHIFT)
+#define IAVF_VFINT_DYN_CTLN1_SWINT_TRIG_SHIFT 2
+#define IAVF_VFINT_DYN_CTLN1_SWINT_TRIG_MASK IAVF_MASK(1UL, IAVF_VFINT_DYN_CTLN1_SWINT_TRIG_SHIFT)
+#define IAVF_VFINT_DYN_CTLN1_ITR_INDX_SHIFT 3
+#define IAVF_VFINT_DYN_CTLN1_ITR_INDX_MASK IAVF_MASK(0x3, IAVF_VFINT_DYN_CTLN1_ITR_INDX_SHIFT)
+#define IAVF_VFINT_DYN_CTLN1_INTERVAL_SHIFT 5
+#define IAVF_VFINT_DYN_CTLN1_INTERVAL_MASK IAVF_MASK(0xFFF, IAVF_VFINT_DYN_CTLN1_INTERVAL_SHIFT)
+#define IAVF_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT 24
+#define IAVF_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK IAVF_MASK(1UL, IAVF_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT)
+#define IAVF_VFINT_DYN_CTLN1_SW_ITR_INDX_SHIFT 25
+#define IAVF_VFINT_DYN_CTLN1_SW_ITR_INDX_MASK IAVF_MASK(0x3, IAVF_VFINT_DYN_CTLN1_SW_ITR_INDX_SHIFT)
+#define IAVF_VFINT_ICR0_ENA1 0x00005000 /* Reset: CORER */
+#define IAVF_VFINT_ICR0_ENA1_ADMINQ_SHIFT 30
+#define IAVF_VFINT_ICR0_ENA1_ADMINQ_MASK IAVF_MASK(1UL, IAVF_VFINT_ICR0_ENA1_ADMINQ_SHIFT)
+#define IAVF_VFINT_ICR0_ENA1_RSVD_SHIFT 31
+#define IAVF_VFINT_ICR01 0x00004800 /* Reset: CORER */
+#define IAVF_VFINT_ICR01_QUEUE_0_SHIFT 1
+#define IAVF_VFINT_ICR01_QUEUE_0_MASK IAVF_MASK(1UL, IAVF_VFINT_ICR01_QUEUE_0_SHIFT)
+#define IAVF_VFINT_ICR01_LINK_STAT_CHANGE_SHIFT 25
+#define IAVF_VFINT_ICR01_LINK_STAT_CHANGE_MASK IAVF_MASK(1UL, IAVF_VFINT_ICR01_LINK_STAT_CHANGE_SHIFT)
+#define IAVF_VFINT_ICR01_ADMINQ_SHIFT 30
+#define IAVF_VFINT_ICR01_ADMINQ_MASK IAVF_MASK(1UL, IAVF_VFINT_ICR01_ADMINQ_SHIFT)
+#define IAVF_VFINT_ITR01(_i) (0x00004C00 + ((_i) * 4)) /* _i=0...2 */ /* Reset: VFR */
+#define IAVF_VFINT_ITRN1(_i, _INTVF) (0x00002800 + ((_i) * 64 + (_INTVF) * 4)) /* _i=0...2, _INTVF=0...15 */ /* Reset: VFR */
+#define IAVF_VFINT_STAT_CTL01 0x00005400 /* Reset: CORER */
#define IAVF_QRX_TAIL1(_Q) (0x00002000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: CORER */
-#define IAVF_QRX_TAIL1_MAX_INDEX 15
-#define IAVF_QRX_TAIL1_TAIL_SHIFT 0
-#define IAVF_QRX_TAIL1_TAIL_MASK IAVF_MASK(0x1FFF, IAVF_QRX_TAIL1_TAIL_SHIFT)
#define IAVF_QTX_TAIL1(_Q) (0x00000000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: PFR */
-#define IAVF_QTX_TAIL1_MAX_INDEX 15
-#define IAVF_QTX_TAIL1_TAIL_SHIFT 0
-#define IAVF_QTX_TAIL1_TAIL_MASK IAVF_MASK(0x1FFF, IAVF_QTX_TAIL1_TAIL_SHIFT)
-#define IAVFMSIX_PBA 0x00002000 /* Reset: VFLR */
-#define IAVFMSIX_PBA_PENBIT_SHIFT 0
-#define IAVFMSIX_PBA_PENBIT_MASK IAVF_MASK(0xFFFFFFFF, IAVFMSIX_PBA_PENBIT_SHIFT)
-#define IAVFMSIX_TADD(_i) (0x00000000 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */
-#define IAVFMSIX_TADD_MAX_INDEX 16
-#define IAVFMSIX_TADD_MSIXTADD10_SHIFT 0
-#define IAVFMSIX_TADD_MSIXTADD10_MASK IAVF_MASK(0x3, IAVFMSIX_TADD_MSIXTADD10_SHIFT)
-#define IAVFMSIX_TADD_MSIXTADD_SHIFT 2
-#define IAVFMSIX_TADD_MSIXTADD_MASK IAVF_MASK(0x3FFFFFFF, IAVFMSIX_TADD_MSIXTADD_SHIFT)
-#define IAVFMSIX_TMSG(_i) (0x00000008 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */
-#define IAVFMSIX_TMSG_MAX_INDEX 16
-#define IAVFMSIX_TMSG_MSIXTMSG_SHIFT 0
-#define IAVFMSIX_TMSG_MSIXTMSG_MASK IAVF_MASK(0xFFFFFFFF, IAVFMSIX_TMSG_MSIXTMSG_SHIFT)
-#define IAVFMSIX_TUADD(_i) (0x00000004 + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */
-#define IAVFMSIX_TUADD_MAX_INDEX 16
-#define IAVFMSIX_TUADD_MSIXTUADD_SHIFT 0
-#define IAVFMSIX_TUADD_MSIXTUADD_MASK IAVF_MASK(0xFFFFFFFF, IAVFMSIX_TUADD_MSIXTUADD_SHIFT)
-#define IAVFMSIX_TVCTRL(_i) (0x0000000C + ((_i) * 16)) /* _i=0...16 */ /* Reset: VFLR */
-#define IAVFMSIX_TVCTRL_MAX_INDEX 16
-#define IAVFMSIX_TVCTRL_MASK_SHIFT 0
-#define IAVFMSIX_TVCTRL_MASK_MASK IAVF_MASK(0x1, IAVFMSIX_TVCTRL_MASK_SHIFT)
-#define IAVFCM_PE_ERRDATA 0x0000DC00 /* Reset: VFR */
-#define IAVFCM_PE_ERRDATA_ERROR_CODE_SHIFT 0
-#define IAVFCM_PE_ERRDATA_ERROR_CODE_MASK IAVF_MASK(0xF, IAVFCM_PE_ERRDATA_ERROR_CODE_SHIFT)
-#define IAVFCM_PE_ERRDATA_Q_TYPE_SHIFT 4
-#define IAVFCM_PE_ERRDATA_Q_TYPE_MASK IAVF_MASK(0x7, IAVFCM_PE_ERRDATA_Q_TYPE_SHIFT)
-#define IAVFCM_PE_ERRDATA_Q_NUM_SHIFT 8
-#define IAVFCM_PE_ERRDATA_Q_NUM_MASK IAVF_MASK(0x3FFFF, IAVFCM_PE_ERRDATA_Q_NUM_SHIFT)
-#define IAVFCM_PE_ERRINFO 0x0000D800 /* Reset: VFR */
-#define IAVFCM_PE_ERRINFO_ERROR_VALID_SHIFT 0
-#define IAVFCM_PE_ERRINFO_ERROR_VALID_MASK IAVF_MASK(0x1, IAVFCM_PE_ERRINFO_ERROR_VALID_SHIFT)
-#define IAVFCM_PE_ERRINFO_ERROR_INST_SHIFT 4
-#define IAVFCM_PE_ERRINFO_ERROR_INST_MASK IAVF_MASK(0x7, IAVFCM_PE_ERRINFO_ERROR_INST_SHIFT)
-#define IAVFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT 8
-#define IAVFCM_PE_ERRINFO_DBL_ERROR_CNT_MASK IAVF_MASK(0xFF, IAVFCM_PE_ERRINFO_DBL_ERROR_CNT_SHIFT)
-#define IAVFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT 16
-#define IAVFCM_PE_ERRINFO_RLU_ERROR_CNT_MASK IAVF_MASK(0xFF, IAVFCM_PE_ERRINFO_RLU_ERROR_CNT_SHIFT)
-#define IAVFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT 24
-#define IAVFCM_PE_ERRINFO_RLS_ERROR_CNT_MASK IAVF_MASK(0xFF, IAVFCM_PE_ERRINFO_RLS_ERROR_CNT_SHIFT)
-#define IAVFQF_HENA(_i) (0x0000C400 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */
-#define IAVFQF_HENA_MAX_INDEX 1
-#define IAVFQF_HENA_PTYPE_ENA_SHIFT 0
-#define IAVFQF_HENA_PTYPE_ENA_MASK IAVF_MASK(0xFFFFFFFF, IAVFQF_HENA_PTYPE_ENA_SHIFT)
-#define IAVFQF_HKEY(_i) (0x0000CC00 + ((_i) * 4)) /* _i=0...12 */ /* Reset: CORER */
-#define IAVFQF_HKEY_MAX_INDEX 12
-#define IAVFQF_HKEY_KEY_0_SHIFT 0
-#define IAVFQF_HKEY_KEY_0_MASK IAVF_MASK(0xFF, IAVFQF_HKEY_KEY_0_SHIFT)
-#define IAVFQF_HKEY_KEY_1_SHIFT 8
-#define IAVFQF_HKEY_KEY_1_MASK IAVF_MASK(0xFF, IAVFQF_HKEY_KEY_1_SHIFT)
-#define IAVFQF_HKEY_KEY_2_SHIFT 16
-#define IAVFQF_HKEY_KEY_2_MASK IAVF_MASK(0xFF, IAVFQF_HKEY_KEY_2_SHIFT)
-#define IAVFQF_HKEY_KEY_3_SHIFT 24
-#define IAVFQF_HKEY_KEY_3_MASK IAVF_MASK(0xFF, IAVFQF_HKEY_KEY_3_SHIFT)
-#define IAVFQF_HLUT(_i) (0x0000D000 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
-#define IAVFQF_HLUT_MAX_INDEX 15
-#define IAVFQF_HLUT_LUT0_SHIFT 0
-#define IAVFQF_HLUT_LUT0_MASK IAVF_MASK(0xF, IAVFQF_HLUT_LUT0_SHIFT)
-#define IAVFQF_HLUT_LUT1_SHIFT 8
-#define IAVFQF_HLUT_LUT1_MASK IAVF_MASK(0xF, IAVFQF_HLUT_LUT1_SHIFT)
-#define IAVFQF_HLUT_LUT2_SHIFT 16
-#define IAVFQF_HLUT_LUT2_MASK IAVF_MASK(0xF, IAVFQF_HLUT_LUT2_SHIFT)
-#define IAVFQF_HLUT_LUT3_SHIFT 24
-#define IAVFQF_HLUT_LUT3_MASK IAVF_MASK(0xF, IAVFQF_HLUT_LUT3_SHIFT)
-#define IAVFQF_HREGION(_i) (0x0000D400 + ((_i) * 4)) /* _i=0...7 */ /* Reset: CORER */
-#define IAVFQF_HREGION_MAX_INDEX 7
-#define IAVFQF_HREGION_OVERRIDE_ENA_0_SHIFT 0
-#define IAVFQF_HREGION_OVERRIDE_ENA_0_MASK IAVF_MASK(0x1, IAVFQF_HREGION_OVERRIDE_ENA_0_SHIFT)
-#define IAVFQF_HREGION_REGION_0_SHIFT 1
-#define IAVFQF_HREGION_REGION_0_MASK IAVF_MASK(0x7, IAVFQF_HREGION_REGION_0_SHIFT)
-#define IAVFQF_HREGION_OVERRIDE_ENA_1_SHIFT 4
-#define IAVFQF_HREGION_OVERRIDE_ENA_1_MASK IAVF_MASK(0x1, IAVFQF_HREGION_OVERRIDE_ENA_1_SHIFT)
-#define IAVFQF_HREGION_REGION_1_SHIFT 5
-#define IAVFQF_HREGION_REGION_1_MASK IAVF_MASK(0x7, IAVFQF_HREGION_REGION_1_SHIFT)
-#define IAVFQF_HREGION_OVERRIDE_ENA_2_SHIFT 8
-#define IAVFQF_HREGION_OVERRIDE_ENA_2_MASK IAVF_MASK(0x1, IAVFQF_HREGION_OVERRIDE_ENA_2_SHIFT)
-#define IAVFQF_HREGION_REGION_2_SHIFT 9
-#define IAVFQF_HREGION_REGION_2_MASK IAVF_MASK(0x7, IAVFQF_HREGION_REGION_2_SHIFT)
-#define IAVFQF_HREGION_OVERRIDE_ENA_3_SHIFT 12
-#define IAVFQF_HREGION_OVERRIDE_ENA_3_MASK IAVF_MASK(0x1, IAVFQF_HREGION_OVERRIDE_ENA_3_SHIFT)
-#define IAVFQF_HREGION_REGION_3_SHIFT 13
-#define IAVFQF_HREGION_REGION_3_MASK IAVF_MASK(0x7, IAVFQF_HREGION_REGION_3_SHIFT)
-#define IAVFQF_HREGION_OVERRIDE_ENA_4_SHIFT 16
-#define IAVFQF_HREGION_OVERRIDE_ENA_4_MASK IAVF_MASK(0x1, IAVFQF_HREGION_OVERRIDE_ENA_4_SHIFT)
-#define IAVFQF_HREGION_REGION_4_SHIFT 17
-#define IAVFQF_HREGION_REGION_4_MASK IAVF_MASK(0x7, IAVFQF_HREGION_REGION_4_SHIFT)
-#define IAVFQF_HREGION_OVERRIDE_ENA_5_SHIFT 20
-#define IAVFQF_HREGION_OVERRIDE_ENA_5_MASK IAVF_MASK(0x1, IAVFQF_HREGION_OVERRIDE_ENA_5_SHIFT)
-#define IAVFQF_HREGION_REGION_5_SHIFT 21
-#define IAVFQF_HREGION_REGION_5_MASK IAVF_MASK(0x7, IAVFQF_HREGION_REGION_5_SHIFT)
-#define IAVFQF_HREGION_OVERRIDE_ENA_6_SHIFT 24
-#define IAVFQF_HREGION_OVERRIDE_ENA_6_MASK IAVF_MASK(0x1, IAVFQF_HREGION_OVERRIDE_ENA_6_SHIFT)
-#define IAVFQF_HREGION_REGION_6_SHIFT 25
-#define IAVFQF_HREGION_REGION_6_MASK IAVF_MASK(0x7, IAVFQF_HREGION_REGION_6_SHIFT)
-#define IAVFQF_HREGION_OVERRIDE_ENA_7_SHIFT 28
-#define IAVFQF_HREGION_OVERRIDE_ENA_7_MASK IAVF_MASK(0x1, IAVFQF_HREGION_OVERRIDE_ENA_7_SHIFT)
-#define IAVFQF_HREGION_REGION_7_SHIFT 29
-#define IAVFQF_HREGION_REGION_7_MASK IAVF_MASK(0x7, IAVFQF_HREGION_REGION_7_SHIFT)
-
-#define IAVFINT_DYN_CTL01_WB_ON_ITR_SHIFT 30
-#define IAVFINT_DYN_CTL01_WB_ON_ITR_MASK IAVF_MASK(0x1, IAVFINT_DYN_CTL01_WB_ON_ITR_SHIFT)
-#define IAVFINT_DYN_CTLN1_WB_ON_ITR_SHIFT 30
-#define IAVFINT_DYN_CTLN1_WB_ON_ITR_MASK IAVF_MASK(0x1, IAVFINT_DYN_CTLN1_WB_ON_ITR_SHIFT)
-#define IAVFPE_AEQALLOC1 0x0000A400 /* Reset: VFR */
-#define IAVFPE_AEQALLOC1_AECOUNT_SHIFT 0
-#define IAVFPE_AEQALLOC1_AECOUNT_MASK IAVF_MASK(0xFFFFFFFF, IAVFPE_AEQALLOC1_AECOUNT_SHIFT)
-#define IAVFPE_CCQPHIGH1 0x00009800 /* Reset: VFR */
-#define IAVFPE_CCQPHIGH1_PECCQPHIGH_SHIFT 0
-#define IAVFPE_CCQPHIGH1_PECCQPHIGH_MASK IAVF_MASK(0xFFFFFFFF, IAVFPE_CCQPHIGH1_PECCQPHIGH_SHIFT)
-#define IAVFPE_CCQPLOW1 0x0000AC00 /* Reset: VFR */
-#define IAVFPE_CCQPLOW1_PECCQPLOW_SHIFT 0
-#define IAVFPE_CCQPLOW1_PECCQPLOW_MASK IAVF_MASK(0xFFFFFFFF, IAVFPE_CCQPLOW1_PECCQPLOW_SHIFT)
-#define IAVFPE_CCQPSTATUS1 0x0000B800 /* Reset: VFR */
-#define IAVFPE_CCQPSTATUS1_CCQP_DONE_SHIFT 0
-#define IAVFPE_CCQPSTATUS1_CCQP_DONE_MASK IAVF_MASK(0x1, IAVFPE_CCQPSTATUS1_CCQP_DONE_SHIFT)
-#define IAVFPE_CCQPSTATUS1_HMC_PROFILE_SHIFT 4
-#define IAVFPE_CCQPSTATUS1_HMC_PROFILE_MASK IAVF_MASK(0x7, IAVFPE_CCQPSTATUS1_HMC_PROFILE_SHIFT)
-#define IAVFPE_CCQPSTATUS1_RDMA_EN_VFS_SHIFT 16
-#define IAVFPE_CCQPSTATUS1_RDMA_EN_VFS_MASK IAVF_MASK(0x3F, IAVFPE_CCQPSTATUS1_RDMA_EN_VFS_SHIFT)
-#define IAVFPE_CCQPSTATUS1_CCQP_ERR_SHIFT 31
-#define IAVFPE_CCQPSTATUS1_CCQP_ERR_MASK IAVF_MASK(0x1, IAVFPE_CCQPSTATUS1_CCQP_ERR_SHIFT)
-#define IAVFPE_CQACK1 0x0000B000 /* Reset: VFR */
-#define IAVFPE_CQACK1_PECQID_SHIFT 0
-#define IAVFPE_CQACK1_PECQID_MASK IAVF_MASK(0x1FFFF, IAVFPE_CQACK1_PECQID_SHIFT)
-#define IAVFPE_CQARM1 0x0000B400 /* Reset: VFR */
-#define IAVFPE_CQARM1_PECQID_SHIFT 0
-#define IAVFPE_CQARM1_PECQID_MASK IAVF_MASK(0x1FFFF, IAVFPE_CQARM1_PECQID_SHIFT)
-#define IAVFPE_CQPDB1 0x0000BC00 /* Reset: VFR */
-#define IAVFPE_CQPDB1_WQHEAD_SHIFT 0
-#define IAVFPE_CQPDB1_WQHEAD_MASK IAVF_MASK(0x7FF, IAVFPE_CQPDB1_WQHEAD_SHIFT)
-#define IAVFPE_CQPERRCODES1 0x00009C00 /* Reset: VFR */
-#define IAVFPE_CQPERRCODES1_CQP_MINOR_CODE_SHIFT 0
-#define IAVFPE_CQPERRCODES1_CQP_MINOR_CODE_MASK IAVF_MASK(0xFFFF, IAVFPE_CQPERRCODES1_CQP_MINOR_CODE_SHIFT)
-#define IAVFPE_CQPERRCODES1_CQP_MAJOR_CODE_SHIFT 16
-#define IAVFPE_CQPERRCODES1_CQP_MAJOR_CODE_MASK IAVF_MASK(0xFFFF, IAVFPE_CQPERRCODES1_CQP_MAJOR_CODE_SHIFT)
-#define IAVFPE_CQPTAIL1 0x0000A000 /* Reset: VFR */
-#define IAVFPE_CQPTAIL1_WQTAIL_SHIFT 0
-#define IAVFPE_CQPTAIL1_WQTAIL_MASK IAVF_MASK(0x7FF, IAVFPE_CQPTAIL1_WQTAIL_SHIFT)
-#define IAVFPE_CQPTAIL1_CQP_OP_ERR_SHIFT 31
-#define IAVFPE_CQPTAIL1_CQP_OP_ERR_MASK IAVF_MASK(0x1, IAVFPE_CQPTAIL1_CQP_OP_ERR_SHIFT)
-#define IAVFPE_IPCONFIG01 0x00008C00 /* Reset: VFR */
-#define IAVFPE_IPCONFIG01_PEIPID_SHIFT 0
-#define IAVFPE_IPCONFIG01_PEIPID_MASK IAVF_MASK(0xFFFF, IAVFPE_IPCONFIG01_PEIPID_SHIFT)
-#define IAVFPE_IPCONFIG01_USEENTIREIDRANGE_SHIFT 16
-#define IAVFPE_IPCONFIG01_USEENTIREIDRANGE_MASK IAVF_MASK(0x1, IAVFPE_IPCONFIG01_USEENTIREIDRANGE_SHIFT)
-#define IAVFPE_MRTEIDXMASK1 0x00009000 /* Reset: VFR */
-#define IAVFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_SHIFT 0
-#define IAVFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_MASK IAVF_MASK(0x1F, IAVFPE_MRTEIDXMASK1_MRTEIDXMASKBITS_SHIFT)
-#define IAVFPE_RCVUNEXPECTEDERROR1 0x00009400 /* Reset: VFR */
-#define IAVFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_SHIFT 0
-#define IAVFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_MASK IAVF_MASK(0xFFFFFF, IAVFPE_RCVUNEXPECTEDERROR1_TCP_RX_UNEXP_ERR_SHIFT)
-#define IAVFPE_TCPNOWTIMER1 0x0000A800 /* Reset: VFR */
-#define IAVFPE_TCPNOWTIMER1_TCP_NOW_SHIFT 0
-#define IAVFPE_TCPNOWTIMER1_TCP_NOW_MASK IAVF_MASK(0xFFFFFFFF, IAVFPE_TCPNOWTIMER1_TCP_NOW_SHIFT)
-#define IAVFPE_WQEALLOC1 0x0000C000 /* Reset: VFR */
-#define IAVFPE_WQEALLOC1_PEQPID_SHIFT 0
-#define IAVFPE_WQEALLOC1_PEQPID_MASK IAVF_MASK(0x3FFFF, IAVFPE_WQEALLOC1_PEQPID_SHIFT)
-#define IAVFPE_WQEALLOC1_WQE_DESC_INDEX_SHIFT 20
-#define IAVFPE_WQEALLOC1_WQE_DESC_INDEX_MASK IAVF_MASK(0xFFF, IAVFPE_WQEALLOC1_WQE_DESC_INDEX_SHIFT)
+#define IAVF_VFQF_HENA(_i) (0x0000C400 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */
+#define IAVF_VFQF_HKEY(_i) (0x0000CC00 + ((_i) * 4)) /* _i=0...12 */ /* Reset: CORER */
+#define IAVF_VFQF_HKEY_MAX_INDEX 12
+#define IAVF_VFQF_HLUT(_i) (0x0000D000 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
+#define IAVF_VFQF_HLUT_MAX_INDEX 15
+#define IAVF_VFINT_DYN_CTLN1_WB_ON_ITR_SHIFT 30
+#define IAVF_VFINT_DYN_CTLN1_WB_ON_ITR_MASK IAVF_MASK(1UL, IAVF_VFINT_DYN_CTLN1_WB_ON_ITR_SHIFT)
#endif /* _IAVF_REGISTER_H_ */
diff --git a/drivers/net/iavf/iavf_ethdev.c b/drivers/net/iavf/iavf_ethdev.c
index 4f80113ae..39faf7fac 100644
--- a/drivers/net/iavf/iavf_ethdev.c
+++ b/drivers/net/iavf/iavf_ethdev.c
@@ -323,9 +323,10 @@ static int iavf_config_rx_queues_irqs(struct rte_eth_dev *dev,
VIRTCHNL_VF_OFFLOAD_WB_ON_ITR) {
/* If WB_ON_ITR supports, enable it */
vf->msix_base = IAVF_RX_VEC_START;
- IAVF_WRITE_REG(hw, IAVFINT_DYN_CTLN1(vf->msix_base - 1),
- IAVFINT_DYN_CTLN1_ITR_INDX_MASK |
- IAVFINT_DYN_CTLN1_WB_ON_ITR_MASK);
+ IAVF_WRITE_REG(hw,
+ IAVF_VFINT_DYN_CTLN1(vf->msix_base - 1),
+ IAVF_VFINT_DYN_CTLN1_ITR_INDX_MASK |
+ IAVF_VFINT_DYN_CTLN1_WB_ON_ITR_MASK);
} else {
/* If no WB_ON_ITR offload flags, need to set
* interrupt for descriptor write back.
@@ -335,12 +336,12 @@ static int iavf_config_rx_queues_irqs(struct rte_eth_dev *dev,
/* set ITR to max */
interval = iavf_calc_itr_interval(
IAVF_QUEUE_ITR_INTERVAL_MAX);
- IAVF_WRITE_REG(hw, IAVFINT_DYN_CTL01,
- IAVFINT_DYN_CTL01_INTENA_MASK |
- (IAVF_ITR_INDEX_DEFAULT <<
- IAVFINT_DYN_CTL01_ITR_INDX_SHIFT) |
- (interval <<
- IAVFINT_DYN_CTL01_INTERVAL_SHIFT));
+ IAVF_WRITE_REG(hw, IAVF_VFINT_DYN_CTL01,
+ IAVF_VFINT_DYN_CTL01_INTENA_MASK |
+ (IAVF_ITR_INDEX_DEFAULT <<
+ IAVF_VFINT_DYN_CTL01_ITR_INDX_SHIFT) |
+ (interval <<
+ IAVF_VFINT_DYN_CTL01_INTERVAL_SHIFT));
}
IAVF_WRITE_FLUSH(hw);
/* map all queues to the same interrupt */
@@ -1115,16 +1116,17 @@ iavf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
msix_intr = pci_dev->intr_handle.intr_vec[queue_id];
if (msix_intr == IAVF_MISC_VEC_ID) {
PMD_DRV_LOG(INFO, "MISC is also enabled for control");
- IAVF_WRITE_REG(hw, IAVFINT_DYN_CTL01,
- IAVFINT_DYN_CTL01_INTENA_MASK |
- IAVFINT_DYN_CTL01_CLEARPBA_MASK |
- IAVFINT_DYN_CTL01_ITR_INDX_MASK);
+ IAVF_WRITE_REG(hw, IAVF_VFINT_DYN_CTL01,
+ IAVF_VFINT_DYN_CTL01_INTENA_MASK |
+ IAVF_VFINT_DYN_CTL01_CLEARPBA_MASK |
+ IAVF_VFINT_DYN_CTL01_ITR_INDX_MASK);
} else {
IAVF_WRITE_REG(hw,
- IAVFINT_DYN_CTLN1(msix_intr - IAVF_RX_VEC_START),
- IAVFINT_DYN_CTLN1_INTENA_MASK |
- IAVFINT_DYN_CTL01_CLEARPBA_MASK |
- IAVFINT_DYN_CTLN1_ITR_INDX_MASK);
+ IAVF_VFINT_DYN_CTLN1
+ (msix_intr - IAVF_RX_VEC_START),
+ IAVF_VFINT_DYN_CTLN1_INTENA_MASK |
+ IAVF_VFINT_DYN_CTL01_CLEARPBA_MASK |
+ IAVF_VFINT_DYN_CTLN1_ITR_INDX_MASK);
}
IAVF_WRITE_FLUSH(hw);
@@ -1148,7 +1150,7 @@ iavf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
}
IAVF_WRITE_REG(hw,
- IAVFINT_DYN_CTLN1(msix_intr - IAVF_RX_VEC_START),
+ IAVF_VFINT_DYN_CTLN1(msix_intr - IAVF_RX_VEC_START),
0);
IAVF_WRITE_FLUSH(hw);
@@ -1161,9 +1163,9 @@ iavf_check_vf_reset_done(struct iavf_hw *hw)
int i, reset;
for (i = 0; i < IAVF_RESET_WAIT_CNT; i++) {
- reset = IAVF_READ_REG(hw, IAVFGEN_RSTAT) &
- IAVFGEN_RSTAT_VFR_STATE_MASK;
- reset = reset >> IAVFGEN_RSTAT_VFR_STATE_SHIFT;
+ reset = IAVF_READ_REG(hw, IAVF_VFGEN_RSTAT) &
+ IAVF_VFGEN_RSTAT_VFR_STATE_MASK;
+ reset = reset >> IAVF_VFGEN_RSTAT_VFR_STATE_SHIFT;
if (reset == VIRTCHNL_VFR_VFACTIVE ||
reset == VIRTCHNL_VFR_COMPLETED)
break;
@@ -1260,10 +1262,13 @@ static inline void
iavf_enable_irq0(struct iavf_hw *hw)
{
/* Enable admin queue interrupt trigger */
- IAVF_WRITE_REG(hw, IAVFINT_ICR0_ENA1, IAVFINT_ICR0_ENA1_ADMINQ_MASK);
+ IAVF_WRITE_REG(hw, IAVF_VFINT_ICR0_ENA1,
+ IAVF_VFINT_ICR0_ENA1_ADMINQ_MASK);
- IAVF_WRITE_REG(hw, IAVFINT_DYN_CTL01, IAVFINT_DYN_CTL01_INTENA_MASK |
- IAVFINT_DYN_CTL01_CLEARPBA_MASK | IAVFINT_DYN_CTL01_ITR_INDX_MASK);
+ IAVF_WRITE_REG(hw, IAVF_VFINT_DYN_CTL01,
+ IAVF_VFINT_DYN_CTL01_INTENA_MASK |
+ IAVF_VFINT_DYN_CTL01_CLEARPBA_MASK |
+ IAVF_VFINT_DYN_CTL01_ITR_INDX_MASK);
IAVF_WRITE_FLUSH(hw);
}
@@ -1272,9 +1277,9 @@ static inline void
iavf_disable_irq0(struct iavf_hw *hw)
{
/* Disable all interrupt types */
- IAVF_WRITE_REG(hw, IAVFINT_ICR0_ENA1, 0);
- IAVF_WRITE_REG(hw, IAVFINT_DYN_CTL01,
- IAVFINT_DYN_CTL01_ITR_INDX_MASK);
+ IAVF_WRITE_REG(hw, IAVF_VFINT_ICR0_ENA1, 0);
+ IAVF_WRITE_REG(hw, IAVF_VFINT_DYN_CTL01,
+ IAVF_VFINT_DYN_CTL01_ITR_INDX_MASK);
IAVF_WRITE_FLUSH(hw);
}
--
2.13.6
^ permalink raw reply [flat|nested] 21+ messages in thread* [dpdk-dev] [PATCH 04/17] net/iavf/base: update device id
2019-12-03 7:03 [dpdk-dev] [PATCH 00/17] iavf base code update Qi Zhang
` (2 preceding siblings ...)
2019-12-03 7:03 ` [dpdk-dev] [PATCH 03/17] net/iavf/base: rename register macro Qi Zhang
@ 2019-12-03 7:03 ` Qi Zhang
2019-12-03 7:03 ` [dpdk-dev] [PATCH 05/17] net/iavf/base: remove unused code Qi Zhang
` (13 subsequent siblings)
17 siblings, 0 replies; 21+ messages in thread
From: Qi Zhang @ 2019-12-03 7:03 UTC (permalink / raw)
To: xiaolong.ye; +Cc: haiyue.wang, dev, Qi Zhang, Paul M Stillwell Jr
Add all supported device id.
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/iavf/base/iavf_common.c | 8 +++++---
drivers/net/iavf/base/iavf_devids.h | 5 ++++-
2 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/drivers/net/iavf/base/iavf_common.c b/drivers/net/iavf/base/iavf_common.c
index 5df4410e0..026dc4756 100644
--- a/drivers/net/iavf/base/iavf_common.c
+++ b/drivers/net/iavf/base/iavf_common.c
@@ -23,9 +23,11 @@ enum iavf_status iavf_set_mac_type(struct iavf_hw *hw)
if (hw->vendor_id == IAVF_INTEL_VENDOR_ID) {
switch (hw->device_id) {
- /* TODO: remove undefined device ID now, need to think how to
- * remove them in share code
- */
+ case IAVF_DEV_ID_X722_VF:
+ hw->mac.type = IAVF_MAC_X722_VF;
+ break;
+ case IAVF_DEV_ID_VF:
+ case IAVF_DEV_ID_VF_HV:
case IAVF_DEV_ID_ADAPTIVE_VF:
hw->mac.type = IAVF_MAC_VF;
break;
diff --git a/drivers/net/iavf/base/iavf_devids.h b/drivers/net/iavf/base/iavf_devids.h
index 2cd88d62f..cd92631f4 100644
--- a/drivers/net/iavf/base/iavf_devids.h
+++ b/drivers/net/iavf/base/iavf_devids.h
@@ -8,7 +8,10 @@
/* Vendor ID */
#define IAVF_INTEL_VENDOR_ID 0x8086
-/* Device IDs */
+/* Device IDs for the VF driver */
+#define IAVF_DEV_ID_VF 0x154C
+#define IAVF_DEV_ID_VF_HV 0x1571
#define IAVF_DEV_ID_ADAPTIVE_VF 0x1889
+#define IAVF_DEV_ID_X722_VF 0x37CD
#endif /* _IAVF_DEVIDS_H_ */
--
2.13.6
^ permalink raw reply [flat|nested] 21+ messages in thread* [dpdk-dev] [PATCH 05/17] net/iavf/base: remove unused code
2019-12-03 7:03 [dpdk-dev] [PATCH 00/17] iavf base code update Qi Zhang
` (3 preceding siblings ...)
2019-12-03 7:03 ` [dpdk-dev] [PATCH 04/17] net/iavf/base: update device id Qi Zhang
@ 2019-12-03 7:03 ` Qi Zhang
2019-12-03 7:03 ` [dpdk-dev] [PATCH 06/17] net/iavf/base: remove unnecessary compile option Qi Zhang
` (12 subsequent siblings)
17 siblings, 0 replies; 21+ messages in thread
From: Qi Zhang @ 2019-12-03 7:03 UTC (permalink / raw)
To: xiaolong.ye; +Cc: haiyue.wang, dev, Qi Zhang, Paul M Stillwell Jr
Remove unused APIs in iavf_prototype.h, iavf_adminq_cmd.h
iavf_type.h, iavf_adminq.h and iavf_common.c
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/iavf/base/iavf_adminq.c | 27 +-
drivers/net/iavf/base/iavf_adminq.h | 43 -
drivers/net/iavf/base/iavf_adminq_cmd.h | 2344 ++-----------------------------
drivers/net/iavf/base/iavf_common.c | 787 -----------
drivers/net/iavf/base/iavf_prototype.h | 83 --
drivers/net/iavf/base/iavf_type.h | 1109 +--------------
6 files changed, 168 insertions(+), 4225 deletions(-)
diff --git a/drivers/net/iavf/base/iavf_adminq.c b/drivers/net/iavf/base/iavf_adminq.c
index 193e2e7d1..68c51daac 100644
--- a/drivers/net/iavf/base/iavf_adminq.c
+++ b/drivers/net/iavf/base/iavf_adminq.c
@@ -17,18 +17,16 @@
STATIC void iavf_adminq_init_regs(struct iavf_hw *hw)
{
/* set head and tail registers in our local struct */
- if (iavf_is_vf(hw)) {
- hw->aq.asq.tail = IAVF_VF_ATQT1;
- hw->aq.asq.head = IAVF_VF_ATQH1;
- hw->aq.asq.len = IAVF_VF_ATQLEN1;
- hw->aq.asq.bal = IAVF_VF_ATQBAL1;
- hw->aq.asq.bah = IAVF_VF_ATQBAH1;
- hw->aq.arq.tail = IAVF_VF_ARQT1;
- hw->aq.arq.head = IAVF_VF_ARQH1;
- hw->aq.arq.len = IAVF_VF_ARQLEN1;
- hw->aq.arq.bal = IAVF_VF_ARQBAL1;
- hw->aq.arq.bah = IAVF_VF_ARQBAH1;
- }
+ hw->aq.asq.tail = IAVF_VF_ATQT1;
+ hw->aq.asq.head = IAVF_VF_ATQH1;
+ hw->aq.asq.len = IAVF_VF_ATQLEN1;
+ hw->aq.asq.bal = IAVF_VF_ATQBAL1;
+ hw->aq.asq.bah = IAVF_VF_ATQBAH1;
+ hw->aq.arq.tail = IAVF_VF_ARQT1;
+ hw->aq.arq.head = IAVF_VF_ARQH1;
+ hw->aq.arq.len = IAVF_VF_ARQLEN1;
+ hw->aq.arq.bal = IAVF_VF_ARQBAL1;
+ hw->aq.arq.bah = IAVF_VF_ARQBAH1;
}
/**
@@ -549,8 +547,6 @@ enum iavf_status iavf_init_adminq(struct iavf_hw *hw)
if (ret_code != IAVF_SUCCESS)
goto init_adminq_free_asq;
- ret_code = IAVF_SUCCESS;
-
/* success! */
goto init_adminq_exit;
@@ -580,9 +576,6 @@ enum iavf_status iavf_shutdown_adminq(struct iavf_hw *hw)
iavf_destroy_spinlock(&hw->aq.asq_spinlock);
iavf_destroy_spinlock(&hw->aq.arq_spinlock);
- if (hw->nvm_buff.va)
- iavf_free_virt_mem(hw, &hw->nvm_buff);
-
return ret_code;
}
diff --git a/drivers/net/iavf/base/iavf_adminq.h b/drivers/net/iavf/base/iavf_adminq.h
index 715621644..bdc5e0187 100644
--- a/drivers/net/iavf/base/iavf_adminq.h
+++ b/drivers/net/iavf/base/iavf_adminq.h
@@ -84,49 +84,6 @@ struct iavf_adminq_info {
enum iavf_admin_queue_err arq_last_status;
};
-/**
- * iavf_aq_rc_to_posix - convert errors to user-land codes
- * aq_ret: AdminQ handler error code can override aq_rc
- * aq_rc: AdminQ firmware error code to convert
- **/
-STATIC INLINE int iavf_aq_rc_to_posix(int aq_ret, int aq_rc)
-{
- int aq_to_posix[] = {
- 0, /* IAVF_AQ_RC_OK */
- -EPERM, /* IAVF_AQ_RC_EPERM */
- -ENOENT, /* IAVF_AQ_RC_ENOENT */
- -ESRCH, /* IAVF_AQ_RC_ESRCH */
- -EINTR, /* IAVF_AQ_RC_EINTR */
- -EIO, /* IAVF_AQ_RC_EIO */
- -ENXIO, /* IAVF_AQ_RC_ENXIO */
- -E2BIG, /* IAVF_AQ_RC_E2BIG */
- -EAGAIN, /* IAVF_AQ_RC_EAGAIN */
- -ENOMEM, /* IAVF_AQ_RC_ENOMEM */
- -EACCES, /* IAVF_AQ_RC_EACCES */
- -EFAULT, /* IAVF_AQ_RC_EFAULT */
- -EBUSY, /* IAVF_AQ_RC_EBUSY */
- -EEXIST, /* IAVF_AQ_RC_EEXIST */
- -EINVAL, /* IAVF_AQ_RC_EINVAL */
- -ENOTTY, /* IAVF_AQ_RC_ENOTTY */
- -ENOSPC, /* IAVF_AQ_RC_ENOSPC */
- -ENOSYS, /* IAVF_AQ_RC_ENOSYS */
- -ERANGE, /* IAVF_AQ_RC_ERANGE */
- -EPIPE, /* IAVF_AQ_RC_EFLUSHED */
- -ESPIPE, /* IAVF_AQ_RC_BAD_ADDR */
- -EROFS, /* IAVF_AQ_RC_EMODE */
- -EFBIG, /* IAVF_AQ_RC_EFBIG */
- };
-
- /* aq_rc is invalid if AQ timed out */
- if (aq_ret == IAVF_ERR_ADMIN_QUEUE_TIMEOUT)
- return -EAGAIN;
-
- if (!((u32)aq_rc < (sizeof(aq_to_posix) / sizeof((aq_to_posix)[0]))))
- return -ERANGE;
-
- return aq_to_posix[aq_rc];
-}
-
/* general information */
#define IAVF_AQ_LARGE_BUF 512
#define IAVF_ASQ_CMD_TIMEOUT 250000 /* usecs */
diff --git a/drivers/net/iavf/base/iavf_adminq_cmd.h b/drivers/net/iavf/base/iavf_adminq_cmd.h
index 45388c8b7..b0ee0b082 100644
--- a/drivers/net/iavf/base/iavf_adminq_cmd.h
+++ b/drivers/net/iavf/base/iavf_adminq_cmd.h
@@ -11,7 +11,6 @@
* This file needs to comply with the Linux Kernel coding style.
*/
-
#define IAVF_FW_API_VERSION_MAJOR 0x0001
#define IAVF_FW_API_VERSION_MINOR_X722 0x0005
#define IAVF_FW_API_VERSION_MINOR_X710 0x0007
@@ -317,33 +316,6 @@ enum iavf_admin_queue_opc {
*/
#define IAVF_CHECK_CMD_LENGTH(X) IAVF_CHECK_STRUCT_LEN(16, X)
-/* internal (0x00XX) commands */
-
-/* Get version (direct 0x0001) */
-struct iavf_aqc_get_version {
- __le32 rom_ver;
- __le32 fw_build;
- __le16 fw_major;
- __le16 fw_minor;
- __le16 api_major;
- __le16 api_minor;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_version);
-
-/* Send driver version (indirect 0x0002) */
-struct iavf_aqc_driver_version {
- u8 driver_major_ver;
- u8 driver_minor_ver;
- u8 driver_build_ver;
- u8 driver_subbuild_ver;
- u8 reserved[4];
- __le32 address_high;
- __le32 address_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_driver_version);
-
/* Queue Shutdown (direct 0x0003) */
struct iavf_aqc_queue_shutdown {
__le32 driver_unloading;
@@ -353,493 +325,9 @@ struct iavf_aqc_queue_shutdown {
IAVF_CHECK_CMD_LENGTH(iavf_aqc_queue_shutdown);
-/* Set PF context (0x0004, direct) */
-struct iavf_aqc_set_pf_context {
- u8 pf_id;
- u8 reserved[15];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_pf_context);
-
-/* Request resource ownership (direct 0x0008)
- * Release resource ownership (direct 0x0009)
- */
-#define IAVF_AQ_RESOURCE_NVM 1
-#define IAVF_AQ_RESOURCE_SDP 2
-#define IAVF_AQ_RESOURCE_ACCESS_READ 1
-#define IAVF_AQ_RESOURCE_ACCESS_WRITE 2
-#define IAVF_AQ_RESOURCE_NVM_READ_TIMEOUT 3000
-#define IAVF_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000
-
-struct iavf_aqc_request_resource {
- __le16 resource_id;
- __le16 access_type;
- __le32 timeout;
- __le32 resource_number;
- u8 reserved[4];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_request_resource);
-
-/* Get function capabilities (indirect 0x000A)
- * Get device capabilities (indirect 0x000B)
- */
-struct iavf_aqc_list_capabilites {
- u8 command_flags;
-#define IAVF_AQ_LIST_CAP_PF_INDEX_EN 1
- u8 pf_index;
- u8 reserved[2];
- __le32 count;
- __le32 addr_high;
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_list_capabilites);
-
-struct iavf_aqc_list_capabilities_element_resp {
- __le16 id;
- u8 major_rev;
- u8 minor_rev;
- __le32 number;
- __le32 logical_id;
- __le32 phys_id;
- u8 reserved[16];
-};
-
-/* list of caps */
-
-#define IAVF_AQ_CAP_ID_SWITCH_MODE 0x0001
-#define IAVF_AQ_CAP_ID_MNG_MODE 0x0002
-#define IAVF_AQ_CAP_ID_NPAR_ACTIVE 0x0003
-#define IAVF_AQ_CAP_ID_OS2BMC_CAP 0x0004
-#define IAVF_AQ_CAP_ID_FUNCTIONS_VALID 0x0005
-#define IAVF_AQ_CAP_ID_ALTERNATE_RAM 0x0006
-#define IAVF_AQ_CAP_ID_WOL_AND_PROXY 0x0008
-#define IAVF_AQ_CAP_ID_SRIOV 0x0012
-#define IAVF_AQ_CAP_ID_VF 0x0013
-#define IAVF_AQ_CAP_ID_VMDQ 0x0014
-#define IAVF_AQ_CAP_ID_8021QBG 0x0015
-#define IAVF_AQ_CAP_ID_8021QBR 0x0016
-#define IAVF_AQ_CAP_ID_VSI 0x0017
-#define IAVF_AQ_CAP_ID_DCB 0x0018
-#define IAVF_AQ_CAP_ID_FCOE 0x0021
-#define IAVF_AQ_CAP_ID_ISCSI 0x0022
-#define IAVF_AQ_CAP_ID_RSS 0x0040
-#define IAVF_AQ_CAP_ID_RXQ 0x0041
-#define IAVF_AQ_CAP_ID_TXQ 0x0042
-#define IAVF_AQ_CAP_ID_MSIX 0x0043
-#define IAVF_AQ_CAP_ID_VF_MSIX 0x0044
-#define IAVF_AQ_CAP_ID_FLOW_DIRECTOR 0x0045
-#define IAVF_AQ_CAP_ID_1588 0x0046
-#define IAVF_AQ_CAP_ID_IWARP 0x0051
-#define IAVF_AQ_CAP_ID_LED 0x0061
-#define IAVF_AQ_CAP_ID_SDP 0x0062
-#define IAVF_AQ_CAP_ID_MDIO 0x0063
-#define IAVF_AQ_CAP_ID_WSR_PROT 0x0064
-#define IAVF_AQ_CAP_ID_NVM_MGMT 0x0080
-#define IAVF_AQ_CAP_ID_FLEX10 0x00F1
-#define IAVF_AQ_CAP_ID_CEM 0x00F2
-
-/* Set CPPM Configuration (direct 0x0103) */
-struct iavf_aqc_cppm_configuration {
- __le16 command_flags;
-#define IAVF_AQ_CPPM_EN_LTRC 0x0800
-#define IAVF_AQ_CPPM_EN_DMCTH 0x1000
-#define IAVF_AQ_CPPM_EN_DMCTLX 0x2000
-#define IAVF_AQ_CPPM_EN_HPTC 0x4000
-#define IAVF_AQ_CPPM_EN_DMARC 0x8000
- __le16 ttlx;
- __le32 dmacr;
- __le16 dmcth;
- u8 hptc;
- u8 reserved;
- __le32 pfltrc;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_cppm_configuration);
-
-/* Set ARP Proxy command / response (indirect 0x0104) */
-struct iavf_aqc_arp_proxy_data {
- __le16 command_flags;
-#define IAVF_AQ_ARP_INIT_IPV4 0x0800
-#define IAVF_AQ_ARP_UNSUP_CTL 0x1000
-#define IAVF_AQ_ARP_ENA 0x2000
-#define IAVF_AQ_ARP_ADD_IPV4 0x4000
-#define IAVF_AQ_ARP_DEL_IPV4 0x8000
- __le16 table_id;
- __le32 enabled_offloads;
-#define IAVF_AQ_ARP_DIRECTED_OFFLOAD_ENABLE 0x00000020
-#define IAVF_AQ_ARP_OFFLOAD_ENABLE 0x00000800
- __le32 ip_addr;
- u8 mac_addr[6];
- u8 reserved[2];
-};
-
-IAVF_CHECK_STRUCT_LEN(0x14, iavf_aqc_arp_proxy_data);
-
-/* Set NS Proxy Table Entry Command (indirect 0x0105) */
-struct iavf_aqc_ns_proxy_data {
- __le16 table_idx_mac_addr_0;
- __le16 table_idx_mac_addr_1;
- __le16 table_idx_ipv6_0;
- __le16 table_idx_ipv6_1;
- __le16 control;
-#define IAVF_AQ_NS_PROXY_ADD_0 0x0001
-#define IAVF_AQ_NS_PROXY_DEL_0 0x0002
-#define IAVF_AQ_NS_PROXY_ADD_1 0x0004
-#define IAVF_AQ_NS_PROXY_DEL_1 0x0008
-#define IAVF_AQ_NS_PROXY_ADD_IPV6_0 0x0010
-#define IAVF_AQ_NS_PROXY_DEL_IPV6_0 0x0020
-#define IAVF_AQ_NS_PROXY_ADD_IPV6_1 0x0040
-#define IAVF_AQ_NS_PROXY_DEL_IPV6_1 0x0080
-#define IAVF_AQ_NS_PROXY_COMMAND_SEQ 0x0100
-#define IAVF_AQ_NS_PROXY_INIT_IPV6_TBL 0x0200
-#define IAVF_AQ_NS_PROXY_INIT_MAC_TBL 0x0400
-#define IAVF_AQ_NS_PROXY_OFFLOAD_ENABLE 0x0800
-#define IAVF_AQ_NS_PROXY_DIRECTED_OFFLOAD_ENABLE 0x1000
- u8 mac_addr_0[6];
- u8 mac_addr_1[6];
- u8 local_mac_addr[6];
- u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */
- u8 ipv6_addr_1[16];
-};
-
-IAVF_CHECK_STRUCT_LEN(0x3c, iavf_aqc_ns_proxy_data);
-
-/* Manage LAA Command (0x0106) - obsolete */
-struct iavf_aqc_mng_laa {
- __le16 command_flags;
-#define IAVF_AQ_LAA_FLAG_WR 0x8000
- u8 reserved[2];
- __le32 sal;
- __le16 sah;
- u8 reserved2[6];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_mng_laa);
-
-/* Manage MAC Address Read Command (indirect 0x0107) */
-struct iavf_aqc_mac_address_read {
- __le16 command_flags;
-#define IAVF_AQC_LAN_ADDR_VALID 0x10
-#define IAVF_AQC_SAN_ADDR_VALID 0x20
-#define IAVF_AQC_PORT_ADDR_VALID 0x40
-#define IAVF_AQC_WOL_ADDR_VALID 0x80
-#define IAVF_AQC_MC_MAG_EN_VALID 0x100
#define IAVF_AQC_WOL_PRESERVE_STATUS 0x200
-#define IAVF_AQC_ADDR_VALID_MASK 0x3F0
- u8 reserved[6];
- __le32 addr_high;
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_mac_address_read);
-
-struct iavf_aqc_mac_address_read_data {
- u8 pf_lan_mac[6];
- u8 pf_san_mac[6];
- u8 port_mac[6];
- u8 pf_wol_mac[6];
-};
-
-IAVF_CHECK_STRUCT_LEN(24, iavf_aqc_mac_address_read_data);
-
-/* Manage MAC Address Write Command (0x0108) */
-struct iavf_aqc_mac_address_write {
- __le16 command_flags;
#define IAVF_AQC_MC_MAG_EN 0x0100
#define IAVF_AQC_WOL_PRESERVE_ON_PFR 0x0200
-#define IAVF_AQC_WRITE_TYPE_LAA_ONLY 0x0000
-#define IAVF_AQC_WRITE_TYPE_LAA_WOL 0x4000
-#define IAVF_AQC_WRITE_TYPE_PORT 0x8000
-#define IAVF_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000
-#define IAVF_AQC_WRITE_TYPE_MASK 0xC000
-
- __le16 mac_sah;
- __le32 mac_sal;
- u8 reserved[8];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_mac_address_write);
-
-/* PXE commands (0x011x) */
-
-/* Clear PXE Command and response (direct 0x0110) */
-struct iavf_aqc_clear_pxe {
- u8 rx_cnt;
- u8 reserved[15];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_clear_pxe);
-
-/* Set WoL Filter (0x0120) */
-
-struct iavf_aqc_set_wol_filter {
- __le16 filter_index;
-#define IAVF_AQC_MAX_NUM_WOL_FILTERS 8
-#define IAVF_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT 15
-#define IAVF_AQC_SET_WOL_FILTER_TYPE_MAGIC_MASK (0x1 << \
- IAVF_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT)
-
-#define IAVF_AQC_SET_WOL_FILTER_INDEX_SHIFT 0
-#define IAVF_AQC_SET_WOL_FILTER_INDEX_MASK (0x7 << \
- IAVF_AQC_SET_WOL_FILTER_INDEX_SHIFT)
- __le16 cmd_flags;
-#define IAVF_AQC_SET_WOL_FILTER 0x8000
-#define IAVF_AQC_SET_WOL_FILTER_NO_TCO_WOL 0x4000
-#define IAVF_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR 0x2000
-#define IAVF_AQC_SET_WOL_FILTER_ACTION_CLEAR 0
-#define IAVF_AQC_SET_WOL_FILTER_ACTION_SET 1
- __le16 valid_flags;
-#define IAVF_AQC_SET_WOL_FILTER_ACTION_VALID 0x8000
-#define IAVF_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID 0x4000
- u8 reserved[2];
- __le32 address_high;
- __le32 address_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_wol_filter);
-
-struct iavf_aqc_set_wol_filter_data {
- u8 filter[128];
- u8 mask[16];
-};
-
-IAVF_CHECK_STRUCT_LEN(0x90, iavf_aqc_set_wol_filter_data);
-
-/* Get Wake Reason (0x0121) */
-
-struct iavf_aqc_get_wake_reason_completion {
- u8 reserved_1[2];
- __le16 wake_reason;
-#define IAVF_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT 0
-#define IAVF_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_MASK (0xFF << \
- IAVF_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT)
-#define IAVF_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT 8
-#define IAVF_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_MASK (0xFF << \
- IAVF_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT)
- u8 reserved_2[12];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_wake_reason_completion);
-
-/* Switch configuration commands (0x02xx) */
-
-/* Used by many indirect commands that only pass an seid and a buffer in the
- * command
- */
-struct iavf_aqc_switch_seid {
- __le16 seid;
- u8 reserved[6];
- __le32 addr_high;
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_switch_seid);
-
-/* Get Switch Configuration command (indirect 0x0200)
- * uses iavf_aqc_switch_seid for the descriptor
- */
-struct iavf_aqc_get_switch_config_header_resp {
- __le16 num_reported;
- __le16 num_total;
- u8 reserved[12];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_switch_config_header_resp);
-
-struct iavf_aqc_switch_config_element_resp {
- u8 element_type;
-#define IAVF_AQ_SW_ELEM_TYPE_MAC 1
-#define IAVF_AQ_SW_ELEM_TYPE_PF 2
-#define IAVF_AQ_SW_ELEM_TYPE_VF 3
-#define IAVF_AQ_SW_ELEM_TYPE_EMP 4
-#define IAVF_AQ_SW_ELEM_TYPE_BMC 5
-#define IAVF_AQ_SW_ELEM_TYPE_PV 16
-#define IAVF_AQ_SW_ELEM_TYPE_VEB 17
-#define IAVF_AQ_SW_ELEM_TYPE_PA 18
-#define IAVF_AQ_SW_ELEM_TYPE_VSI 19
- u8 revision;
-#define IAVF_AQ_SW_ELEM_REV_1 1
- __le16 seid;
- __le16 uplink_seid;
- __le16 downlink_seid;
- u8 reserved[3];
- u8 connection_type;
-#define IAVF_AQ_CONN_TYPE_REGULAR 0x1
-#define IAVF_AQ_CONN_TYPE_DEFAULT 0x2
-#define IAVF_AQ_CONN_TYPE_CASCADED 0x3
- __le16 scheduler_id;
- __le16 element_info;
-};
-
-IAVF_CHECK_STRUCT_LEN(0x10, iavf_aqc_switch_config_element_resp);
-
-/* Get Switch Configuration (indirect 0x0200)
- * an array of elements are returned in the response buffer
- * the first in the array is the header, remainder are elements
- */
-struct iavf_aqc_get_switch_config_resp {
- struct iavf_aqc_get_switch_config_header_resp header;
- struct iavf_aqc_switch_config_element_resp element[1];
-};
-
-IAVF_CHECK_STRUCT_LEN(0x20, iavf_aqc_get_switch_config_resp);
-
-/* Add Statistics (direct 0x0201)
- * Remove Statistics (direct 0x0202)
- */
-struct iavf_aqc_add_remove_statistics {
- __le16 seid;
- __le16 vlan;
- __le16 stat_index;
- u8 reserved[10];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_remove_statistics);
-
-/* Set Port Parameters command (direct 0x0203) */
-struct iavf_aqc_set_port_parameters {
- __le16 command_flags;
-#define IAVF_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1
-#define IAVF_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */
-#define IAVF_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4
- __le16 bad_frame_vsi;
-#define IAVF_AQ_SET_P_PARAMS_BFRAME_SEID_SHIFT 0x0
-#define IAVF_AQ_SET_P_PARAMS_BFRAME_SEID_MASK 0x3FF
- __le16 default_seid; /* reserved for command */
- u8 reserved[10];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_port_parameters);
-
-/* Get Switch Resource Allocation (indirect 0x0204) */
-struct iavf_aqc_get_switch_resource_alloc {
- u8 num_entries; /* reserved for command */
- u8 reserved[7];
- __le32 addr_high;
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_switch_resource_alloc);
-
-/* expect an array of these structs in the response buffer */
-struct iavf_aqc_switch_resource_alloc_element_resp {
- u8 resource_type;
-#define IAVF_AQ_RESOURCE_TYPE_VEB 0x0
-#define IAVF_AQ_RESOURCE_TYPE_VSI 0x1
-#define IAVF_AQ_RESOURCE_TYPE_MACADDR 0x2
-#define IAVF_AQ_RESOURCE_TYPE_STAG 0x3
-#define IAVF_AQ_RESOURCE_TYPE_ETAG 0x4
-#define IAVF_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5
-#define IAVF_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6
-#define IAVF_AQ_RESOURCE_TYPE_VLAN 0x7
-#define IAVF_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8
-#define IAVF_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9
-#define IAVF_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA
-#define IAVF_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB
-#define IAVF_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC
-#define IAVF_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD
-#define IAVF_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF
-#define IAVF_AQ_RESOURCE_TYPE_IP_FILTERS 0x10
-#define IAVF_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11
-#define IAVF_AQ_RESOURCE_TYPE_VN2_KEYS 0x12
-#define IAVF_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13
- u8 reserved1;
- __le16 guaranteed;
- __le16 total;
- __le16 used;
- __le16 total_unalloced;
- u8 reserved2[6];
-};
-
-IAVF_CHECK_STRUCT_LEN(0x10, iavf_aqc_switch_resource_alloc_element_resp);
-
-/* Set Switch Configuration (direct 0x0205) */
-struct iavf_aqc_set_switch_config {
- __le16 flags;
-/* flags used for both fields below */
-#define IAVF_AQ_SET_SWITCH_CFG_PROMISC 0x0001
-#define IAVF_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002
-#define IAVF_AQ_SET_SWITCH_CFG_HW_ATR_EVICT 0x0004
- __le16 valid_flags;
- /* The ethertype in switch_tag is dropped on ingress and used
- * internally by the switch. Set this to zero for the default
- * of 0x88a8 (802.1ad). Should be zero for firmware API
- * versions lower than 1.7.
- */
- __le16 switch_tag;
- /* The ethertypes in first_tag and second_tag are used to
- * match the outer and inner VLAN tags (respectively) when HW
- * double VLAN tagging is enabled via the set port parameters
- * AQ command. Otherwise these are both ignored. Set them to
- * zero for their defaults of 0x8100 (802.1Q). Should be zero
- * for firmware API versions lower than 1.7.
- */
- __le16 first_tag;
- __le16 second_tag;
- u8 reserved[6];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_switch_config);
-
-/* Read Receive control registers (direct 0x0206)
- * Write Receive control registers (direct 0x0207)
- * used for accessing Rx control registers that can be
- * slow and need special handling when under high Rx load
- */
-struct iavf_aqc_rx_ctl_reg_read_write {
- __le32 reserved1;
- __le32 address;
- __le32 reserved2;
- __le32 value;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_rx_ctl_reg_read_write);
-
-/* Add VSI (indirect 0x0210)
- * this indirect command uses struct iavf_aqc_vsi_properties_data
- * as the indirect buffer (128 bytes)
- *
- * Update VSI (indirect 0x211)
- * uses the same data structure as Add VSI
- *
- * Get VSI (indirect 0x0212)
- * uses the same completion and data structure as Add VSI
- */
-struct iavf_aqc_add_get_update_vsi {
- __le16 uplink_seid;
- u8 connection_type;
-#define IAVF_AQ_VSI_CONN_TYPE_NORMAL 0x1
-#define IAVF_AQ_VSI_CONN_TYPE_DEFAULT 0x2
-#define IAVF_AQ_VSI_CONN_TYPE_CASCADED 0x3
- u8 reserved1;
- u8 vf_id;
- u8 reserved2;
- __le16 vsi_flags;
-#define IAVF_AQ_VSI_TYPE_SHIFT 0x0
-#define IAVF_AQ_VSI_TYPE_MASK (0x3 << IAVF_AQ_VSI_TYPE_SHIFT)
-#define IAVF_AQ_VSI_TYPE_VF 0x0
-#define IAVF_AQ_VSI_TYPE_VMDQ2 0x1
-#define IAVF_AQ_VSI_TYPE_PF 0x2
-#define IAVF_AQ_VSI_TYPE_EMP_MNG 0x3
-#define IAVF_AQ_VSI_FLAG_CASCADED_PV 0x4
- __le32 addr_high;
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_get_update_vsi);
-
-struct iavf_aqc_add_get_update_vsi_completion {
- __le16 seid;
- __le16 vsi_number;
- __le16 vsi_used;
- __le16 vsi_free;
- __le32 addr_high;
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_get_update_vsi_completion);
struct iavf_aqc_vsi_properties_data {
/* first 96 byte are written by SW */
@@ -966,87 +454,6 @@ struct iavf_aqc_vsi_properties_data {
IAVF_CHECK_STRUCT_LEN(128, iavf_aqc_vsi_properties_data);
-/* Add Port Virtualizer (direct 0x0220)
- * also used for update PV (direct 0x0221) but only flags are used
- * (IS_CTRL_PORT only works on add PV)
- */
-struct iavf_aqc_add_update_pv {
- __le16 command_flags;
-#define IAVF_AQC_PV_FLAG_PV_TYPE 0x1
-#define IAVF_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2
-#define IAVF_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4
-#define IAVF_AQC_PV_FLAG_IS_CTRL_PORT 0x8
- __le16 uplink_seid;
- __le16 connected_seid;
- u8 reserved[10];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_update_pv);
-
-struct iavf_aqc_add_update_pv_completion {
- /* reserved for update; for add also encodes error if rc == ENOSPC */
- __le16 pv_seid;
-#define IAVF_AQC_PV_ERR_FLAG_NO_PV 0x1
-#define IAVF_AQC_PV_ERR_FLAG_NO_SCHED 0x2
-#define IAVF_AQC_PV_ERR_FLAG_NO_COUNTER 0x4
-#define IAVF_AQC_PV_ERR_FLAG_NO_ENTRY 0x8
- u8 reserved[14];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_update_pv_completion);
-
-/* Get PV Params (direct 0x0222)
- * uses iavf_aqc_switch_seid for the descriptor
- */
-
-struct iavf_aqc_get_pv_params_completion {
- __le16 seid;
- __le16 default_stag;
- __le16 pv_flags; /* same flags as add_pv */
-#define IAVF_AQC_GET_PV_PV_TYPE 0x1
-#define IAVF_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2
-#define IAVF_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4
- u8 reserved[8];
- __le16 default_port_seid;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_pv_params_completion);
-
-/* Add VEB (direct 0x0230) */
-struct iavf_aqc_add_veb {
- __le16 uplink_seid;
- __le16 downlink_seid;
- __le16 veb_flags;
-#define IAVF_AQC_ADD_VEB_FLOATING 0x1
-#define IAVF_AQC_ADD_VEB_PORT_TYPE_SHIFT 1
-#define IAVF_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \
- IAVF_AQC_ADD_VEB_PORT_TYPE_SHIFT)
-#define IAVF_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2
-#define IAVF_AQC_ADD_VEB_PORT_TYPE_DATA 0x4
-#define IAVF_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */
-#define IAVF_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10
- u8 enable_tcs;
- u8 reserved[9];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_veb);
-
-struct iavf_aqc_add_veb_completion {
- u8 reserved[6];
- __le16 switch_seid;
- /* also encodes error if rc == ENOSPC; codes are the same as add_pv */
- __le16 veb_seid;
-#define IAVF_AQC_VEB_ERR_FLAG_NO_VEB 0x1
-#define IAVF_AQC_VEB_ERR_FLAG_NO_SCHED 0x2
-#define IAVF_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4
-#define IAVF_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8
- __le16 statistic_index;
- __le16 vebs_used;
- __le16 vebs_free;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_veb_completion);
-
/* Get VEB Parameters (direct 0x0232)
* uses iavf_aqc_switch_seid for the descriptor
*/
@@ -1062,1486 +469,116 @@ struct iavf_aqc_get_veb_parameters_completion {
IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_veb_parameters_completion);
-/* Delete Element (direct 0x0243)
- * uses the generic iavf_aqc_switch_seid
- */
-
-/* Add MAC-VLAN (indirect 0x0250) */
-
-/* used for the command for most vlan commands */
-struct iavf_aqc_macvlan {
- __le16 num_addresses;
- __le16 seid[3];
-#define IAVF_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0
-#define IAVF_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \
- IAVF_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
-#define IAVF_AQC_MACVLAN_CMD_SEID_VALID 0x8000
- __le32 addr_high;
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_macvlan);
-
-/* indirect data for command and response */
-struct iavf_aqc_add_macvlan_element_data {
- u8 mac_addr[6];
- __le16 vlan_tag;
- __le16 flags;
-#define IAVF_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001
-#define IAVF_AQC_MACVLAN_ADD_HASH_MATCH 0x0002
-#define IAVF_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004
-#define IAVF_AQC_MACVLAN_ADD_TO_QUEUE 0x0008
-#define IAVF_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010
- __le16 queue_number;
-#define IAVF_AQC_MACVLAN_CMD_QUEUE_SHIFT 0
-#define IAVF_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \
- IAVF_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
- /* response section */
- u8 match_method;
-#define IAVF_AQC_MM_PERFECT_MATCH 0x01
-#define IAVF_AQC_MM_HASH_MATCH 0x02
-#define IAVF_AQC_MM_ERR_NO_RES 0xFF
- u8 reserved1[3];
-};
+#define IAVF_LINK_SPEED_100MB_SHIFT 0x1
+#define IAVF_LINK_SPEED_1000MB_SHIFT 0x2
+#define IAVF_LINK_SPEED_10GB_SHIFT 0x3
+#define IAVF_LINK_SPEED_40GB_SHIFT 0x4
+#define IAVF_LINK_SPEED_20GB_SHIFT 0x5
+#define IAVF_LINK_SPEED_25GB_SHIFT 0x6
-struct iavf_aqc_add_remove_macvlan_completion {
- __le16 perfect_mac_used;
- __le16 perfect_mac_free;
- __le16 unicast_hash_free;
- __le16 multicast_hash_free;
- __le32 addr_high;
- __le32 addr_low;
+enum iavf_aq_link_speed {
+ IAVF_LINK_SPEED_UNKNOWN = 0,
+ IAVF_LINK_SPEED_100MB = (1 << IAVF_LINK_SPEED_100MB_SHIFT),
+ IAVF_LINK_SPEED_1GB = (1 << IAVF_LINK_SPEED_1000MB_SHIFT),
+ IAVF_LINK_SPEED_10GB = (1 << IAVF_LINK_SPEED_10GB_SHIFT),
+ IAVF_LINK_SPEED_40GB = (1 << IAVF_LINK_SPEED_40GB_SHIFT),
+ IAVF_LINK_SPEED_20GB = (1 << IAVF_LINK_SPEED_20GB_SHIFT),
+ IAVF_LINK_SPEED_25GB = (1 << IAVF_LINK_SPEED_25GB_SHIFT),
};
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_remove_macvlan_completion);
-
-/* Remove MAC-VLAN (indirect 0x0251)
- * uses iavf_aqc_macvlan for the descriptor
- * data points to an array of num_addresses of elements
- */
-
-struct iavf_aqc_remove_macvlan_element_data {
- u8 mac_addr[6];
- __le16 vlan_tag;
- u8 flags;
-#define IAVF_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01
-#define IAVF_AQC_MACVLAN_DEL_HASH_MATCH 0x02
-#define IAVF_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08
-#define IAVF_AQC_MACVLAN_DEL_ALL_VSIS 0x10
- u8 reserved[3];
- /* reply section */
- u8 error_code;
-#define IAVF_AQC_REMOVE_MACVLAN_SUCCESS 0x0
-#define IAVF_AQC_REMOVE_MACVLAN_FAIL 0xFF
- u8 reply_reserved[3];
-};
+#define IAVF_AQ_LINK_UP_FUNCTION 0x01
-/* Add VLAN (indirect 0x0252)
- * Remove VLAN (indirect 0x0253)
- * use the generic iavf_aqc_macvlan for the command
+/* Send to PF command (indirect 0x0801) id is only used by PF
+ * Send to VF command (indirect 0x0802) id is only used by PF
+ * Send to Peer PF command (indirect 0x0803)
*/
-struct iavf_aqc_add_remove_vlan_element_data {
- __le16 vlan_tag;
- u8 vlan_flags;
-/* flags for add VLAN */
-#define IAVF_AQC_ADD_VLAN_LOCAL 0x1
-#define IAVF_AQC_ADD_PVLAN_TYPE_SHIFT 1
-#define IAVF_AQC_ADD_PVLAN_TYPE_MASK (0x3 << IAVF_AQC_ADD_PVLAN_TYPE_SHIFT)
-#define IAVF_AQC_ADD_PVLAN_TYPE_REGULAR 0x0
-#define IAVF_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2
-#define IAVF_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4
-#define IAVF_AQC_VLAN_PTYPE_SHIFT 3
-#define IAVF_AQC_VLAN_PTYPE_MASK (0x3 << IAVF_AQC_VLAN_PTYPE_SHIFT)
-#define IAVF_AQC_VLAN_PTYPE_REGULAR_VSI 0x0
-#define IAVF_AQC_VLAN_PTYPE_PROMISC_VSI 0x8
-#define IAVF_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10
-#define IAVF_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18
-/* flags for remove VLAN */
-#define IAVF_AQC_REMOVE_VLAN_ALL 0x1
- u8 reserved;
- u8 result;
-/* flags for add VLAN */
-#define IAVF_AQC_ADD_VLAN_SUCCESS 0x0
-#define IAVF_AQC_ADD_VLAN_FAIL_REQUEST 0xFE
-#define IAVF_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF
-/* flags for remove VLAN */
-#define IAVF_AQC_REMOVE_VLAN_SUCCESS 0x0
-#define IAVF_AQC_REMOVE_VLAN_FAIL 0xFF
- u8 reserved1[3];
-};
-
-struct iavf_aqc_add_remove_vlan_completion {
+struct iavf_aqc_pf_vf_message {
+ __le32 id;
u8 reserved[4];
- __le16 vlans_used;
- __le16 vlans_free;
__le32 addr_high;
__le32 addr_low;
};
-/* Set VSI Promiscuous Modes (direct 0x0254) */
-struct iavf_aqc_set_vsi_promiscuous_modes {
- __le16 promiscuous_flags;
- __le16 valid_flags;
-/* flags used for both fields above */
-#define IAVF_AQC_SET_VSI_PROMISC_UNICAST 0x01
-#define IAVF_AQC_SET_VSI_PROMISC_MULTICAST 0x02
-#define IAVF_AQC_SET_VSI_PROMISC_BROADCAST 0x04
-#define IAVF_AQC_SET_VSI_DEFAULT 0x08
-#define IAVF_AQC_SET_VSI_PROMISC_VLAN 0x10
-#define IAVF_AQC_SET_VSI_PROMISC_TX 0x8000
- __le16 seid;
-#define IAVF_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF
- __le16 vlan_tag;
-#define IAVF_AQC_SET_VSI_VLAN_MASK 0x0FFF
-#define IAVF_AQC_SET_VSI_VLAN_VALID 0x8000
- u8 reserved[8];
-};
+IAVF_CHECK_CMD_LENGTH(iavf_aqc_pf_vf_message);
+
+/* Get CEE DCBX Oper Config (0x0A07)
+ * uses the generic descriptor struct
+ * returns below as indirect response
+ */
+
+#define IAVF_AQC_CEE_APP_FCOE_SHIFT 0x0
+#define IAVF_AQC_CEE_APP_FCOE_MASK (0x7 << IAVF_AQC_CEE_APP_FCOE_SHIFT)
+#define IAVF_AQC_CEE_APP_ISCSI_SHIFT 0x3
+#define IAVF_AQC_CEE_APP_ISCSI_MASK (0x7 << IAVF_AQC_CEE_APP_ISCSI_SHIFT)
+#define IAVF_AQC_CEE_APP_FIP_SHIFT 0x8
+#define IAVF_AQC_CEE_APP_FIP_MASK (0x7 << IAVF_AQC_CEE_APP_FIP_SHIFT)
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_vsi_promiscuous_modes);
+#define IAVF_AQC_CEE_PG_STATUS_SHIFT 0x0
+#define IAVF_AQC_CEE_PG_STATUS_MASK (0x7 << IAVF_AQC_CEE_PG_STATUS_SHIFT)
+#define IAVF_AQC_CEE_PFC_STATUS_SHIFT 0x3
+#define IAVF_AQC_CEE_PFC_STATUS_MASK (0x7 << IAVF_AQC_CEE_PFC_STATUS_SHIFT)
+#define IAVF_AQC_CEE_APP_STATUS_SHIFT 0x8
+#define IAVF_AQC_CEE_APP_STATUS_MASK (0x7 << IAVF_AQC_CEE_APP_STATUS_SHIFT)
+#define IAVF_AQC_CEE_FCOE_STATUS_SHIFT 0x8
+#define IAVF_AQC_CEE_FCOE_STATUS_MASK (0x7 << IAVF_AQC_CEE_FCOE_STATUS_SHIFT)
+#define IAVF_AQC_CEE_ISCSI_STATUS_SHIFT 0xB
+#define IAVF_AQC_CEE_ISCSI_STATUS_MASK (0x7 << IAVF_AQC_CEE_ISCSI_STATUS_SHIFT)
+#define IAVF_AQC_CEE_FIP_STATUS_SHIFT 0x10
+#define IAVF_AQC_CEE_FIP_STATUS_MASK (0x7 << IAVF_AQC_CEE_FIP_STATUS_SHIFT)
-/* Add S/E-tag command (direct 0x0255)
- * Uses generic iavf_aqc_add_remove_tag_completion for completion
+/* struct iavf_aqc_get_cee_dcb_cfg_v1_resp was originally defined with
+ * word boundary layout issues, which the Linux compilers silently deal
+ * with by adding padding, making the actual struct larger than designed.
+ * However, the FW compiler for the NIC is less lenient and complains
+ * about the struct. Hence, the struct defined here has an extra byte in
+ * fields reserved3 and reserved4 to directly acknowledge that padding,
+ * and the new length is used in the length check macro.
*/
-struct iavf_aqc_add_tag {
- __le16 flags;
-#define IAVF_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001
- __le16 seid;
-#define IAVF_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0
-#define IAVF_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \
- IAVF_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT)
- __le16 tag;
- __le16 queue_number;
- u8 reserved[8];
+struct iavf_aqc_get_cee_dcb_cfg_v1_resp {
+ u8 reserved1;
+ u8 oper_num_tc;
+ u8 oper_prio_tc[4];
+ u8 reserved2;
+ u8 oper_tc_bw[8];
+ u8 oper_pfc_en;
+ u8 reserved3[2];
+ __le16 oper_app_prio;
+ u8 reserved4[2];
+ __le16 tlv_status;
};
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_tag);
+IAVF_CHECK_STRUCT_LEN(0x18, iavf_aqc_get_cee_dcb_cfg_v1_resp);
-struct iavf_aqc_add_remove_tag_completion {
+struct iavf_aqc_get_cee_dcb_cfg_resp {
+ u8 oper_num_tc;
+ u8 oper_prio_tc[4];
+ u8 oper_tc_bw[8];
+ u8 oper_pfc_en;
+ __le16 oper_app_prio;
+ __le32 tlv_status;
u8 reserved[12];
- __le16 tags_used;
- __le16 tags_free;
};
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_remove_tag_completion);
+IAVF_CHECK_STRUCT_LEN(0x20, iavf_aqc_get_cee_dcb_cfg_resp);
-/* Remove S/E-tag command (direct 0x0256)
- * Uses generic iavf_aqc_add_remove_tag_completion for completion
+/* Set Local LLDP MIB (indirect 0x0A08)
+ * Used to replace the local MIB of a given LLDP agent. e.g. DCBx
*/
-struct iavf_aqc_remove_tag {
- __le16 seid;
-#define IAVF_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0
-#define IAVF_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
- IAVF_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT)
- __le16 tag;
- u8 reserved[12];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_remove_tag);
-
-/* Add multicast E-Tag (direct 0x0257)
- * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
- * and no external data
- */
-struct iavf_aqc_add_remove_mcast_etag {
- __le16 pv_seid;
- __le16 etag;
- u8 num_unicast_etags;
- u8 reserved[3];
- __le32 addr_high; /* address of array of 2-byte s-tags */
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_remove_mcast_etag);
-
-struct iavf_aqc_add_remove_mcast_etag_completion {
- u8 reserved[4];
- __le16 mcast_etags_used;
- __le16 mcast_etags_free;
- __le32 addr_high;
- __le32 addr_low;
-
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_remove_mcast_etag_completion);
-
-/* Update S/E-Tag (direct 0x0259) */
-struct iavf_aqc_update_tag {
- __le16 seid;
-#define IAVF_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0
-#define IAVF_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
- IAVF_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT)
- __le16 old_tag;
- __le16 new_tag;
- u8 reserved[10];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_update_tag);
-
-struct iavf_aqc_update_tag_completion {
- u8 reserved[12];
- __le16 tags_used;
- __le16 tags_free;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_update_tag_completion);
-
-/* Add Control Packet filter (direct 0x025A)
- * Remove Control Packet filter (direct 0x025B)
- * uses the iavf_aqc_add_oveb_cloud,
- * and the generic direct completion structure
- */
-struct iavf_aqc_add_remove_control_packet_filter {
- u8 mac[6];
- __le16 etype;
- __le16 flags;
-#define IAVF_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001
-#define IAVF_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002
-#define IAVF_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004
-#define IAVF_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008
-#define IAVF_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000
- __le16 seid;
-#define IAVF_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0
-#define IAVF_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \
- IAVF_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT)
- __le16 queue;
- u8 reserved[2];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_remove_control_packet_filter);
-
-struct iavf_aqc_add_remove_control_packet_filter_completion {
- __le16 mac_etype_used;
- __le16 etype_used;
- __le16 mac_etype_free;
- __le16 etype_free;
- u8 reserved[8];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_remove_control_packet_filter_completion);
-
-/* Add Cloud filters (indirect 0x025C)
- * Remove Cloud filters (indirect 0x025D)
- * uses the iavf_aqc_add_remove_cloud_filters,
- * and the generic indirect completion structure
- */
-struct iavf_aqc_add_remove_cloud_filters {
- u8 num_filters;
- u8 reserved;
- __le16 seid;
-#define IAVF_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0
-#define IAVF_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \
- IAVF_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)
- u8 big_buffer_flag;
-#define IAVF_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER 1
- u8 reserved2[3];
- __le32 addr_high;
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_remove_cloud_filters);
-
-struct iavf_aqc_add_remove_cloud_filters_element_data {
- u8 outer_mac[6];
- u8 inner_mac[6];
- __le16 inner_vlan;
- union {
- struct {
- u8 reserved[12];
- u8 data[4];
- } v4;
- struct {
- u8 data[16];
- } v6;
- } ipaddr;
- __le16 flags;
-#define IAVF_AQC_ADD_CLOUD_FILTER_SHIFT 0
-#define IAVF_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \
- IAVF_AQC_ADD_CLOUD_FILTER_SHIFT)
-/* 0x0000 reserved */
-#define IAVF_AQC_ADD_CLOUD_FILTER_OIP 0x0001
-/* 0x0002 reserved */
-#define IAVF_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003
-#define IAVF_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004
-/* 0x0005 reserved */
-#define IAVF_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006
-/* 0x0007 reserved */
-/* 0x0008 reserved */
-#define IAVF_AQC_ADD_CLOUD_FILTER_OMAC 0x0009
-#define IAVF_AQC_ADD_CLOUD_FILTER_IMAC 0x000A
-#define IAVF_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B
-#define IAVF_AQC_ADD_CLOUD_FILTER_IIP 0x000C
-/* 0x0010 to 0x0017 is for custom filters */
-
-#define IAVF_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080
-#define IAVF_AQC_ADD_CLOUD_VNK_SHIFT 6
-#define IAVF_AQC_ADD_CLOUD_VNK_MASK 0x00C0
-#define IAVF_AQC_ADD_CLOUD_FLAGS_IPV4 0
-#define IAVF_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100
-
-#define IAVF_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9
-#define IAVF_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00
-#define IAVF_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0
-#define IAVF_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1
-#define IAVF_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2
-#define IAVF_AQC_ADD_CLOUD_TNL_TYPE_IP 3
-#define IAVF_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4
-#define IAVF_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5
-
-#define IAVF_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000
-#define IAVF_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000
-#define IAVF_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000
-
- __le32 tenant_id;
- u8 reserved[4];
- __le16 queue_number;
-#define IAVF_AQC_ADD_CLOUD_QUEUE_SHIFT 0
-#define IAVF_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \
- IAVF_AQC_ADD_CLOUD_QUEUE_SHIFT)
- u8 reserved2[14];
- /* response section */
- u8 allocation_result;
-#define IAVF_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0
-#define IAVF_AQC_ADD_CLOUD_FILTER_FAIL 0xFF
- u8 response_reserved[7];
-};
-
-/* iavf_aqc_add_rm_cloud_filt_elem_ext is used when
- * IAVF_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER flag is set.
- */
-struct iavf_aqc_add_rm_cloud_filt_elem_ext {
- struct iavf_aqc_add_remove_cloud_filters_element_data element;
- u16 general_fields[32];
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0 0
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1 1
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2 2
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0 3
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1 4
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2 5
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0 6
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1 7
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2 8
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0 9
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1 10
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2 11
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X14_WORD0 12
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X14_WORD1 13
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X14_WORD2 14
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X16_WORD0 15
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X16_WORD1 16
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X16_WORD2 17
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X16_WORD3 18
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X16_WORD4 19
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X16_WORD5 20
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X16_WORD6 21
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X16_WORD7 22
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X17_WORD0 23
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X17_WORD1 24
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X17_WORD2 25
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X17_WORD3 26
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X17_WORD4 27
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X17_WORD5 28
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X17_WORD6 29
-#define IAVF_AQC_ADD_CLOUD_FV_FLU_0X17_WORD7 30
-};
-
-struct iavf_aqc_remove_cloud_filters_completion {
- __le16 perfect_ovlan_used;
- __le16 perfect_ovlan_free;
- __le16 vlan_used;
- __le16 vlan_free;
- __le32 addr_high;
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_remove_cloud_filters_completion);
-
-/* Replace filter Command 0x025F
- * uses the iavf_aqc_replace_cloud_filters,
- * and the generic indirect completion structure
- */
-struct iavf_filter_data {
- u8 filter_type;
- u8 input[3];
-};
-
-struct iavf_aqc_replace_cloud_filters_cmd {
- u8 valid_flags;
-#define IAVF_AQC_REPLACE_L1_FILTER 0x0
-#define IAVF_AQC_REPLACE_CLOUD_FILTER 0x1
-#define IAVF_AQC_GET_CLOUD_FILTERS 0x2
-#define IAVF_AQC_MIRROR_CLOUD_FILTER 0x4
-#define IAVF_AQC_HIGH_PRIORITY_CLOUD_FILTER 0x8
- u8 old_filter_type;
- u8 new_filter_type;
- u8 tr_bit;
- u8 reserved[4];
- __le32 addr_high;
- __le32 addr_low;
-};
-
-struct iavf_aqc_replace_cloud_filters_cmd_buf {
- u8 data[32];
-/* Filter type INPUT codes*/
-#define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_ENTRIES_MAX 3
-#define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED (1 << 7UL)
-
-/* Field Vector offsets */
-#define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_MAC_DA 0
-#define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_ETH 6
-#define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG 7
-#define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN 8
-#define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_OVLAN 9
-#define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN 10
-#define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY 11
-#define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC 12
-/* big FLU */
-#define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IP_DA 14
-/* big FLU */
-#define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_OIP_DA 15
-
-#define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN 37
- struct iavf_filter_data filters[8];
-};
-
-/* Add Mirror Rule (indirect or direct 0x0260)
- * Delete Mirror Rule (indirect or direct 0x0261)
- * note: some rule types (4,5) do not use an external buffer.
- * take care to set the flags correctly.
- */
-struct iavf_aqc_add_delete_mirror_rule {
- __le16 seid;
- __le16 rule_type;
-#define IAVF_AQC_MIRROR_RULE_TYPE_SHIFT 0
-#define IAVF_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \
- IAVF_AQC_MIRROR_RULE_TYPE_SHIFT)
-#define IAVF_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1
-#define IAVF_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2
-#define IAVF_AQC_MIRROR_RULE_TYPE_VLAN 3
-#define IAVF_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4
-#define IAVF_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5
- __le16 num_entries;
- __le16 destination; /* VSI for add, rule id for delete */
- __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_delete_mirror_rule);
-
-struct iavf_aqc_add_delete_mirror_rule_completion {
- u8 reserved[2];
- __le16 rule_id; /* only used on add */
- __le16 mirror_rules_used;
- __le16 mirror_rules_free;
- __le32 addr_high;
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_delete_mirror_rule_completion);
-
-/* Dynamic Device Personalization */
-struct iavf_aqc_write_personalization_profile {
- u8 flags;
- u8 reserved[3];
- __le32 profile_track_id;
- __le32 addr_high;
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_write_personalization_profile);
-
-struct iavf_aqc_write_ddp_resp {
- __le32 error_offset;
- __le32 error_info;
- __le32 addr_high;
- __le32 addr_low;
-};
-
-struct iavf_aqc_get_applied_profiles {
- u8 flags;
-#define IAVF_AQC_GET_DDP_GET_CONF 0x1
-#define IAVF_AQC_GET_DDP_GET_RDPU_CONF 0x2
- u8 rsv[3];
- __le32 reserved;
- __le32 addr_high;
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_applied_profiles);
-
-/* DCB 0x03xx*/
-
-/* PFC Ignore (direct 0x0301)
- * the command and response use the same descriptor structure
- */
-struct iavf_aqc_pfc_ignore {
- u8 tc_bitmap;
- u8 command_flags; /* unused on response */
-#define IAVF_AQC_PFC_IGNORE_SET 0x80
-#define IAVF_AQC_PFC_IGNORE_CLEAR 0x0
- u8 reserved[14];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_pfc_ignore);
-
-/* DCB Update (direct 0x0302) uses the iavf_aq_desc structure
- * with no parameters
- */
-
-/* TX scheduler 0x04xx */
-
-/* Almost all the indirect commands use
- * this generic struct to pass the SEID in param0
- */
-struct iavf_aqc_tx_sched_ind {
- __le16 vsi_seid;
- u8 reserved[6];
- __le32 addr_high;
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_tx_sched_ind);
-
-/* Several commands respond with a set of queue set handles */
-struct iavf_aqc_qs_handles_resp {
- __le16 qs_handles[8];
-};
-
-/* Configure VSI BW limits (direct 0x0400) */
-struct iavf_aqc_configure_vsi_bw_limit {
- __le16 vsi_seid;
- u8 reserved[2];
- __le16 credit;
- u8 reserved1[2];
- u8 max_credit; /* 0-3, limit = 2^max */
- u8 reserved2[7];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_configure_vsi_bw_limit);
-
-/* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
- * responds with iavf_aqc_qs_handles_resp
- */
-struct iavf_aqc_configure_vsi_ets_sla_bw_data {
- u8 tc_valid_bits;
- u8 reserved[15];
- __le16 tc_bw_credits[8]; /* FW writesback QS handles here */
-
- /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
- __le16 tc_bw_max[2];
- u8 reserved1[28];
-};
-
-IAVF_CHECK_STRUCT_LEN(0x40, iavf_aqc_configure_vsi_ets_sla_bw_data);
-
-/* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
- * responds with iavf_aqc_qs_handles_resp
- */
-struct iavf_aqc_configure_vsi_tc_bw_data {
- u8 tc_valid_bits;
- u8 reserved[3];
- u8 tc_bw_credits[8];
- u8 reserved1[4];
- __le16 qs_handles[8];
-};
-
-IAVF_CHECK_STRUCT_LEN(0x20, iavf_aqc_configure_vsi_tc_bw_data);
-
-/* Query vsi bw configuration (indirect 0x0408) */
-struct iavf_aqc_query_vsi_bw_config_resp {
- u8 tc_valid_bits;
- u8 tc_suspended_bits;
- u8 reserved[14];
- __le16 qs_handles[8];
- u8 reserved1[4];
- __le16 port_bw_limit;
- u8 reserved2[2];
- u8 max_bw; /* 0-3, limit = 2^max */
- u8 reserved3[23];
-};
-
-IAVF_CHECK_STRUCT_LEN(0x40, iavf_aqc_query_vsi_bw_config_resp);
-
-/* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
-struct iavf_aqc_query_vsi_ets_sla_config_resp {
- u8 tc_valid_bits;
- u8 reserved[3];
- u8 share_credits[8];
- __le16 credits[8];
-
- /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
- __le16 tc_bw_max[2];
-};
-
-IAVF_CHECK_STRUCT_LEN(0x20, iavf_aqc_query_vsi_ets_sla_config_resp);
-
-/* Configure Switching Component Bandwidth Limit (direct 0x0410) */
-struct iavf_aqc_configure_switching_comp_bw_limit {
- __le16 seid;
- u8 reserved[2];
- __le16 credit;
- u8 reserved1[2];
- u8 max_bw; /* 0-3, limit = 2^max */
- u8 reserved2[7];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_configure_switching_comp_bw_limit);
-
-/* Enable Physical Port ETS (indirect 0x0413)
- * Modify Physical Port ETS (indirect 0x0414)
- * Disable Physical Port ETS (indirect 0x0415)
- */
-struct iavf_aqc_configure_switching_comp_ets_data {
- u8 reserved[4];
- u8 tc_valid_bits;
- u8 seepage;
-#define IAVF_AQ_ETS_SEEPAGE_EN_MASK 0x1
- u8 tc_strict_priority_flags;
- u8 reserved1[17];
- u8 tc_bw_share_credits[8];
- u8 reserved2[96];
-};
-
-IAVF_CHECK_STRUCT_LEN(0x80, iavf_aqc_configure_switching_comp_ets_data);
-
-/* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
-struct iavf_aqc_configure_switching_comp_ets_bw_limit_data {
- u8 tc_valid_bits;
- u8 reserved[15];
- __le16 tc_bw_credit[8];
-
- /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
- __le16 tc_bw_max[2];
- u8 reserved1[28];
-};
-
-IAVF_CHECK_STRUCT_LEN(0x40,
- iavf_aqc_configure_switching_comp_ets_bw_limit_data);
-
-/* Configure Switching Component Bandwidth Allocation per Tc
- * (indirect 0x0417)
- */
-struct iavf_aqc_configure_switching_comp_bw_config_data {
- u8 tc_valid_bits;
- u8 reserved[2];
- u8 absolute_credits; /* bool */
- u8 tc_bw_share_credits[8];
- u8 reserved1[20];
-};
-
-IAVF_CHECK_STRUCT_LEN(0x20, iavf_aqc_configure_switching_comp_bw_config_data);
-
-/* Query Switching Component Configuration (indirect 0x0418) */
-struct iavf_aqc_query_switching_comp_ets_config_resp {
- u8 tc_valid_bits;
- u8 reserved[35];
- __le16 port_bw_limit;
- u8 reserved1[2];
- u8 tc_bw_max; /* 0-3, limit = 2^max */
- u8 reserved2[23];
-};
-
-IAVF_CHECK_STRUCT_LEN(0x40, iavf_aqc_query_switching_comp_ets_config_resp);
-
-/* Query PhysicalPort ETS Configuration (indirect 0x0419) */
-struct iavf_aqc_query_port_ets_config_resp {
- u8 reserved[4];
- u8 tc_valid_bits;
- u8 reserved1;
- u8 tc_strict_priority_bits;
- u8 reserved2;
- u8 tc_bw_share_credits[8];
- __le16 tc_bw_limits[8];
-
- /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
- __le16 tc_bw_max[2];
- u8 reserved3[32];
-};
-
-IAVF_CHECK_STRUCT_LEN(0x44, iavf_aqc_query_port_ets_config_resp);
-
-/* Query Switching Component Bandwidth Allocation per Traffic Type
- * (indirect 0x041A)
- */
-struct iavf_aqc_query_switching_comp_bw_config_resp {
- u8 tc_valid_bits;
- u8 reserved[2];
- u8 absolute_credits_enable; /* bool */
- u8 tc_bw_share_credits[8];
- __le16 tc_bw_limits[8];
-
- /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
- __le16 tc_bw_max[2];
-};
-
-IAVF_CHECK_STRUCT_LEN(0x20, iavf_aqc_query_switching_comp_bw_config_resp);
-
-/* Suspend/resume port TX traffic
- * (direct 0x041B and 0x041C) uses the generic SEID struct
- */
-
-/* Configure partition BW
- * (indirect 0x041D)
- */
-struct iavf_aqc_configure_partition_bw_data {
- __le16 pf_valid_bits;
- u8 min_bw[16]; /* guaranteed bandwidth */
- u8 max_bw[16]; /* bandwidth limit */
-};
-
-IAVF_CHECK_STRUCT_LEN(0x22, iavf_aqc_configure_partition_bw_data);
-
-/* Get and set the active HMC resource profile and status.
- * (direct 0x0500) and (direct 0x0501)
- */
-struct iavf_aq_get_set_hmc_resource_profile {
- u8 pm_profile;
- u8 pe_vf_enabled;
- u8 reserved[14];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aq_get_set_hmc_resource_profile);
-
-enum iavf_aq_hmc_profile {
- /* IAVF_HMC_PROFILE_NO_CHANGE = 0, reserved */
- IAVF_HMC_PROFILE_DEFAULT = 1,
- IAVF_HMC_PROFILE_FAVOR_VF = 2,
- IAVF_HMC_PROFILE_EQUAL = 3,
-};
-
-/* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
-
-/* set in param0 for get phy abilities to report qualified modules */
-#define IAVF_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001
-#define IAVF_AQ_PHY_REPORT_INITIAL_VALUES 0x0002
-
-enum iavf_aq_phy_type {
- IAVF_PHY_TYPE_SGMII = 0x0,
- IAVF_PHY_TYPE_1000BASE_KX = 0x1,
- IAVF_PHY_TYPE_10GBASE_KX4 = 0x2,
- IAVF_PHY_TYPE_10GBASE_KR = 0x3,
- IAVF_PHY_TYPE_40GBASE_KR4 = 0x4,
- IAVF_PHY_TYPE_XAUI = 0x5,
- IAVF_PHY_TYPE_XFI = 0x6,
- IAVF_PHY_TYPE_SFI = 0x7,
- IAVF_PHY_TYPE_XLAUI = 0x8,
- IAVF_PHY_TYPE_XLPPI = 0x9,
- IAVF_PHY_TYPE_40GBASE_CR4_CU = 0xA,
- IAVF_PHY_TYPE_10GBASE_CR1_CU = 0xB,
- IAVF_PHY_TYPE_10GBASE_AOC = 0xC,
- IAVF_PHY_TYPE_40GBASE_AOC = 0xD,
- IAVF_PHY_TYPE_UNRECOGNIZED = 0xE,
- IAVF_PHY_TYPE_UNSUPPORTED = 0xF,
- IAVF_PHY_TYPE_100BASE_TX = 0x11,
- IAVF_PHY_TYPE_1000BASE_T = 0x12,
- IAVF_PHY_TYPE_10GBASE_T = 0x13,
- IAVF_PHY_TYPE_10GBASE_SR = 0x14,
- IAVF_PHY_TYPE_10GBASE_LR = 0x15,
- IAVF_PHY_TYPE_10GBASE_SFPP_CU = 0x16,
- IAVF_PHY_TYPE_10GBASE_CR1 = 0x17,
- IAVF_PHY_TYPE_40GBASE_CR4 = 0x18,
- IAVF_PHY_TYPE_40GBASE_SR4 = 0x19,
- IAVF_PHY_TYPE_40GBASE_LR4 = 0x1A,
- IAVF_PHY_TYPE_1000BASE_SX = 0x1B,
- IAVF_PHY_TYPE_1000BASE_LX = 0x1C,
- IAVF_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D,
- IAVF_PHY_TYPE_20GBASE_KR2 = 0x1E,
- IAVF_PHY_TYPE_25GBASE_KR = 0x1F,
- IAVF_PHY_TYPE_25GBASE_CR = 0x20,
- IAVF_PHY_TYPE_25GBASE_SR = 0x21,
- IAVF_PHY_TYPE_25GBASE_LR = 0x22,
- IAVF_PHY_TYPE_25GBASE_AOC = 0x23,
- IAVF_PHY_TYPE_25GBASE_ACC = 0x24,
- IAVF_PHY_TYPE_MAX,
- IAVF_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP = 0xFD,
- IAVF_PHY_TYPE_EMPTY = 0xFE,
- IAVF_PHY_TYPE_DEFAULT = 0xFF,
-};
-
-#define IAVF_LINK_SPEED_100MB_SHIFT 0x1
-#define IAVF_LINK_SPEED_1000MB_SHIFT 0x2
-#define IAVF_LINK_SPEED_10GB_SHIFT 0x3
-#define IAVF_LINK_SPEED_40GB_SHIFT 0x4
-#define IAVF_LINK_SPEED_20GB_SHIFT 0x5
-#define IAVF_LINK_SPEED_25GB_SHIFT 0x6
-
-enum iavf_aq_link_speed {
- IAVF_LINK_SPEED_UNKNOWN = 0,
- IAVF_LINK_SPEED_100MB = (1 << IAVF_LINK_SPEED_100MB_SHIFT),
- IAVF_LINK_SPEED_1GB = (1 << IAVF_LINK_SPEED_1000MB_SHIFT),
- IAVF_LINK_SPEED_10GB = (1 << IAVF_LINK_SPEED_10GB_SHIFT),
- IAVF_LINK_SPEED_40GB = (1 << IAVF_LINK_SPEED_40GB_SHIFT),
- IAVF_LINK_SPEED_20GB = (1 << IAVF_LINK_SPEED_20GB_SHIFT),
- IAVF_LINK_SPEED_25GB = (1 << IAVF_LINK_SPEED_25GB_SHIFT),
-};
-
-struct iavf_aqc_module_desc {
- u8 oui[3];
- u8 reserved1;
- u8 part_number[16];
- u8 revision[4];
- u8 reserved2[8];
-};
-
-IAVF_CHECK_STRUCT_LEN(0x20, iavf_aqc_module_desc);
-
-struct iavf_aq_get_phy_abilities_resp {
- __le32 phy_type; /* bitmap using the above enum for offsets */
- u8 link_speed; /* bitmap using the above enum bit patterns */
- u8 abilities;
-#define IAVF_AQ_PHY_FLAG_PAUSE_TX 0x01
-#define IAVF_AQ_PHY_FLAG_PAUSE_RX 0x02
-#define IAVF_AQ_PHY_FLAG_LOW_POWER 0x04
-#define IAVF_AQ_PHY_LINK_ENABLED 0x08
-#define IAVF_AQ_PHY_AN_ENABLED 0x10
-#define IAVF_AQ_PHY_FLAG_MODULE_QUAL 0x20
-#define IAVF_AQ_PHY_FEC_ABILITY_KR 0x40
-#define IAVF_AQ_PHY_FEC_ABILITY_RS 0x80
- __le16 eee_capability;
-#define IAVF_AQ_EEE_100BASE_TX 0x0002
-#define IAVF_AQ_EEE_1000BASE_T 0x0004
-#define IAVF_AQ_EEE_10GBASE_T 0x0008
-#define IAVF_AQ_EEE_1000BASE_KX 0x0010
-#define IAVF_AQ_EEE_10GBASE_KX4 0x0020
-#define IAVF_AQ_EEE_10GBASE_KR 0x0040
- __le32 eeer_val;
- u8 d3_lpan;
-#define IAVF_AQ_SET_PHY_D3_LPAN_ENA 0x01
- u8 phy_type_ext;
-#define IAVF_AQ_PHY_TYPE_EXT_25G_KR 0x01
-#define IAVF_AQ_PHY_TYPE_EXT_25G_CR 0x02
-#define IAVF_AQ_PHY_TYPE_EXT_25G_SR 0x04
-#define IAVF_AQ_PHY_TYPE_EXT_25G_LR 0x08
-#define IAVF_AQ_PHY_TYPE_EXT_25G_AOC 0x10
-#define IAVF_AQ_PHY_TYPE_EXT_25G_ACC 0x20
- u8 fec_cfg_curr_mod_ext_info;
-#define IAVF_AQ_ENABLE_FEC_KR 0x01
-#define IAVF_AQ_ENABLE_FEC_RS 0x02
-#define IAVF_AQ_REQUEST_FEC_KR 0x04
-#define IAVF_AQ_REQUEST_FEC_RS 0x08
-#define IAVF_AQ_ENABLE_FEC_AUTO 0x10
-#define IAVF_AQ_FEC
-#define IAVF_AQ_MODULE_TYPE_EXT_MASK 0xE0
-#define IAVF_AQ_MODULE_TYPE_EXT_SHIFT 5
-
- u8 ext_comp_code;
- u8 phy_id[4];
- u8 module_type[3];
- u8 qualified_module_count;
-#define IAVF_AQ_PHY_MAX_QMS 16
- struct iavf_aqc_module_desc qualified_module[IAVF_AQ_PHY_MAX_QMS];
-};
-
-IAVF_CHECK_STRUCT_LEN(0x218, iavf_aq_get_phy_abilities_resp);
-
-/* Set PHY Config (direct 0x0601) */
-struct iavf_aq_set_phy_config { /* same bits as above in all */
- __le32 phy_type;
- u8 link_speed;
- u8 abilities;
-/* bits 0-2 use the values from get_phy_abilities_resp */
-#define IAVF_AQ_PHY_ENABLE_LINK 0x08
-#define IAVF_AQ_PHY_ENABLE_AN 0x10
-#define IAVF_AQ_PHY_ENABLE_ATOMIC_LINK 0x20
- __le16 eee_capability;
- __le32 eeer;
- u8 low_power_ctrl;
- u8 phy_type_ext;
- u8 fec_config;
-#define IAVF_AQ_SET_FEC_ABILITY_KR BIT(0)
-#define IAVF_AQ_SET_FEC_ABILITY_RS BIT(1)
-#define IAVF_AQ_SET_FEC_REQUEST_KR BIT(2)
-#define IAVF_AQ_SET_FEC_REQUEST_RS BIT(3)
-#define IAVF_AQ_SET_FEC_AUTO BIT(4)
-#define IAVF_AQ_PHY_FEC_CONFIG_SHIFT 0x0
-#define IAVF_AQ_PHY_FEC_CONFIG_MASK (0x1F << IAVF_AQ_PHY_FEC_CONFIG_SHIFT)
- u8 reserved;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aq_set_phy_config);
-
-/* Set MAC Config command data structure (direct 0x0603) */
-struct iavf_aq_set_mac_config {
- __le16 max_frame_size;
- u8 params;
-#define IAVF_AQ_SET_MAC_CONFIG_CRC_EN 0x04
-#define IAVF_AQ_SET_MAC_CONFIG_PACING_MASK 0x78
-#define IAVF_AQ_SET_MAC_CONFIG_PACING_SHIFT 3
-#define IAVF_AQ_SET_MAC_CONFIG_PACING_NONE 0x0
-#define IAVF_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF
-#define IAVF_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9
-#define IAVF_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8
-#define IAVF_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7
-#define IAVF_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6
-#define IAVF_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5
-#define IAVF_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4
-#define IAVF_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3
-#define IAVF_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2
-#define IAVF_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1
- u8 tx_timer_priority; /* bitmap */
- __le16 tx_timer_value;
- __le16 fc_refresh_threshold;
- u8 reserved[8];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aq_set_mac_config);
-
-/* Restart Auto-Negotiation (direct 0x605) */
-struct iavf_aqc_set_link_restart_an {
- u8 command;
-#define IAVF_AQ_PHY_RESTART_AN 0x02
-#define IAVF_AQ_PHY_LINK_ENABLE 0x04
- u8 reserved[15];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_link_restart_an);
-
-/* Get Link Status cmd & response data structure (direct 0x0607) */
-struct iavf_aqc_get_link_status {
- __le16 command_flags; /* only field set on command */
-#define IAVF_AQ_LSE_MASK 0x3
-#define IAVF_AQ_LSE_NOP 0x0
-#define IAVF_AQ_LSE_DISABLE 0x2
-#define IAVF_AQ_LSE_ENABLE 0x3
-/* only response uses this flag */
-#define IAVF_AQ_LSE_IS_ENABLED 0x1
- u8 phy_type; /* iavf_aq_phy_type */
- u8 link_speed; /* iavf_aq_link_speed */
- u8 link_info;
-#define IAVF_AQ_LINK_UP 0x01 /* obsolete */
-#define IAVF_AQ_LINK_UP_FUNCTION 0x01
-#define IAVF_AQ_LINK_FAULT 0x02
-#define IAVF_AQ_LINK_FAULT_TX 0x04
-#define IAVF_AQ_LINK_FAULT_RX 0x08
-#define IAVF_AQ_LINK_FAULT_REMOTE 0x10
-#define IAVF_AQ_LINK_UP_PORT 0x20
-#define IAVF_AQ_MEDIA_AVAILABLE 0x40
-#define IAVF_AQ_SIGNAL_DETECT 0x80
- u8 an_info;
-#define IAVF_AQ_AN_COMPLETED 0x01
-#define IAVF_AQ_LP_AN_ABILITY 0x02
-#define IAVF_AQ_PD_FAULT 0x04
-#define IAVF_AQ_FEC_EN 0x08
-#define IAVF_AQ_PHY_LOW_POWER 0x10
-#define IAVF_AQ_LINK_PAUSE_TX 0x20
-#define IAVF_AQ_LINK_PAUSE_RX 0x40
-#define IAVF_AQ_QUALIFIED_MODULE 0x80
- u8 ext_info;
-#define IAVF_AQ_LINK_PHY_TEMP_ALARM 0x01
-#define IAVF_AQ_LINK_XCESSIVE_ERRORS 0x02
-#define IAVF_AQ_LINK_TX_SHIFT 0x02
-#define IAVF_AQ_LINK_TX_MASK (0x03 << IAVF_AQ_LINK_TX_SHIFT)
-#define IAVF_AQ_LINK_TX_ACTIVE 0x00
-#define IAVF_AQ_LINK_TX_DRAINED 0x01
-#define IAVF_AQ_LINK_TX_FLUSHED 0x03
-#define IAVF_AQ_LINK_FORCED_40G 0x10
-/* 25G Error Codes */
-#define IAVF_AQ_25G_NO_ERR 0X00
-#define IAVF_AQ_25G_NOT_PRESENT 0X01
-#define IAVF_AQ_25G_NVM_CRC_ERR 0X02
-#define IAVF_AQ_25G_SBUS_UCODE_ERR 0X03
-#define IAVF_AQ_25G_SERDES_UCODE_ERR 0X04
-#define IAVF_AQ_25G_NIMB_UCODE_ERR 0X05
- u8 loopback; /* use defines from iavf_aqc_set_lb_mode */
-/* Since firmware API 1.7 loopback field keeps power class info as well */
-#define IAVF_AQ_LOOPBACK_MASK 0x07
-#define IAVF_AQ_PWR_CLASS_SHIFT_LB 6
-#define IAVF_AQ_PWR_CLASS_MASK_LB (0x03 << IAVF_AQ_PWR_CLASS_SHIFT_LB)
- __le16 max_frame_size;
- u8 config;
-#define IAVF_AQ_CONFIG_FEC_KR_ENA 0x01
-#define IAVF_AQ_CONFIG_FEC_RS_ENA 0x02
-#define IAVF_AQ_CONFIG_CRC_ENA 0x04
-#define IAVF_AQ_CONFIG_PACING_MASK 0x78
- union {
- struct {
- u8 power_desc;
-#define IAVF_AQ_LINK_POWER_CLASS_1 0x00
-#define IAVF_AQ_LINK_POWER_CLASS_2 0x01
-#define IAVF_AQ_LINK_POWER_CLASS_3 0x02
-#define IAVF_AQ_LINK_POWER_CLASS_4 0x03
-#define IAVF_AQ_PWR_CLASS_MASK 0x03
- u8 reserved[4];
- };
- struct {
- u8 link_type[4];
- u8 link_type_ext;
- };
- };
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_link_status);
-
-/* Set event mask command (direct 0x613) */
-struct iavf_aqc_set_phy_int_mask {
- u8 reserved[8];
- __le16 event_mask;
-#define IAVF_AQ_EVENT_LINK_UPDOWN 0x0002
-#define IAVF_AQ_EVENT_MEDIA_NA 0x0004
-#define IAVF_AQ_EVENT_LINK_FAULT 0x0008
-#define IAVF_AQ_EVENT_PHY_TEMP_ALARM 0x0010
-#define IAVF_AQ_EVENT_EXCESSIVE_ERRORS 0x0020
-#define IAVF_AQ_EVENT_SIGNAL_DETECT 0x0040
-#define IAVF_AQ_EVENT_AN_COMPLETED 0x0080
-#define IAVF_AQ_EVENT_MODULE_QUAL_FAIL 0x0100
-#define IAVF_AQ_EVENT_PORT_TX_SUSPENDED 0x0200
- u8 reserved1[6];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_phy_int_mask);
-
-/* Get Local AN advt register (direct 0x0614)
- * Set Local AN advt register (direct 0x0615)
- * Get Link Partner AN advt register (direct 0x0616)
- */
-struct iavf_aqc_an_advt_reg {
- __le32 local_an_reg0;
- __le16 local_an_reg1;
- u8 reserved[10];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_an_advt_reg);
-
-/* Set Loopback mode (0x0618) */
-struct iavf_aqc_set_lb_mode {
- u8 lb_level;
-#define IAVF_AQ_LB_NONE 0
-#define IAVF_AQ_LB_MAC 1
-#define IAVF_AQ_LB_SERDES 2
-#define IAVF_AQ_LB_PHY_INT 3
-#define IAVF_AQ_LB_PHY_EXT 4
-#define IAVF_AQ_LB_CPVL_PCS 5
-#define IAVF_AQ_LB_CPVL_EXT 6
-#define IAVF_AQ_LB_PHY_LOCAL 0x01
-#define IAVF_AQ_LB_PHY_REMOTE 0x02
-#define IAVF_AQ_LB_MAC_LOCAL 0x04
- u8 lb_type;
-#define IAVF_AQ_LB_LOCAL 0
-#define IAVF_AQ_LB_FAR 0x01
- u8 speed;
-#define IAVF_AQ_LB_SPEED_NONE 0
-#define IAVF_AQ_LB_SPEED_1G 1
-#define IAVF_AQ_LB_SPEED_10G 2
-#define IAVF_AQ_LB_SPEED_40G 3
-#define IAVF_AQ_LB_SPEED_20G 4
- u8 force_speed;
- u8 reserved[12];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_lb_mode);
-
-/* Set PHY Debug command (0x0622) */
-struct iavf_aqc_set_phy_debug {
- u8 command_flags;
-#define IAVF_AQ_PHY_DEBUG_RESET_INTERNAL 0x02
-#define IAVF_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2
-#define IAVF_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \
- IAVF_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)
-#define IAVF_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00
-#define IAVF_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01
-#define IAVF_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02
-/* Disable link manageability on a single port */
-#define IAVF_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10
-/* Disable link manageability on all ports needs both bits 4 and 5 */
-#define IAVF_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW 0x20
- u8 reserved[15];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_phy_debug);
-
-enum iavf_aq_phy_reg_type {
- IAVF_AQC_PHY_REG_INTERNAL = 0x1,
- IAVF_AQC_PHY_REG_EXERNAL_BASET = 0x2,
- IAVF_AQC_PHY_REG_EXERNAL_MODULE = 0x3
-};
-
-/* Run PHY Activity (0x0626) */
-struct iavf_aqc_run_phy_activity {
- __le16 activity_id;
- u8 flags;
- u8 reserved1;
- __le32 control;
- __le32 data;
- u8 reserved2[4];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_run_phy_activity);
-
-/* Set PHY Register command (0x0628) */
-/* Get PHY Register command (0x0629) */
-struct iavf_aqc_phy_register_access {
- u8 phy_interface;
-#define IAVF_AQ_PHY_REG_ACCESS_INTERNAL 0
-#define IAVF_AQ_PHY_REG_ACCESS_EXTERNAL 1
-#define IAVF_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE 2
- u8 dev_addres;
- u8 reserved1[2];
- __le32 reg_address;
- __le32 reg_value;
- u8 reserved2[4];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_phy_register_access);
-
-/* NVM Read command (indirect 0x0701)
- * NVM Erase commands (direct 0x0702)
- * NVM Update commands (indirect 0x0703)
- */
-struct iavf_aqc_nvm_update {
- u8 command_flags;
-#define IAVF_AQ_NVM_LAST_CMD 0x01
-#define IAVF_AQ_NVM_FLASH_ONLY 0x80
-#define IAVF_AQ_NVM_PRESERVATION_FLAGS_SHIFT 1
-#define IAVF_AQ_NVM_PRESERVATION_FLAGS_MASK 0x03
-#define IAVF_AQ_NVM_PRESERVATION_FLAGS_SELECTED 0x03
-#define IAVF_AQ_NVM_PRESERVATION_FLAGS_ALL 0x01
- u8 module_pointer;
- __le16 length;
- __le32 offset;
- __le32 addr_high;
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_nvm_update);
-
-/* NVM Config Read (indirect 0x0704) */
-struct iavf_aqc_nvm_config_read {
- __le16 cmd_flags;
-#define IAVF_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1
-#define IAVF_AQ_ANVM_READ_SINGLE_FEATURE 0
-#define IAVF_AQ_ANVM_READ_MULTIPLE_FEATURES 1
- __le16 element_count;
- __le16 element_id; /* Feature/field ID */
- __le16 element_id_msw; /* MSWord of field ID */
- __le32 address_high;
- __le32 address_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_nvm_config_read);
-
-/* NVM Config Write (indirect 0x0705) */
-struct iavf_aqc_nvm_config_write {
- __le16 cmd_flags;
- __le16 element_count;
- u8 reserved[4];
- __le32 address_high;
- __le32 address_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_nvm_config_write);
-
-/* Used for 0x0704 as well as for 0x0705 commands */
-#define IAVF_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1
-#define IAVF_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \
- (1 << IAVF_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT)
-#define IAVF_AQ_ANVM_FEATURE 0
-#define IAVF_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT)
-struct iavf_aqc_nvm_config_data_feature {
- __le16 feature_id;
-#define IAVF_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01
-#define IAVF_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08
-#define IAVF_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10
- __le16 feature_options;
- __le16 feature_selection;
-};
-
-IAVF_CHECK_STRUCT_LEN(0x6, iavf_aqc_nvm_config_data_feature);
-
-struct iavf_aqc_nvm_config_data_immediate_field {
- __le32 field_id;
- __le32 field_value;
- __le16 field_options;
- __le16 reserved;
-};
-
-IAVF_CHECK_STRUCT_LEN(0xc, iavf_aqc_nvm_config_data_immediate_field);
-
-/* OEM Post Update (indirect 0x0720)
- * no command data struct used
- */
-struct iavf_aqc_nvm_oem_post_update {
-#define IAVF_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01
- u8 sel_data;
- u8 reserved[7];
-};
-
-IAVF_CHECK_STRUCT_LEN(0x8, iavf_aqc_nvm_oem_post_update);
-
-struct iavf_aqc_nvm_oem_post_update_buffer {
- u8 str_len;
- u8 dev_addr;
- __le16 eeprom_addr;
- u8 data[36];
-};
-
-IAVF_CHECK_STRUCT_LEN(0x28, iavf_aqc_nvm_oem_post_update_buffer);
-
-/* Thermal Sensor (indirect 0x0721)
- * read or set thermal sensor configs and values
- * takes a sensor and command specific data buffer, not detailed here
- */
-struct iavf_aqc_thermal_sensor {
- u8 sensor_action;
-#define IAVF_AQ_THERMAL_SENSOR_READ_CONFIG 0
-#define IAVF_AQ_THERMAL_SENSOR_SET_CONFIG 1
-#define IAVF_AQ_THERMAL_SENSOR_READ_TEMP 2
- u8 reserved[7];
- __le32 addr_high;
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_thermal_sensor);
-
-/* Send to PF command (indirect 0x0801) id is only used by PF
- * Send to VF command (indirect 0x0802) id is only used by PF
- * Send to Peer PF command (indirect 0x0803)
- */
-struct iavf_aqc_pf_vf_message {
- __le32 id;
- u8 reserved[4];
- __le32 addr_high;
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_pf_vf_message);
-
-/* Alternate structure */
-
-/* Direct write (direct 0x0900)
- * Direct read (direct 0x0902)
- */
-struct iavf_aqc_alternate_write {
- __le32 address0;
- __le32 data0;
- __le32 address1;
- __le32 data1;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_alternate_write);
-
-/* Indirect write (indirect 0x0901)
- * Indirect read (indirect 0x0903)
- */
-
-struct iavf_aqc_alternate_ind_write {
- __le32 address;
- __le32 length;
- __le32 addr_high;
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_alternate_ind_write);
-
-/* Done alternate write (direct 0x0904)
- * uses iavf_aq_desc
- */
-struct iavf_aqc_alternate_write_done {
- __le16 cmd_flags;
-#define IAVF_AQ_ALTERNATE_MODE_BIOS_MASK 1
-#define IAVF_AQ_ALTERNATE_MODE_BIOS_LEGACY 0
-#define IAVF_AQ_ALTERNATE_MODE_BIOS_UEFI 1
-#define IAVF_AQ_ALTERNATE_RESET_NEEDED 2
- u8 reserved[14];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_alternate_write_done);
-
-/* Set OEM mode (direct 0x0905) */
-struct iavf_aqc_alternate_set_mode {
- __le32 mode;
-#define IAVF_AQ_ALTERNATE_MODE_NONE 0
-#define IAVF_AQ_ALTERNATE_MODE_OEM 1
- u8 reserved[12];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_alternate_set_mode);
-
-/* Clear port Alternate RAM (direct 0x0906) uses iavf_aq_desc */
-
-/* async events 0x10xx */
-
-/* Lan Queue Overflow Event (direct, 0x1001) */
-struct iavf_aqc_lan_overflow {
- __le32 prtdcb_rupto;
- __le32 otx_ctl;
- u8 reserved[8];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_lan_overflow);
-
-/* Get LLDP MIB (indirect 0x0A00) */
-struct iavf_aqc_lldp_get_mib {
- u8 type;
- u8 reserved1;
-#define IAVF_AQ_LLDP_MIB_TYPE_MASK 0x3
-#define IAVF_AQ_LLDP_MIB_LOCAL 0x0
-#define IAVF_AQ_LLDP_MIB_REMOTE 0x1
-#define IAVF_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2
-#define IAVF_AQ_LLDP_BRIDGE_TYPE_MASK 0xC
-#define IAVF_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2
-#define IAVF_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0
-#define IAVF_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1
-#define IAVF_AQ_LLDP_TX_SHIFT 0x4
-#define IAVF_AQ_LLDP_TX_MASK (0x03 << IAVF_AQ_LLDP_TX_SHIFT)
-/* TX pause flags use IAVF_AQ_LINK_TX_* above */
- __le16 local_len;
- __le16 remote_len;
- u8 reserved2[2];
- __le32 addr_high;
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_lldp_get_mib);
-
-/* Configure LLDP MIB Change Event (direct 0x0A01)
- * also used for the event (with type in the command field)
- */
-struct iavf_aqc_lldp_update_mib {
- u8 command;
-#define IAVF_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
-#define IAVF_AQ_LLDP_MIB_UPDATE_DISABLE 0x1
- u8 reserved[7];
- __le32 addr_high;
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_lldp_update_mib);
-
-/* Add LLDP TLV (indirect 0x0A02)
- * Delete LLDP TLV (indirect 0x0A04)
- */
-struct iavf_aqc_lldp_add_tlv {
- u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
- u8 reserved1[1];
- __le16 len;
- u8 reserved2[4];
- __le32 addr_high;
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_lldp_add_tlv);
-
-/* Update LLDP TLV (indirect 0x0A03) */
-struct iavf_aqc_lldp_update_tlv {
- u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
- u8 reserved;
- __le16 old_len;
- __le16 new_offset;
- __le16 new_len;
- __le32 addr_high;
- __le32 addr_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_lldp_update_tlv);
-
-/* Stop LLDP (direct 0x0A05) */
-struct iavf_aqc_lldp_stop {
- u8 command;
-#define IAVF_AQ_LLDP_AGENT_STOP 0x0
-#define IAVF_AQ_LLDP_AGENT_SHUTDOWN 0x1
- u8 reserved[15];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_lldp_stop);
-
-/* Start LLDP (direct 0x0A06) */
-
-struct iavf_aqc_lldp_start {
- u8 command;
-#define IAVF_AQ_LLDP_AGENT_START 0x1
- u8 reserved[15];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_lldp_start);
-
-/* Set DCB (direct 0x0303) */
-struct iavf_aqc_set_dcb_parameters {
- u8 command;
-#define IAVF_AQ_DCB_SET_AGENT 0x1
-#define IAVF_DCB_VALID 0x1
- u8 valid_flags;
- u8 reserved[14];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_dcb_parameters);
-
-/* Get CEE DCBX Oper Config (0x0A07)
- * uses the generic descriptor struct
- * returns below as indirect response
- */
-
-#define IAVF_AQC_CEE_APP_FCOE_SHIFT 0x0
-#define IAVF_AQC_CEE_APP_FCOE_MASK (0x7 << IAVF_AQC_CEE_APP_FCOE_SHIFT)
-#define IAVF_AQC_CEE_APP_ISCSI_SHIFT 0x3
-#define IAVF_AQC_CEE_APP_ISCSI_MASK (0x7 << IAVF_AQC_CEE_APP_ISCSI_SHIFT)
-#define IAVF_AQC_CEE_APP_FIP_SHIFT 0x8
-#define IAVF_AQC_CEE_APP_FIP_MASK (0x7 << IAVF_AQC_CEE_APP_FIP_SHIFT)
-
-#define IAVF_AQC_CEE_PG_STATUS_SHIFT 0x0
-#define IAVF_AQC_CEE_PG_STATUS_MASK (0x7 << IAVF_AQC_CEE_PG_STATUS_SHIFT)
-#define IAVF_AQC_CEE_PFC_STATUS_SHIFT 0x3
-#define IAVF_AQC_CEE_PFC_STATUS_MASK (0x7 << IAVF_AQC_CEE_PFC_STATUS_SHIFT)
-#define IAVF_AQC_CEE_APP_STATUS_SHIFT 0x8
-#define IAVF_AQC_CEE_APP_STATUS_MASK (0x7 << IAVF_AQC_CEE_APP_STATUS_SHIFT)
-#define IAVF_AQC_CEE_FCOE_STATUS_SHIFT 0x8
-#define IAVF_AQC_CEE_FCOE_STATUS_MASK (0x7 << IAVF_AQC_CEE_FCOE_STATUS_SHIFT)
-#define IAVF_AQC_CEE_ISCSI_STATUS_SHIFT 0xB
-#define IAVF_AQC_CEE_ISCSI_STATUS_MASK (0x7 << IAVF_AQC_CEE_ISCSI_STATUS_SHIFT)
-#define IAVF_AQC_CEE_FIP_STATUS_SHIFT 0x10
-#define IAVF_AQC_CEE_FIP_STATUS_MASK (0x7 << IAVF_AQC_CEE_FIP_STATUS_SHIFT)
-
-/* struct iavf_aqc_get_cee_dcb_cfg_v1_resp was originally defined with
- * word boundary layout issues, which the Linux compilers silently deal
- * with by adding padding, making the actual struct larger than designed.
- * However, the FW compiler for the NIC is less lenient and complains
- * about the struct. Hence, the struct defined here has an extra byte in
- * fields reserved3 and reserved4 to directly acknowledge that padding,
- * and the new length is used in the length check macro.
- */
-struct iavf_aqc_get_cee_dcb_cfg_v1_resp {
- u8 reserved1;
- u8 oper_num_tc;
- u8 oper_prio_tc[4];
- u8 reserved2;
- u8 oper_tc_bw[8];
- u8 oper_pfc_en;
- u8 reserved3[2];
- __le16 oper_app_prio;
- u8 reserved4[2];
- __le16 tlv_status;
-};
-
-IAVF_CHECK_STRUCT_LEN(0x18, iavf_aqc_get_cee_dcb_cfg_v1_resp);
-
-struct iavf_aqc_get_cee_dcb_cfg_resp {
- u8 oper_num_tc;
- u8 oper_prio_tc[4];
- u8 oper_tc_bw[8];
- u8 oper_pfc_en;
- __le16 oper_app_prio;
- __le32 tlv_status;
- u8 reserved[12];
-};
-
-IAVF_CHECK_STRUCT_LEN(0x20, iavf_aqc_get_cee_dcb_cfg_resp);
-
-/* Set Local LLDP MIB (indirect 0x0A08)
- * Used to replace the local MIB of a given LLDP agent. e.g. DCBx
- */
-struct iavf_aqc_lldp_set_local_mib {
-#define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0
-#define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << \
- SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT)
-#define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0
-#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1)
-#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK (1 << \
- SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT)
-#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1
- u8 type;
- u8 reserved0;
- __le16 length;
- u8 reserved1[4];
- __le32 address_high;
- __le32 address_low;
+struct iavf_aqc_lldp_set_local_mib {
+#define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0
+#define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << \
+ SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT)
+#define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0
+#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT (1)
+#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK (1 << \
+ SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT)
+#define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS 0x1
+ u8 type;
+ u8 reserved0;
+ __le16 length;
+ u8 reserved1[4];
+ __le32 address_high;
+ __le32 address_low;
};
IAVF_CHECK_CMD_LENGTH(iavf_aqc_lldp_set_local_mib);
@@ -2567,51 +604,6 @@ struct iavf_aqc_lldp_stop_start_specific_agent {
IAVF_CHECK_CMD_LENGTH(iavf_aqc_lldp_stop_start_specific_agent);
-/* Add Udp Tunnel command and completion (direct 0x0B00) */
-struct iavf_aqc_add_udp_tunnel {
- __le16 udp_port;
- u8 reserved0[3];
- u8 protocol_type;
-#define IAVF_AQC_TUNNEL_TYPE_VXLAN 0x00
-#define IAVF_AQC_TUNNEL_TYPE_NGE 0x01
-#define IAVF_AQC_TUNNEL_TYPE_TEREDO 0x10
-#define IAVF_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11
- u8 reserved1[10];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_udp_tunnel);
-
-struct iavf_aqc_add_udp_tunnel_completion {
- __le16 udp_port;
- u8 filter_entry_index;
- u8 multiple_pfs;
-#define IAVF_AQC_SINGLE_PF 0x0
-#define IAVF_AQC_MULTIPLE_PFS 0x1
- u8 total_filters;
- u8 reserved[11];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_udp_tunnel_completion);
-
-/* remove UDP Tunnel command (0x0B01) */
-struct iavf_aqc_remove_udp_tunnel {
- u8 reserved[2];
- u8 index; /* 0 to 15 */
- u8 reserved2[13];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_remove_udp_tunnel);
-
-struct iavf_aqc_del_udp_tunnel_completion {
- __le16 udp_port;
- u8 index; /* 0 to 15 */
- u8 multiple_pfs;
- u8 total_filters_used;
- u8 reserved1[11];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_del_udp_tunnel_completion);
-
struct iavf_aqc_get_set_rss_key {
#define IAVF_AQC_SET_RSS_KEY_VSI_VALID (0x1 << 15)
#define IAVF_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0
@@ -2651,162 +643,4 @@ struct iavf_aqc_get_set_rss_lut {
};
IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_set_rss_lut);
-
-/* tunnel key structure 0x0B10 */
-
-struct iavf_aqc_tunnel_key_structure {
- u8 key1_off;
- u8 key2_off;
- u8 key1_len; /* 0 to 15 */
- u8 key2_len; /* 0 to 15 */
- u8 flags;
-#define IAVF_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
-/* response flags */
-#define IAVF_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01
-#define IAVF_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02
-#define IAVF_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
- u8 network_key_index;
-#define IAVF_AQC_NETWORK_KEY_INDEX_VXLAN 0x0
-#define IAVF_AQC_NETWORK_KEY_INDEX_NGE 0x1
-#define IAVF_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2
-#define IAVF_AQC_NETWORK_KEY_INDEX_GRE 0x3
- u8 reserved[10];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_tunnel_key_structure);
-
-/* OEM mode commands (direct 0xFE0x) */
-struct iavf_aqc_oem_param_change {
- __le32 param_type;
-#define IAVF_AQ_OEM_PARAM_TYPE_PF_CTL 0
-#define IAVF_AQ_OEM_PARAM_TYPE_BW_CTL 1
-#define IAVF_AQ_OEM_PARAM_MAC 2
- __le32 param_value1;
- __le16 param_value2;
- u8 reserved[6];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_oem_param_change);
-
-struct iavf_aqc_oem_state_change {
- __le32 state;
-#define IAVF_AQ_OEM_STATE_LINK_DOWN 0x0
-#define IAVF_AQ_OEM_STATE_LINK_UP 0x1
- u8 reserved[12];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_oem_state_change);
-
-/* Initialize OCSD (0xFE02, direct) */
-struct iavf_aqc_opc_oem_ocsd_initialize {
- u8 type_status;
- u8 reserved1[3];
- __le32 ocsd_memory_block_addr_high;
- __le32 ocsd_memory_block_addr_low;
- __le32 requested_update_interval;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_opc_oem_ocsd_initialize);
-
-/* Initialize OCBB (0xFE03, direct) */
-struct iavf_aqc_opc_oem_ocbb_initialize {
- u8 type_status;
- u8 reserved1[3];
- __le32 ocbb_memory_block_addr_high;
- __le32 ocbb_memory_block_addr_low;
- u8 reserved2[4];
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_opc_oem_ocbb_initialize);
-
-/* debug commands */
-
-/* get device id (0xFF00) uses the generic structure */
-
-/* set test more (0xFF01, internal) */
-
-struct iavf_acq_set_test_mode {
- u8 mode;
-#define IAVF_AQ_TEST_PARTIAL 0
-#define IAVF_AQ_TEST_FULL 1
-#define IAVF_AQ_TEST_NVM 2
- u8 reserved[3];
- u8 command;
-#define IAVF_AQ_TEST_OPEN 0
-#define IAVF_AQ_TEST_CLOSE 1
-#define IAVF_AQ_TEST_INC 2
- u8 reserved2[3];
- __le32 address_high;
- __le32 address_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_acq_set_test_mode);
-
-/* Debug Read Register command (0xFF03)
- * Debug Write Register command (0xFF04)
- */
-struct iavf_aqc_debug_reg_read_write {
- __le32 reserved;
- __le32 address;
- __le32 value_high;
- __le32 value_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_debug_reg_read_write);
-
-/* Scatter/gather Reg Read (indirect 0xFF05)
- * Scatter/gather Reg Write (indirect 0xFF06)
- */
-
-/* iavf_aq_desc is used for the command */
-struct iavf_aqc_debug_reg_sg_element_data {
- __le32 address;
- __le32 value;
-};
-
-/* Debug Modify register (direct 0xFF07) */
-struct iavf_aqc_debug_modify_reg {
- __le32 address;
- __le32 value;
- __le32 clear_mask;
- __le32 set_mask;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_debug_modify_reg);
-
-/* dump internal data (0xFF08, indirect) */
-
-#define IAVF_AQ_CLUSTER_ID_AUX 0
-#define IAVF_AQ_CLUSTER_ID_SWITCH_FLU 1
-#define IAVF_AQ_CLUSTER_ID_TXSCHED 2
-#define IAVF_AQ_CLUSTER_ID_HMC 3
-#define IAVF_AQ_CLUSTER_ID_MAC0 4
-#define IAVF_AQ_CLUSTER_ID_MAC1 5
-#define IAVF_AQ_CLUSTER_ID_MAC2 6
-#define IAVF_AQ_CLUSTER_ID_MAC3 7
-#define IAVF_AQ_CLUSTER_ID_DCB 8
-#define IAVF_AQ_CLUSTER_ID_EMP_MEM 9
-#define IAVF_AQ_CLUSTER_ID_PKT_BUF 10
-#define IAVF_AQ_CLUSTER_ID_ALTRAM 11
-
-struct iavf_aqc_debug_dump_internals {
- u8 cluster_id;
- u8 table_id;
- __le16 data_size;
- __le32 idx;
- __le32 address_high;
- __le32 address_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_debug_dump_internals);
-
-struct iavf_aqc_debug_modify_internals {
- u8 cluster_id;
- u8 cluster_specific_params[7];
- __le32 address_high;
- __le32 address_low;
-};
-
-IAVF_CHECK_CMD_LENGTH(iavf_aqc_debug_modify_internals);
-
#endif /* _IAVF_ADMINQ_CMD_H_ */
diff --git a/drivers/net/iavf/base/iavf_common.c b/drivers/net/iavf/base/iavf_common.c
index 026dc4756..926081e87 100644
--- a/drivers/net/iavf/base/iavf_common.c
+++ b/drivers/net/iavf/base/iavf_common.c
@@ -891,7 +891,6 @@ struct iavf_rx_ptype_decoded iavf_ptype_lookup[] = {
IAVF_PTT_UNUSED_ENTRY(255)
};
-
/**
* iavf_validate_mac_addr - Validate unicast MAC address
* @mac_addr: pointer to MAC address
@@ -917,202 +916,6 @@ enum iavf_status iavf_validate_mac_addr(u8 *mac_addr)
}
/**
- * iavf_aq_rx_ctl_read_register - use FW to read from an Rx control register
- * @hw: pointer to the hw struct
- * @reg_addr: register address
- * @reg_val: ptr to register value
- * @cmd_details: pointer to command details structure or NULL
- *
- * Use the firmware to read the Rx control register,
- * especially useful if the Rx unit is under heavy pressure
- **/
-enum iavf_status iavf_aq_rx_ctl_read_register(struct iavf_hw *hw,
- u32 reg_addr, u32 *reg_val,
- struct iavf_asq_cmd_details *cmd_details)
-{
- struct iavf_aq_desc desc;
- struct iavf_aqc_rx_ctl_reg_read_write *cmd_resp =
- (struct iavf_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
- enum iavf_status status;
-
- if (reg_val == NULL)
- return IAVF_ERR_PARAM;
-
- iavf_fill_default_direct_cmd_desc(&desc, iavf_aqc_opc_rx_ctl_reg_read);
-
- cmd_resp->address = CPU_TO_LE32(reg_addr);
-
- status = iavf_asq_send_command(hw, &desc, NULL, 0, cmd_details);
-
- if (status == IAVF_SUCCESS)
- *reg_val = LE32_TO_CPU(cmd_resp->value);
-
- return status;
-}
-
-/**
- * iavf_read_rx_ctl - read from an Rx control register
- * @hw: pointer to the hw struct
- * @reg_addr: register address
- **/
-u32 iavf_read_rx_ctl(struct iavf_hw *hw, u32 reg_addr)
-{
- enum iavf_status status = IAVF_SUCCESS;
- bool use_register;
- int retry = 5;
- u32 val = 0;
-
- use_register = (((hw->aq.api_maj_ver == 1) &&
- (hw->aq.api_min_ver < 5)) ||
- (hw->mac.type == IAVF_MAC_X722));
- if (!use_register) {
-do_retry:
- status = iavf_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
- if (hw->aq.asq_last_status == IAVF_AQ_RC_EAGAIN && retry) {
- iavf_msec_delay(1);
- retry--;
- goto do_retry;
- }
- }
-
- /* if the AQ access failed, try the old-fashioned way */
- if (status || use_register)
- val = rd32(hw, reg_addr);
-
- return val;
-}
-
-/**
- * iavf_aq_rx_ctl_write_register
- * @hw: pointer to the hw struct
- * @reg_addr: register address
- * @reg_val: register value
- * @cmd_details: pointer to command details structure or NULL
- *
- * Use the firmware to write to an Rx control register,
- * especially useful if the Rx unit is under heavy pressure
- **/
-enum iavf_status iavf_aq_rx_ctl_write_register(struct iavf_hw *hw,
- u32 reg_addr, u32 reg_val,
- struct iavf_asq_cmd_details *cmd_details)
-{
- struct iavf_aq_desc desc;
- struct iavf_aqc_rx_ctl_reg_read_write *cmd =
- (struct iavf_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
- enum iavf_status status;
-
- iavf_fill_default_direct_cmd_desc(&desc, iavf_aqc_opc_rx_ctl_reg_write);
-
- cmd->address = CPU_TO_LE32(reg_addr);
- cmd->value = CPU_TO_LE32(reg_val);
-
- status = iavf_asq_send_command(hw, &desc, NULL, 0, cmd_details);
-
- return status;
-}
-
-/**
- * iavf_write_rx_ctl - write to an Rx control register
- * @hw: pointer to the hw struct
- * @reg_addr: register address
- * @reg_val: register value
- **/
-void iavf_write_rx_ctl(struct iavf_hw *hw, u32 reg_addr, u32 reg_val)
-{
- enum iavf_status status = IAVF_SUCCESS;
- bool use_register;
- int retry = 5;
-
- use_register = (((hw->aq.api_maj_ver == 1) &&
- (hw->aq.api_min_ver < 5)) ||
- (hw->mac.type == IAVF_MAC_X722));
- if (!use_register) {
-do_retry:
- status = iavf_aq_rx_ctl_write_register(hw, reg_addr,
- reg_val, NULL);
- if (hw->aq.asq_last_status == IAVF_AQ_RC_EAGAIN && retry) {
- iavf_msec_delay(1);
- retry--;
- goto do_retry;
- }
- }
-
- /* if the AQ access failed, try the old-fashioned way */
- if (status || use_register)
- wr32(hw, reg_addr, reg_val);
-}
-
-/**
- * iavf_aq_set_phy_register
- * @hw: pointer to the hw struct
- * @phy_select: select which phy should be accessed
- * @dev_addr: PHY device address
- * @reg_addr: PHY register address
- * @reg_val: new register value
- * @cmd_details: pointer to command details structure or NULL
- *
- * Write the external PHY register.
- **/
-enum iavf_status iavf_aq_set_phy_register(struct iavf_hw *hw,
- u8 phy_select, u8 dev_addr,
- u32 reg_addr, u32 reg_val,
- struct iavf_asq_cmd_details *cmd_details)
-{
- struct iavf_aq_desc desc;
- struct iavf_aqc_phy_register_access *cmd =
- (struct iavf_aqc_phy_register_access *)&desc.params.raw;
- enum iavf_status status;
-
- iavf_fill_default_direct_cmd_desc(&desc,
- iavf_aqc_opc_set_phy_register);
-
- cmd->phy_interface = phy_select;
- cmd->dev_addres = dev_addr;
- cmd->reg_address = CPU_TO_LE32(reg_addr);
- cmd->reg_value = CPU_TO_LE32(reg_val);
-
- status = iavf_asq_send_command(hw, &desc, NULL, 0, cmd_details);
-
- return status;
-}
-
-/**
- * iavf_aq_get_phy_register
- * @hw: pointer to the hw struct
- * @phy_select: select which phy should be accessed
- * @dev_addr: PHY device address
- * @reg_addr: PHY register address
- * @reg_val: read register value
- * @cmd_details: pointer to command details structure or NULL
- *
- * Read the external PHY register.
- **/
-enum iavf_status iavf_aq_get_phy_register(struct iavf_hw *hw,
- u8 phy_select, u8 dev_addr,
- u32 reg_addr, u32 *reg_val,
- struct iavf_asq_cmd_details *cmd_details)
-{
- struct iavf_aq_desc desc;
- struct iavf_aqc_phy_register_access *cmd =
- (struct iavf_aqc_phy_register_access *)&desc.params.raw;
- enum iavf_status status;
-
- iavf_fill_default_direct_cmd_desc(&desc,
- iavf_aqc_opc_get_phy_register);
-
- cmd->phy_interface = phy_select;
- cmd->dev_addres = dev_addr;
- cmd->reg_address = CPU_TO_LE32(reg_addr);
-
- status = iavf_asq_send_command(hw, &desc, NULL, 0, cmd_details);
- if (!status)
- *reg_val = LE32_TO_CPU(cmd->reg_value);
-
- return status;
-}
-
-
-/**
* iavf_aq_send_msg_to_pf
* @hw: pointer to the hardware structure
* @v_opcode: opcodes for VF-PF communication
@@ -1178,8 +981,6 @@ void iavf_parse_hw_config(struct iavf_hw *hw,
hw->dev_caps.num_msix_vectors_vf = msg->max_vectors;
hw->dev_caps.dcb = msg->vf_cap_flags &
VIRTCHNL_VF_OFFLOAD_L2;
- hw->dev_caps.iwarp = (msg->vf_cap_flags &
- VIRTCHNL_VF_OFFLOAD_IWARP) ? 1 : 0;
for (i = 0; i < msg->num_vsis; i++) {
if (vsi_res->vsi_type == VIRTCHNL_VSI_SRIOV) {
iavf_memcpy(hw->mac.perm_addr,
@@ -1209,174 +1010,6 @@ enum iavf_status iavf_reset(struct iavf_hw *hw)
}
/**
- * iavf_aq_set_arp_proxy_config
- * @hw: pointer to the HW structure
- * @proxy_config: pointer to proxy config command table struct
- * @cmd_details: pointer to command details
- *
- * Set ARP offload parameters from pre-populated
- * iavf_aqc_arp_proxy_data struct
- **/
-enum iavf_status iavf_aq_set_arp_proxy_config(struct iavf_hw *hw,
- struct iavf_aqc_arp_proxy_data *proxy_config,
- struct iavf_asq_cmd_details *cmd_details)
-{
- struct iavf_aq_desc desc;
- enum iavf_status status;
-
- if (!proxy_config)
- return IAVF_ERR_PARAM;
-
- iavf_fill_default_direct_cmd_desc(&desc, iavf_aqc_opc_set_proxy_config);
-
- desc.flags |= CPU_TO_LE16((u16)IAVF_AQ_FLAG_BUF);
- desc.flags |= CPU_TO_LE16((u16)IAVF_AQ_FLAG_RD);
- desc.params.external.addr_high =
- CPU_TO_LE32(IAVF_HI_DWORD((u64)proxy_config));
- desc.params.external.addr_low =
- CPU_TO_LE32(IAVF_LO_DWORD((u64)proxy_config));
- desc.datalen = CPU_TO_LE16(sizeof(struct iavf_aqc_arp_proxy_data));
-
- status = iavf_asq_send_command(hw, &desc, proxy_config,
- sizeof(struct iavf_aqc_arp_proxy_data),
- cmd_details);
-
- return status;
-}
-
-/**
- * iavf_aq_opc_set_ns_proxy_table_entry
- * @hw: pointer to the HW structure
- * @ns_proxy_table_entry: pointer to NS table entry command struct
- * @cmd_details: pointer to command details
- *
- * Set IPv6 Neighbor Solicitation (NS) protocol offload parameters
- * from pre-populated iavf_aqc_ns_proxy_data struct
- **/
-enum iavf_status iavf_aq_set_ns_proxy_table_entry(struct iavf_hw *hw,
- struct iavf_aqc_ns_proxy_data *ns_proxy_table_entry,
- struct iavf_asq_cmd_details *cmd_details)
-{
- struct iavf_aq_desc desc;
- enum iavf_status status;
-
- if (!ns_proxy_table_entry)
- return IAVF_ERR_PARAM;
-
- iavf_fill_default_direct_cmd_desc(&desc,
- iavf_aqc_opc_set_ns_proxy_table_entry);
-
- desc.flags |= CPU_TO_LE16((u16)IAVF_AQ_FLAG_BUF);
- desc.flags |= CPU_TO_LE16((u16)IAVF_AQ_FLAG_RD);
- desc.params.external.addr_high =
- CPU_TO_LE32(IAVF_HI_DWORD((u64)ns_proxy_table_entry));
- desc.params.external.addr_low =
- CPU_TO_LE32(IAVF_LO_DWORD((u64)ns_proxy_table_entry));
- desc.datalen = CPU_TO_LE16(sizeof(struct iavf_aqc_ns_proxy_data));
-
- status = iavf_asq_send_command(hw, &desc, ns_proxy_table_entry,
- sizeof(struct iavf_aqc_ns_proxy_data),
- cmd_details);
-
- return status;
-}
-
-/**
- * iavf_aq_set_clear_wol_filter
- * @hw: pointer to the hw struct
- * @filter_index: index of filter to modify (0-7)
- * @filter: buffer containing filter to be set
- * @set_filter: true to set filter, false to clear filter
- * @no_wol_tco: if true, pass through packets cannot cause wake-up
- * if false, pass through packets may cause wake-up
- * @filter_valid: true if filter action is valid
- * @no_wol_tco_valid: true if no WoL in TCO traffic action valid
- * @cmd_details: pointer to command details structure or NULL
- *
- * Set or clear WoL filter for port attached to the PF
- **/
-enum iavf_status iavf_aq_set_clear_wol_filter(struct iavf_hw *hw,
- u8 filter_index,
- struct iavf_aqc_set_wol_filter_data *filter,
- bool set_filter, bool no_wol_tco,
- bool filter_valid, bool no_wol_tco_valid,
- struct iavf_asq_cmd_details *cmd_details)
-{
- struct iavf_aq_desc desc;
- struct iavf_aqc_set_wol_filter *cmd =
- (struct iavf_aqc_set_wol_filter *)&desc.params.raw;
- enum iavf_status status;
- u16 cmd_flags = 0;
- u16 valid_flags = 0;
- u16 buff_len = 0;
-
- iavf_fill_default_direct_cmd_desc(&desc, iavf_aqc_opc_set_wol_filter);
-
- if (filter_index >= IAVF_AQC_MAX_NUM_WOL_FILTERS)
- return IAVF_ERR_PARAM;
- cmd->filter_index = CPU_TO_LE16(filter_index);
-
- if (set_filter) {
- if (!filter)
- return IAVF_ERR_PARAM;
-
- cmd_flags |= IAVF_AQC_SET_WOL_FILTER;
- cmd_flags |= IAVF_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR;
- }
-
- if (no_wol_tco)
- cmd_flags |= IAVF_AQC_SET_WOL_FILTER_NO_TCO_WOL;
- cmd->cmd_flags = CPU_TO_LE16(cmd_flags);
-
- if (filter_valid)
- valid_flags |= IAVF_AQC_SET_WOL_FILTER_ACTION_VALID;
- if (no_wol_tco_valid)
- valid_flags |= IAVF_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID;
- cmd->valid_flags = CPU_TO_LE16(valid_flags);
-
- buff_len = sizeof(*filter);
- desc.datalen = CPU_TO_LE16(buff_len);
-
- desc.flags |= CPU_TO_LE16((u16)IAVF_AQ_FLAG_BUF);
- desc.flags |= CPU_TO_LE16((u16)IAVF_AQ_FLAG_RD);
-
- cmd->address_high = CPU_TO_LE32(IAVF_HI_DWORD((u64)filter));
- cmd->address_low = CPU_TO_LE32(IAVF_LO_DWORD((u64)filter));
-
- status = iavf_asq_send_command(hw, &desc, filter,
- buff_len, cmd_details);
-
- return status;
-}
-
-/**
- * iavf_aq_get_wake_event_reason
- * @hw: pointer to the hw struct
- * @wake_reason: return value, index of matching filter
- * @cmd_details: pointer to command details structure or NULL
- *
- * Get information for the reason of a Wake Up event
- **/
-enum iavf_status iavf_aq_get_wake_event_reason(struct iavf_hw *hw,
- u16 *wake_reason,
- struct iavf_asq_cmd_details *cmd_details)
-{
- struct iavf_aq_desc desc;
- struct iavf_aqc_get_wake_reason_completion *resp =
- (struct iavf_aqc_get_wake_reason_completion *)&desc.params.raw;
- enum iavf_status status;
-
- iavf_fill_default_direct_cmd_desc(&desc, iavf_aqc_opc_get_wake_reason);
-
- status = iavf_asq_send_command(hw, &desc, NULL, 0, cmd_details);
-
- if (status == IAVF_SUCCESS)
- *wake_reason = LE16_TO_CPU(resp->wake_reason);
-
- return status;
-}
-
-/**
* iavf_aq_clear_all_wol_filters
* @hw: pointer to the hw struct
* @cmd_details: pointer to command details structure or NULL
@@ -1396,423 +1029,3 @@ enum iavf_status iavf_aq_clear_all_wol_filters(struct iavf_hw *hw,
return status;
}
-
-/**
- * iavf_aq_write_ddp - Write dynamic device personalization (ddp)
- * @hw: pointer to the hw struct
- * @buff: command buffer (size in bytes = buff_size)
- * @buff_size: buffer size in bytes
- * @track_id: package tracking id
- * @error_offset: returns error offset
- * @error_info: returns error information
- * @cmd_details: pointer to command details structure or NULL
- **/
-enum
-iavf_status iavf_aq_write_ddp(struct iavf_hw *hw, void *buff,
- u16 buff_size, u32 track_id,
- u32 *error_offset, u32 *error_info,
- struct iavf_asq_cmd_details *cmd_details)
-{
- struct iavf_aq_desc desc;
- struct iavf_aqc_write_personalization_profile *cmd =
- (struct iavf_aqc_write_personalization_profile *)
- &desc.params.raw;
- struct iavf_aqc_write_ddp_resp *resp;
- enum iavf_status status;
-
- iavf_fill_default_direct_cmd_desc(&desc,
- iavf_aqc_opc_write_personalization_profile);
-
- desc.flags |= CPU_TO_LE16(IAVF_AQ_FLAG_BUF | IAVF_AQ_FLAG_RD);
- if (buff_size > IAVF_AQ_LARGE_BUF)
- desc.flags |= CPU_TO_LE16((u16)IAVF_AQ_FLAG_LB);
-
- desc.datalen = CPU_TO_LE16(buff_size);
-
- cmd->profile_track_id = CPU_TO_LE32(track_id);
-
- status = iavf_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
- if (!status) {
- resp = (struct iavf_aqc_write_ddp_resp *)&desc.params.raw;
- if (error_offset)
- *error_offset = LE32_TO_CPU(resp->error_offset);
- if (error_info)
- *error_info = LE32_TO_CPU(resp->error_info);
- }
-
- return status;
-}
-
-/**
- * iavf_aq_get_ddp_list - Read dynamic device personalization (ddp)
- * @hw: pointer to the hw struct
- * @buff: command buffer (size in bytes = buff_size)
- * @buff_size: buffer size in bytes
- * @flags: AdminQ command flags
- * @cmd_details: pointer to command details structure or NULL
- **/
-enum
-iavf_status iavf_aq_get_ddp_list(struct iavf_hw *hw, void *buff,
- u16 buff_size, u8 flags,
- struct iavf_asq_cmd_details *cmd_details)
-{
- struct iavf_aq_desc desc;
- struct iavf_aqc_get_applied_profiles *cmd =
- (struct iavf_aqc_get_applied_profiles *)&desc.params.raw;
- enum iavf_status status;
-
- iavf_fill_default_direct_cmd_desc(&desc,
- iavf_aqc_opc_get_personalization_profile_list);
-
- desc.flags |= CPU_TO_LE16((u16)IAVF_AQ_FLAG_BUF);
- if (buff_size > IAVF_AQ_LARGE_BUF)
- desc.flags |= CPU_TO_LE16((u16)IAVF_AQ_FLAG_LB);
- desc.datalen = CPU_TO_LE16(buff_size);
-
- cmd->flags = flags;
-
- status = iavf_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
-
- return status;
-}
-
-/**
- * iavf_find_segment_in_package
- * @segment_type: the segment type to search for (i.e., SEGMENT_TYPE_IAVF)
- * @pkg_hdr: pointer to the package header to be searched
- *
- * This function searches a package file for a particular segment type. On
- * success it returns a pointer to the segment header, otherwise it will
- * return NULL.
- **/
-struct iavf_generic_seg_header *
-iavf_find_segment_in_package(u32 segment_type,
- struct iavf_package_header *pkg_hdr)
-{
- struct iavf_generic_seg_header *segment;
- u32 i;
-
- /* Search all package segments for the requested segment type */
- for (i = 0; i < pkg_hdr->segment_count; i++) {
- segment =
- (struct iavf_generic_seg_header *)((u8 *)pkg_hdr +
- pkg_hdr->segment_offset[i]);
-
- if (segment->type == segment_type)
- return segment;
- }
-
- return NULL;
-}
-
-/* Get section table in profile */
-#define IAVF_SECTION_TABLE(profile, sec_tbl) \
- do { \
- struct iavf_profile_segment *p = (profile); \
- u32 count; \
- u32 *nvm; \
- count = p->device_table_count; \
- nvm = (u32 *)&p->device_table[count]; \
- sec_tbl = (struct iavf_section_table *)&nvm[nvm[0] + 1]; \
- } while (0)
-
-/* Get section header in profile */
-#define IAVF_SECTION_HEADER(profile, offset) \
- (struct iavf_profile_section_header *)((u8 *)(profile) + (offset))
-
-/**
- * iavf_find_section_in_profile
- * @section_type: the section type to search for (i.e., SECTION_TYPE_NOTE)
- * @profile: pointer to the iavf segment header to be searched
- *
- * This function searches iavf segment for a particular section type. On
- * success it returns a pointer to the section header, otherwise it will
- * return NULL.
- **/
-struct iavf_profile_section_header *
-iavf_find_section_in_profile(u32 section_type,
- struct iavf_profile_segment *profile)
-{
- struct iavf_profile_section_header *sec;
- struct iavf_section_table *sec_tbl;
- u32 sec_off;
- u32 i;
-
- if (profile->header.type != SEGMENT_TYPE_IAVF)
- return NULL;
-
- IAVF_SECTION_TABLE(profile, sec_tbl);
-
- for (i = 0; i < sec_tbl->section_count; i++) {
- sec_off = sec_tbl->section_offset[i];
- sec = IAVF_SECTION_HEADER(profile, sec_off);
- if (sec->section.type == section_type)
- return sec;
- }
-
- return NULL;
-}
-
-/**
- * iavf_ddp_exec_aq_section - Execute generic AQ for DDP
- * @hw: pointer to the hw struct
- * @aq: command buffer containing all data to execute AQ
- **/
-STATIC enum
-iavf_status iavf_ddp_exec_aq_section(struct iavf_hw *hw,
- struct iavf_profile_aq_section *aq)
-{
- enum iavf_status status;
- struct iavf_aq_desc desc;
- u8 *msg = NULL;
- u16 msglen;
-
- iavf_fill_default_direct_cmd_desc(&desc, aq->opcode);
- desc.flags |= CPU_TO_LE16(aq->flags);
- iavf_memcpy(desc.params.raw, aq->param, sizeof(desc.params.raw),
- IAVF_NONDMA_TO_NONDMA);
-
- msglen = aq->datalen;
- if (msglen) {
- desc.flags |= CPU_TO_LE16((u16)(IAVF_AQ_FLAG_BUF |
- IAVF_AQ_FLAG_RD));
- if (msglen > IAVF_AQ_LARGE_BUF)
- desc.flags |= CPU_TO_LE16((u16)IAVF_AQ_FLAG_LB);
- desc.datalen = CPU_TO_LE16(msglen);
- msg = &aq->data[0];
- }
-
- status = iavf_asq_send_command(hw, &desc, msg, msglen, NULL);
-
- if (status != IAVF_SUCCESS) {
- iavf_debug(hw, IAVF_DEBUG_PACKAGE,
- "unable to exec DDP AQ opcode %u, error %d\n",
- aq->opcode, status);
- return status;
- }
-
- /* copy returned desc to aq_buf */
- iavf_memcpy(aq->param, desc.params.raw, sizeof(desc.params.raw),
- IAVF_NONDMA_TO_NONDMA);
-
- return IAVF_SUCCESS;
-}
-
-/**
- * iavf_validate_profile
- * @hw: pointer to the hardware structure
- * @profile: pointer to the profile segment of the package to be validated
- * @track_id: package tracking id
- * @rollback: flag if the profile is for rollback.
- *
- * Validates supported devices and profile's sections.
- */
-STATIC enum iavf_status
-iavf_validate_profile(struct iavf_hw *hw, struct iavf_profile_segment *profile,
- u32 track_id, bool rollback)
-{
- struct iavf_profile_section_header *sec = NULL;
- enum iavf_status status = IAVF_SUCCESS;
- struct iavf_section_table *sec_tbl;
- u32 vendor_dev_id;
- u32 dev_cnt;
- u32 sec_off;
- u32 i;
-
- if (track_id == IAVF_DDP_TRACKID_INVALID) {
- iavf_debug(hw, IAVF_DEBUG_PACKAGE, "Invalid track_id\n");
- return IAVF_NOT_SUPPORTED;
- }
-
- dev_cnt = profile->device_table_count;
- for (i = 0; i < dev_cnt; i++) {
- vendor_dev_id = profile->device_table[i].vendor_dev_id;
- if ((vendor_dev_id >> 16) == IAVF_INTEL_VENDOR_ID &&
- hw->device_id == (vendor_dev_id & 0xFFFF))
- break;
- }
- if (dev_cnt && (i == dev_cnt)) {
- iavf_debug(hw, IAVF_DEBUG_PACKAGE,
- "Device doesn't support DDP\n");
- return IAVF_ERR_DEVICE_NOT_SUPPORTED;
- }
-
- IAVF_SECTION_TABLE(profile, sec_tbl);
-
- /* Validate sections types */
- for (i = 0; i < sec_tbl->section_count; i++) {
- sec_off = sec_tbl->section_offset[i];
- sec = IAVF_SECTION_HEADER(profile, sec_off);
- if (rollback) {
- if (sec->section.type == SECTION_TYPE_MMIO ||
- sec->section.type == SECTION_TYPE_AQ ||
- sec->section.type == SECTION_TYPE_RB_AQ) {
- iavf_debug(hw, IAVF_DEBUG_PACKAGE,
- "Not a roll-back package\n");
- return IAVF_NOT_SUPPORTED;
- }
- } else {
- if (sec->section.type == SECTION_TYPE_RB_AQ ||
- sec->section.type == SECTION_TYPE_RB_MMIO) {
- iavf_debug(hw, IAVF_DEBUG_PACKAGE,
- "Not an original package\n");
- return IAVF_NOT_SUPPORTED;
- }
- }
- }
-
- return status;
-}
-
-/**
- * iavf_write_profile
- * @hw: pointer to the hardware structure
- * @profile: pointer to the profile segment of the package to be downloaded
- * @track_id: package tracking id
- *
- * Handles the download of a complete package.
- */
-enum iavf_status
-iavf_write_profile(struct iavf_hw *hw, struct iavf_profile_segment *profile,
- u32 track_id)
-{
- enum iavf_status status = IAVF_SUCCESS;
- struct iavf_section_table *sec_tbl;
- struct iavf_profile_section_header *sec = NULL;
- struct iavf_profile_aq_section *ddp_aq;
- u32 section_size = 0;
- u32 offset = 0, info = 0;
- u32 sec_off;
- u32 i;
-
- status = iavf_validate_profile(hw, profile, track_id, false);
- if (status)
- return status;
-
- IAVF_SECTION_TABLE(profile, sec_tbl);
-
- for (i = 0; i < sec_tbl->section_count; i++) {
- sec_off = sec_tbl->section_offset[i];
- sec = IAVF_SECTION_HEADER(profile, sec_off);
- /* Process generic admin command */
- if (sec->section.type == SECTION_TYPE_AQ) {
- ddp_aq = (struct iavf_profile_aq_section *)&sec[1];
- status = iavf_ddp_exec_aq_section(hw, ddp_aq);
- if (status) {
- iavf_debug(hw, IAVF_DEBUG_PACKAGE,
- "Failed to execute aq: section %d, opcode %u\n",
- i, ddp_aq->opcode);
- break;
- }
- sec->section.type = SECTION_TYPE_RB_AQ;
- }
-
- /* Skip any non-mmio sections */
- if (sec->section.type != SECTION_TYPE_MMIO)
- continue;
-
- section_size = sec->section.size +
- sizeof(struct iavf_profile_section_header);
-
- /* Write MMIO section */
- status = iavf_aq_write_ddp(hw, (void *)sec, (u16)section_size,
- track_id, &offset, &info, NULL);
- if (status) {
- iavf_debug(hw, IAVF_DEBUG_PACKAGE,
- "Failed to write profile: section %d, offset %d, info %d\n",
- i, offset, info);
- break;
- }
- }
- return status;
-}
-
-/**
- * iavf_rollback_profile
- * @hw: pointer to the hardware structure
- * @profile: pointer to the profile segment of the package to be removed
- * @track_id: package tracking id
- *
- * Rolls back previously loaded package.
- */
-enum iavf_status
-iavf_rollback_profile(struct iavf_hw *hw, struct iavf_profile_segment *profile,
- u32 track_id)
-{
- struct iavf_profile_section_header *sec = NULL;
- enum iavf_status status = IAVF_SUCCESS;
- struct iavf_section_table *sec_tbl;
- u32 offset = 0, info = 0;
- u32 section_size = 0;
- u32 sec_off;
- int i;
-
- status = iavf_validate_profile(hw, profile, track_id, true);
- if (status)
- return status;
-
- IAVF_SECTION_TABLE(profile, sec_tbl);
-
- /* For rollback write sections in reverse */
- for (i = sec_tbl->section_count - 1; i >= 0; i--) {
- sec_off = sec_tbl->section_offset[i];
- sec = IAVF_SECTION_HEADER(profile, sec_off);
-
- /* Skip any non-rollback sections */
- if (sec->section.type != SECTION_TYPE_RB_MMIO)
- continue;
-
- section_size = sec->section.size +
- sizeof(struct iavf_profile_section_header);
-
- /* Write roll-back MMIO section */
- status = iavf_aq_write_ddp(hw, (void *)sec, (u16)section_size,
- track_id, &offset, &info, NULL);
- if (status) {
- iavf_debug(hw, IAVF_DEBUG_PACKAGE,
- "Failed to write profile: section %d, offset %d, info %d\n",
- i, offset, info);
- break;
- }
- }
- return status;
-}
-
-/**
- * iavf_add_pinfo_to_list
- * @hw: pointer to the hardware structure
- * @profile: pointer to the profile segment of the package
- * @profile_info_sec: buffer for information section
- * @track_id: package tracking id
- *
- * Register a profile to the list of loaded profiles.
- */
-enum iavf_status
-iavf_add_pinfo_to_list(struct iavf_hw *hw,
- struct iavf_profile_segment *profile,
- u8 *profile_info_sec, u32 track_id)
-{
- enum iavf_status status = IAVF_SUCCESS;
- struct iavf_profile_section_header *sec = NULL;
- struct iavf_profile_info *pinfo;
- u32 offset = 0, info = 0;
-
- sec = (struct iavf_profile_section_header *)profile_info_sec;
- sec->tbl_size = 1;
- sec->data_end = sizeof(struct iavf_profile_section_header) +
- sizeof(struct iavf_profile_info);
- sec->section.type = SECTION_TYPE_INFO;
- sec->section.offset = sizeof(struct iavf_profile_section_header);
- sec->section.size = sizeof(struct iavf_profile_info);
- pinfo = (struct iavf_profile_info *)(profile_info_sec +
- sec->section.offset);
- pinfo->track_id = track_id;
- pinfo->version = profile->version;
- pinfo->op = IAVF_DDP_ADD_TRACKID;
- iavf_memcpy(pinfo->name, profile->name, IAVF_DDP_NAME_SIZE,
- IAVF_NONDMA_TO_NONDMA);
-
- status = iavf_aq_write_ddp(hw, (void *)sec, sec->data_end,
- track_id, &offset, &info, NULL);
- return status;
-}
diff --git a/drivers/net/iavf/base/iavf_prototype.h b/drivers/net/iavf/base/iavf_prototype.h
index 4b428b8d9..5b61b43d9 100644
--- a/drivers/net/iavf/base/iavf_prototype.h
+++ b/drivers/net/iavf/base/iavf_prototype.h
@@ -61,7 +61,6 @@ enum iavf_status iavf_aq_set_rss_key(struct iavf_hw *hw,
const char *iavf_aq_str(struct iavf_hw *hw, enum iavf_admin_queue_err aq_err);
const char *iavf_stat_str(struct iavf_hw *hw, enum iavf_status stat_err);
-
enum iavf_status iavf_set_mac_type(struct iavf_hw *hw);
extern struct iavf_rx_ptype_decoded iavf_ptype_lookup[];
@@ -77,7 +76,6 @@ void iavf_acquire_spinlock(struct iavf_spinlock *sp);
void iavf_release_spinlock(struct iavf_spinlock *sp);
void iavf_destroy_spinlock(struct iavf_spinlock *sp);
-/* iavf_common for VF drivers*/
void iavf_parse_hw_config(struct iavf_hw *hw,
struct virtchnl_vf_resource *msg);
enum iavf_status iavf_reset(struct iavf_hw *hw);
@@ -86,92 +84,11 @@ enum iavf_status iavf_aq_send_msg_to_pf(struct iavf_hw *hw,
enum iavf_status v_retval,
u8 *msg, u16 msglen,
struct iavf_asq_cmd_details *cmd_details);
-enum iavf_status iavf_set_filter_control(struct iavf_hw *hw,
- struct iavf_filter_control_settings *settings);
-enum iavf_status iavf_aq_add_rem_control_packet_filter(struct iavf_hw *hw,
- u8 *mac_addr, u16 ethtype, u16 flags,
- u16 vsi_seid, u16 queue, bool is_add,
- struct iavf_control_filter_stats *stats,
- struct iavf_asq_cmd_details *cmd_details);
enum iavf_status iavf_aq_debug_dump(struct iavf_hw *hw, u8 cluster_id,
u8 table_id, u32 start_index, u16 buff_size,
void *buff, u16 *ret_buff_size,
u8 *ret_next_table, u32 *ret_next_index,
struct iavf_asq_cmd_details *cmd_details);
-void iavf_add_filter_to_drop_tx_flow_control_frames(struct iavf_hw *hw,
- u16 vsi_seid);
-enum iavf_status iavf_aq_rx_ctl_read_register(struct iavf_hw *hw,
- u32 reg_addr, u32 *reg_val,
- struct iavf_asq_cmd_details *cmd_details);
-u32 iavf_read_rx_ctl(struct iavf_hw *hw, u32 reg_addr);
-enum iavf_status iavf_aq_rx_ctl_write_register(struct iavf_hw *hw,
- u32 reg_addr, u32 reg_val,
- struct iavf_asq_cmd_details *cmd_details);
-void iavf_write_rx_ctl(struct iavf_hw *hw, u32 reg_addr, u32 reg_val);
-enum iavf_status iavf_aq_set_phy_register(struct iavf_hw *hw,
- u8 phy_select, u8 dev_addr,
- u32 reg_addr, u32 reg_val,
- struct iavf_asq_cmd_details *cmd_details);
-enum iavf_status iavf_aq_get_phy_register(struct iavf_hw *hw,
- u8 phy_select, u8 dev_addr,
- u32 reg_addr, u32 *reg_val,
- struct iavf_asq_cmd_details *cmd_details);
-
-enum iavf_status iavf_aq_set_arp_proxy_config(struct iavf_hw *hw,
- struct iavf_aqc_arp_proxy_data *proxy_config,
- struct iavf_asq_cmd_details *cmd_details);
-enum iavf_status iavf_aq_set_ns_proxy_table_entry(struct iavf_hw *hw,
- struct iavf_aqc_ns_proxy_data *ns_proxy_table_entry,
- struct iavf_asq_cmd_details *cmd_details);
-enum iavf_status iavf_aq_set_clear_wol_filter(struct iavf_hw *hw,
- u8 filter_index,
- struct iavf_aqc_set_wol_filter_data *filter,
- bool set_filter, bool no_wol_tco,
- bool filter_valid, bool no_wol_tco_valid,
- struct iavf_asq_cmd_details *cmd_details);
-enum iavf_status iavf_aq_get_wake_event_reason(struct iavf_hw *hw,
- u16 *wake_reason,
- struct iavf_asq_cmd_details *cmd_details);
enum iavf_status iavf_aq_clear_all_wol_filters(struct iavf_hw *hw,
struct iavf_asq_cmd_details *cmd_details);
-enum iavf_status iavf_read_phy_register_clause22(struct iavf_hw *hw,
- u16 reg, u8 phy_addr, u16 *value);
-enum iavf_status iavf_write_phy_register_clause22(struct iavf_hw *hw,
- u16 reg, u8 phy_addr, u16 value);
-enum iavf_status iavf_read_phy_register_clause45(struct iavf_hw *hw,
- u8 page, u16 reg, u8 phy_addr, u16 *value);
-enum iavf_status iavf_write_phy_register_clause45(struct iavf_hw *hw,
- u8 page, u16 reg, u8 phy_addr, u16 value);
-enum iavf_status iavf_read_phy_register(struct iavf_hw *hw,
- u8 page, u16 reg, u8 phy_addr, u16 *value);
-enum iavf_status iavf_write_phy_register(struct iavf_hw *hw,
- u8 page, u16 reg, u8 phy_addr, u16 value);
-u8 iavf_get_phy_address(struct iavf_hw *hw, u8 dev_num);
-enum iavf_status iavf_blink_phy_link_led(struct iavf_hw *hw,
- u32 time, u32 interval);
-enum iavf_status iavf_aq_write_ddp(struct iavf_hw *hw, void *buff,
- u16 buff_size, u32 track_id,
- u32 *error_offset, u32 *error_info,
- struct iavf_asq_cmd_details *
- cmd_details);
-enum iavf_status iavf_aq_get_ddp_list(struct iavf_hw *hw, void *buff,
- u16 buff_size, u8 flags,
- struct iavf_asq_cmd_details *
- cmd_details);
-struct iavf_generic_seg_header *
-iavf_find_segment_in_package(u32 segment_type,
- struct iavf_package_header *pkg_header);
-struct iavf_profile_section_header *
-iavf_find_section_in_profile(u32 section_type,
- struct iavf_profile_segment *profile);
-enum iavf_status
-iavf_write_profile(struct iavf_hw *hw, struct iavf_profile_segment *iavf_seg,
- u32 track_id);
-enum iavf_status
-iavf_rollback_profile(struct iavf_hw *hw, struct iavf_profile_segment *iavf_seg,
- u32 track_id);
-enum iavf_status
-iavf_add_pinfo_to_list(struct iavf_hw *hw,
- struct iavf_profile_segment *profile,
- u8 *profile_info_sec, u32 track_id);
#endif /* _IAVF_PROTOTYPE_H_ */
diff --git a/drivers/net/iavf/base/iavf_type.h b/drivers/net/iavf/base/iavf_type.h
index 4ccde31a2..487352f51 100644
--- a/drivers/net/iavf/base/iavf_type.h
+++ b/drivers/net/iavf/base/iavf_type.h
@@ -29,10 +29,8 @@
#endif /* BIT_ULL */
#endif /* LINUX_MACROS */
-#ifndef IAVF_MASK
/* IAVF_MASK is a macro used on 32 bit registers */
#define IAVF_MASK(mask, shift) (mask << shift)
-#endif
#define IAVF_MAX_PF 16
#define IAVF_MAX_PF_VSI 64
@@ -40,16 +38,10 @@
#define IAVF_MAX_VSI_QP 16
#define IAVF_MAX_VF_VSI 3
#define IAVF_MAX_CHAINED_RX_BUFFERS 5
-#define IAVF_MAX_PF_UDP_OFFLOAD_PORTS 16
/* something less than 1 minute */
#define IAVF_HEARTBEAT_TIMEOUT (HZ * 50)
-/* Max default timeout in ms, */
-#define IAVF_MAX_NVM_TIMEOUT 18000
-
-/* Max timeout in ms for the phy to respond */
-#define IAVF_MAX_PHY_TIMEOUT 500
/* Check whether address is multicast. */
#define IAVF_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01))
@@ -59,8 +51,6 @@
((((u8 *)(address))[0] == ((u8)0xff)) && \
(((u8 *)(address))[1] == ((u8)0xff)))
-/* Switch from ms to the 1usec global time (this is the GTIME resolution) */
-#define IAVF_MS_TO_GTIME(time) ((time) * 1000)
/* forward declaration */
struct iavf_hw;
@@ -190,33 +180,6 @@ enum iavf_mac_type {
IAVF_MAC_GENERIC,
};
-enum iavf_media_type {
- IAVF_MEDIA_TYPE_UNKNOWN = 0,
- IAVF_MEDIA_TYPE_FIBER,
- IAVF_MEDIA_TYPE_BASET,
- IAVF_MEDIA_TYPE_BACKPLANE,
- IAVF_MEDIA_TYPE_CX4,
- IAVF_MEDIA_TYPE_DA,
- IAVF_MEDIA_TYPE_VIRTUAL
-};
-
-enum iavf_fc_mode {
- IAVF_FC_NONE = 0,
- IAVF_FC_RX_PAUSE,
- IAVF_FC_TX_PAUSE,
- IAVF_FC_FULL,
- IAVF_FC_PFC,
- IAVF_FC_DEFAULT
-};
-
-enum iavf_set_fc_aq_failures {
- IAVF_SET_FC_AQ_FAIL_NONE = 0,
- IAVF_SET_FC_AQ_FAIL_GET = 1,
- IAVF_SET_FC_AQ_FAIL_SET = 2,
- IAVF_SET_FC_AQ_FAIL_UPDATE = 4,
- IAVF_SET_FC_AQ_FAIL_SET_UPDATE = 6
-};
-
enum iavf_vsi_type {
IAVF_VSI_MAIN = 0,
IAVF_VSI_VMDQ1 = 1,
@@ -236,99 +199,6 @@ enum iavf_queue_type {
IAVF_QUEUE_TYPE_UNKNOWN
};
-struct iavf_link_status {
- enum iavf_aq_phy_type phy_type;
- enum iavf_aq_link_speed link_speed;
- u8 link_info;
- u8 an_info;
- u8 req_fec_info;
- u8 fec_info;
- u8 ext_info;
- u8 loopback;
- /* is Link Status Event notification to SW enabled */
- bool lse_enable;
- u16 max_frame_size;
- bool crc_enable;
- u8 pacing;
- u8 requested_speeds;
- u8 module_type[3];
- /* 1st byte: module identifier */
-#define IAVF_MODULE_TYPE_SFP 0x03
-#define IAVF_MODULE_TYPE_QSFP 0x0D
- /* 2nd byte: ethernet compliance codes for 10/40G */
-#define IAVF_MODULE_TYPE_40G_ACTIVE 0x01
-#define IAVF_MODULE_TYPE_40G_LR4 0x02
-#define IAVF_MODULE_TYPE_40G_SR4 0x04
-#define IAVF_MODULE_TYPE_40G_CR4 0x08
-#define IAVF_MODULE_TYPE_10G_BASE_SR 0x10
-#define IAVF_MODULE_TYPE_10G_BASE_LR 0x20
-#define IAVF_MODULE_TYPE_10G_BASE_LRM 0x40
-#define IAVF_MODULE_TYPE_10G_BASE_ER 0x80
- /* 3rd byte: ethernet compliance codes for 1G */
-#define IAVF_MODULE_TYPE_1000BASE_SX 0x01
-#define IAVF_MODULE_TYPE_1000BASE_LX 0x02
-#define IAVF_MODULE_TYPE_1000BASE_CX 0x04
-#define IAVF_MODULE_TYPE_1000BASE_T 0x08
-};
-
-struct iavf_phy_info {
- struct iavf_link_status link_info;
- struct iavf_link_status link_info_old;
- bool get_link_info;
- enum iavf_media_type media_type;
- /* all the phy types the NVM is capable of */
- u64 phy_types;
-};
-
-#define IAVF_CAP_PHY_TYPE_SGMII BIT_ULL(IAVF_PHY_TYPE_SGMII)
-#define IAVF_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(IAVF_PHY_TYPE_1000BASE_KX)
-#define IAVF_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(IAVF_PHY_TYPE_10GBASE_KX4)
-#define IAVF_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(IAVF_PHY_TYPE_10GBASE_KR)
-#define IAVF_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(IAVF_PHY_TYPE_40GBASE_KR4)
-#define IAVF_CAP_PHY_TYPE_XAUI BIT_ULL(IAVF_PHY_TYPE_XAUI)
-#define IAVF_CAP_PHY_TYPE_XFI BIT_ULL(IAVF_PHY_TYPE_XFI)
-#define IAVF_CAP_PHY_TYPE_SFI BIT_ULL(IAVF_PHY_TYPE_SFI)
-#define IAVF_CAP_PHY_TYPE_XLAUI BIT_ULL(IAVF_PHY_TYPE_XLAUI)
-#define IAVF_CAP_PHY_TYPE_XLPPI BIT_ULL(IAVF_PHY_TYPE_XLPPI)
-#define IAVF_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(IAVF_PHY_TYPE_40GBASE_CR4_CU)
-#define IAVF_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(IAVF_PHY_TYPE_10GBASE_CR1_CU)
-#define IAVF_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(IAVF_PHY_TYPE_10GBASE_AOC)
-#define IAVF_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(IAVF_PHY_TYPE_40GBASE_AOC)
-#define IAVF_CAP_PHY_TYPE_100BASE_TX BIT_ULL(IAVF_PHY_TYPE_100BASE_TX)
-#define IAVF_CAP_PHY_TYPE_1000BASE_T BIT_ULL(IAVF_PHY_TYPE_1000BASE_T)
-#define IAVF_CAP_PHY_TYPE_10GBASE_T BIT_ULL(IAVF_PHY_TYPE_10GBASE_T)
-#define IAVF_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(IAVF_PHY_TYPE_10GBASE_SR)
-#define IAVF_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(IAVF_PHY_TYPE_10GBASE_LR)
-#define IAVF_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(IAVF_PHY_TYPE_10GBASE_SFPP_CU)
-#define IAVF_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(IAVF_PHY_TYPE_10GBASE_CR1)
-#define IAVF_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(IAVF_PHY_TYPE_40GBASE_CR4)
-#define IAVF_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(IAVF_PHY_TYPE_40GBASE_SR4)
-#define IAVF_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(IAVF_PHY_TYPE_40GBASE_LR4)
-#define IAVF_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(IAVF_PHY_TYPE_1000BASE_SX)
-#define IAVF_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(IAVF_PHY_TYPE_1000BASE_LX)
-#define IAVF_CAP_PHY_TYPE_1000BASE_T_OPTICAL \
- BIT_ULL(IAVF_PHY_TYPE_1000BASE_T_OPTICAL)
-#define IAVF_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(IAVF_PHY_TYPE_20GBASE_KR2)
-/*
- * Defining the macro IAVF_TYPE_OFFSET to implement a bit shift for some
- * PHY types. There is an unused bit (31) in the IAVF_CAP_PHY_TYPE_* bit
- * fields but no corresponding gap in the iavf_aq_phy_type enumeration. So,
- * a shift is needed to adjust for this with values larger than 31. The
- * only affected values are IAVF_PHY_TYPE_25GBASE_*.
- */
-#define IAVF_PHY_TYPE_OFFSET 1
-#define IAVF_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(IAVF_PHY_TYPE_25GBASE_KR + \
- IAVF_PHY_TYPE_OFFSET)
-#define IAVF_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(IAVF_PHY_TYPE_25GBASE_CR + \
- IAVF_PHY_TYPE_OFFSET)
-#define IAVF_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(IAVF_PHY_TYPE_25GBASE_SR + \
- IAVF_PHY_TYPE_OFFSET)
-#define IAVF_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(IAVF_PHY_TYPE_25GBASE_LR + \
- IAVF_PHY_TYPE_OFFSET)
-#define IAVF_CAP_PHY_TYPE_25GBASE_AOC BIT_ULL(IAVF_PHY_TYPE_25GBASE_AOC + \
- IAVF_PHY_TYPE_OFFSET)
-#define IAVF_CAP_PHY_TYPE_25GBASE_ACC BIT_ULL(IAVF_PHY_TYPE_25GBASE_ACC + \
- IAVF_PHY_TYPE_OFFSET)
#define IAVF_HW_CAP_MAX_GPIO 30
#define IAVF_HW_CAP_MDIO_PORT_MODE_MDIO 0
#define IAVF_HW_CAP_MDIO_PORT_MODE_I2C 1
@@ -344,71 +214,24 @@ enum iavf_acpi_programming_method {
/* Capabilities of a PF or a VF or the whole device */
struct iavf_hw_capabilities {
- u32 switch_mode;
-#define IAVF_NVM_IMAGE_TYPE_EVB 0x0
-#define IAVF_NVM_IMAGE_TYPE_CLOUD 0x2
-#define IAVF_NVM_IMAGE_TYPE_UDP_CLOUD 0x3
-
- u32 management_mode;
- u32 mng_protocols_over_mctp;
-#define IAVF_MNG_PROTOCOL_PLDM 0x2
-#define IAVF_MNG_PROTOCOL_OEM_COMMANDS 0x4
-#define IAVF_MNG_PROTOCOL_NCSI 0x8
- u32 npar_enable;
- u32 os2bmc;
- u32 valid_functions;
- bool sr_iov_1_1;
- bool vmdq;
- bool evb_802_1_qbg; /* Edge Virtual Bridging */
- bool evb_802_1_qbh; /* Bridge Port Extension */
+ /* Cloud filter modes:
+ * Mode1: Filter on L4 port only
+ * Mode2: Filter for non-tunneled traffic
+ * Mode3: Filter for tunnel traffic
+ */
+#define IAVF_CLOUD_FILTER_MODE1 0x6
+#define IAVF_CLOUD_FILTER_MODE2 0x7
+#define IAVF_CLOUD_FILTER_MODE3 0x8
+#define IAVF_SWITCH_MODE_MASK 0xF
+
bool dcb;
bool fcoe;
- bool iscsi; /* Indicates iSCSI enabled */
- bool flex10_enable;
- bool flex10_capable;
- u32 flex10_mode;
-#define IAVF_FLEX10_MODE_UNKNOWN 0x0
-#define IAVF_FLEX10_MODE_DCC 0x1
-#define IAVF_FLEX10_MODE_DCI 0x2
-
- u32 flex10_status;
-#define IAVF_FLEX10_STATUS_DCC_ERROR 0x1
-#define IAVF_FLEX10_STATUS_VC_MODE 0x2
-
- bool sec_rev_disabled;
- bool update_disabled;
-#define IAVF_NVM_MGMT_SEC_REV_DISABLED 0x1
-#define IAVF_NVM_MGMT_UPDATE_DISABLED 0x2
-
- bool mgmt_cem;
- bool ieee_1588;
bool iwarp;
- bool fd;
- u32 fd_filters_guaranteed;
- u32 fd_filters_best_effort;
- bool rss;
- u32 rss_table_size;
- u32 rss_table_entry_width;
- bool led[IAVF_HW_CAP_MAX_GPIO];
- bool sdp[IAVF_HW_CAP_MAX_GPIO];
- u32 nvm_image_type;
- u32 num_flow_director_filters;
- u32 num_vfs;
- u32 vf_base_id;
u32 num_vsis;
u32 num_rx_qp;
u32 num_tx_qp;
u32 base_queue;
- u32 num_msix_vectors;
u32 num_msix_vectors_vf;
- u32 led_pin_num;
- u32 sdp_pin_num;
- u32 mdio_port_num;
- u32 mdio_port_mode;
- u8 rx_buf_chain_len;
- u32 enabled_tcmap;
- u32 maxtc;
- u64 wr_csr_prot;
bool apm_wol_support;
enum iavf_acpi_programming_method acpi_prog_method;
bool proxy_support;
@@ -423,107 +246,25 @@ struct iavf_mac_info {
u16 max_fcoeq;
};
-enum iavf_aq_resources_ids {
- IAVF_NVM_RESOURCE_ID = 1
-};
-
-enum iavf_aq_resource_access_type {
- IAVF_RESOURCE_READ = 1,
- IAVF_RESOURCE_WRITE
-};
+#define IAVF_NVM_EXEC_GET_AQ_RESULT 0x0
+#define IAVF_NVM_EXEC_FEATURES 0xe
+#define IAVF_NVM_EXEC_STATUS 0xf
-struct iavf_nvm_info {
- u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
- u32 timeout; /* [ms] */
- u16 sr_size; /* Shadow RAM size in words */
- bool blank_nvm_mode; /* is NVM empty (no FW present)*/
- u16 version; /* NVM package version */
- u32 eetrack; /* NVM data version */
- u32 oem_ver; /* OEM version info */
-};
+/* NVMUpdate features API */
+#define IAVF_NVMUPD_FEATURES_API_VER_MAJOR 0
+#define IAVF_NVMUPD_FEATURES_API_VER_MINOR 14
+#define IAVF_NVMUPD_FEATURES_API_FEATURES_ARRAY_LEN 12
-/* definitions used in NVM update support */
-
-enum iavf_nvmupd_cmd {
- IAVF_NVMUPD_INVALID,
- IAVF_NVMUPD_READ_CON,
- IAVF_NVMUPD_READ_SNT,
- IAVF_NVMUPD_READ_LCB,
- IAVF_NVMUPD_READ_SA,
- IAVF_NVMUPD_WRITE_ERA,
- IAVF_NVMUPD_WRITE_CON,
- IAVF_NVMUPD_WRITE_SNT,
- IAVF_NVMUPD_WRITE_LCB,
- IAVF_NVMUPD_WRITE_SA,
- IAVF_NVMUPD_CSUM_CON,
- IAVF_NVMUPD_CSUM_SA,
- IAVF_NVMUPD_CSUM_LCB,
- IAVF_NVMUPD_STATUS,
- IAVF_NVMUPD_EXEC_AQ,
- IAVF_NVMUPD_GET_AQ_RESULT,
- IAVF_NVMUPD_GET_AQ_EVENT,
-};
-
-enum iavf_nvmupd_state {
- IAVF_NVMUPD_STATE_INIT,
- IAVF_NVMUPD_STATE_READING,
- IAVF_NVMUPD_STATE_WRITING,
- IAVF_NVMUPD_STATE_INIT_WAIT,
- IAVF_NVMUPD_STATE_WRITE_WAIT,
- IAVF_NVMUPD_STATE_ERROR
-};
+#define IAVF_NVMUPD_FEATURE_FLAT_NVM_SUPPORT BIT(0)
-/* nvm_access definition and its masks/shifts need to be accessible to
- * application, core driver, and shared code. Where is the right file?
- */
-#define IAVF_NVM_READ 0xB
-#define IAVF_NVM_WRITE 0xC
-
-#define IAVF_NVM_MOD_PNT_MASK 0xFF
-
-#define IAVF_NVM_TRANS_SHIFT 8
-#define IAVF_NVM_TRANS_MASK (0xf << IAVF_NVM_TRANS_SHIFT)
-#define IAVF_NVM_PRESERVATION_FLAGS_SHIFT 12
-#define IAVF_NVM_PRESERVATION_FLAGS_MASK \
- (0x3 << IAVF_NVM_PRESERVATION_FLAGS_SHIFT)
-#define IAVF_NVM_PRESERVATION_FLAGS_SELECTED 0x01
-#define IAVF_NVM_PRESERVATION_FLAGS_ALL 0x02
-#define IAVF_NVM_CON 0x0
-#define IAVF_NVM_SNT 0x1
-#define IAVF_NVM_LCB 0x2
-#define IAVF_NVM_SA (IAVF_NVM_SNT | IAVF_NVM_LCB)
-#define IAVF_NVM_ERA 0x4
-#define IAVF_NVM_CSUM 0x8
-#define IAVF_NVM_AQE 0xe
-#define IAVF_NVM_EXEC 0xf
-
-#define IAVF_NVM_ADAPT_SHIFT 16
-#define IAVF_NVM_ADAPT_MASK (0xffffULL << IAVF_NVM_ADAPT_SHIFT)
-
-#define IAVF_NVMUPD_MAX_DATA 4096
-#define IAVF_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
-
-struct iavf_nvm_access {
- u32 command;
- u32 config;
- u32 offset; /* in bytes */
- u32 data_size; /* in bytes */
- u8 data[1];
+struct iavf_nvmupd_features {
+ u8 major;
+ u8 minor;
+ u16 size;
+ u8 features[IAVF_NVMUPD_FEATURES_API_FEATURES_ARRAY_LEN];
};
-/* (Q)SFP module access definitions */
-#define IAVF_I2C_EEPROM_DEV_ADDR 0xA0
-#define IAVF_I2C_EEPROM_DEV_ADDR2 0xA2
-#define IAVF_MODULE_TYPE_ADDR 0x00
-#define IAVF_MODULE_REVISION_ADDR 0x01
-#define IAVF_MODULE_SFF_8472_COMP 0x5E
-#define IAVF_MODULE_SFF_8472_SWAP 0x5C
-#define IAVF_MODULE_SFF_ADDR_MODE 0x04
#define IAVF_MODULE_SFF_DIAG_CAPAB 0x40
-#define IAVF_MODULE_TYPE_QSFP_PLUS 0x0D
-#define IAVF_MODULE_TYPE_QSFP28 0x11
-#define IAVF_MODULE_QSFP_MAX_LEN 640
-
/* PCI bus types */
enum iavf_bus_type {
iavf_bus_type_unknown = 0,
@@ -571,16 +312,7 @@ struct iavf_bus_info {
u16 bus_id;
};
-/* Flow control (FC) parameters */
-struct iavf_fc_info {
- enum iavf_fc_mode current_mode; /* FC mode in effect */
- enum iavf_fc_mode requested_mode; /* FC mode requested by caller */
-};
-
-#define IAVF_MAX_TRAFFIC_CLASS 8
#define IAVF_MAX_USER_PRIORITY 8
-#define IAVF_DCBX_MAX_APPS 32
-#define IAVF_LLDPDU_SIZE 1500
#define IAVF_TLV_STATUS_OPER 0x1
#define IAVF_TLV_STATUS_SYNC 0x2
#define IAVF_TLV_STATUS_ERR 0x4
@@ -593,56 +325,14 @@ struct iavf_fc_info {
#define IAVF_CEE_APP_SEL_ETHTYPE 0x0
#define IAVF_CEE_APP_SEL_TCPIP 0x1
-/* CEE or IEEE 802.1Qaz ETS Configuration data */
-struct iavf_dcb_ets_config {
- u8 willing;
- u8 cbs;
- u8 maxtcs;
- u8 prioritytable[IAVF_MAX_TRAFFIC_CLASS];
- u8 tcbwtable[IAVF_MAX_TRAFFIC_CLASS];
- u8 tsatable[IAVF_MAX_TRAFFIC_CLASS];
-};
-
-/* CEE or IEEE 802.1Qaz PFC Configuration data */
-struct iavf_dcb_pfc_config {
- u8 willing;
- u8 mbc;
- u8 pfccap;
- u8 pfcenable;
-};
-
-/* CEE or IEEE 802.1Qaz Application Priority data */
-struct iavf_dcb_app_priority_table {
- u8 priority;
- u8 selector;
- u16 protocolid;
-};
-
-struct iavf_dcbx_config {
- u8 dcbx_mode;
-#define IAVF_DCBX_MODE_CEE 0x1
-#define IAVF_DCBX_MODE_IEEE 0x2
- u8 app_mode;
-#define IAVF_DCBX_APPS_NON_WILLING 0x1
- u32 numapps;
- u32 tlv_status; /* CEE mode TLV status */
- struct iavf_dcb_ets_config etscfg;
- struct iavf_dcb_ets_config etsrec;
- struct iavf_dcb_pfc_config pfc;
- struct iavf_dcb_app_priority_table app[IAVF_DCBX_MAX_APPS];
-};
-
/* Port hardware description */
struct iavf_hw {
u8 *hw_addr;
void *back;
/* subsystem structs */
- struct iavf_phy_info phy;
struct iavf_mac_info mac;
struct iavf_bus_info bus;
- struct iavf_nvm_info nvm;
- struct iavf_fc_info fc;
/* pci info */
u16 device_id;
@@ -650,47 +340,14 @@ struct iavf_hw {
u16 subsystem_device_id;
u16 subsystem_vendor_id;
u8 revision_id;
- u8 port;
bool adapter_stopped;
/* capabilities for entire device and PCI func */
struct iavf_hw_capabilities dev_caps;
- struct iavf_hw_capabilities func_caps;
-
- /* Flow Director shared filter space */
- u16 fdir_shared_filter_count;
-
- /* device profile info */
- u8 pf_id;
- u16 main_vsi_seid;
-
- /* for multi-function MACs */
- u16 partition_id;
- u16 num_partitions;
- u16 num_ports;
-
- /* Closest numa node to the device */
- u16 numa_node;
/* Admin Queue info */
struct iavf_adminq_info aq;
- /* state of nvm update process */
- enum iavf_nvmupd_state nvmupd_state;
- struct iavf_aq_desc nvm_wb_desc;
- struct iavf_aq_desc nvm_aq_event_desc;
- struct iavf_virt_mem nvm_buff;
- bool nvm_release_on_done;
- u16 nvm_wait_opcode;
-
- /* LLDP/DCBX Status */
- u16 dcbx_status;
-
- /* DCBX info */
- struct iavf_dcbx_config local_dcbx_config; /* Oper/Local Cfg */
- struct iavf_dcbx_config remote_dcbx_config; /* Peer Cfg */
- struct iavf_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */
-
/* WoL and proxy support */
u16 num_wol_proxy_filters;
u16 wol_proxy_vsi_seid;
@@ -699,24 +356,17 @@ struct iavf_hw {
#define IAVF_HW_FLAG_802_1AD_CAPABLE BIT_ULL(1)
#define IAVF_HW_FLAG_AQ_PHY_ACCESS_CAPABLE BIT_ULL(2)
#define IAVF_HW_FLAG_NVM_READ_REQUIRES_LOCK BIT_ULL(3)
+#define IAVF_HW_FLAG_FW_LLDP_STOPPABLE BIT_ULL(4)
u64 flags;
- /* Used in set switch config AQ command */
- u16 switch_tag;
- u16 first_tag;
- u16 second_tag;
+ /* NVMUpdate features */
+ struct iavf_nvmupd_features nvmupd_features;
/* debug mask */
u32 debug_mask;
char err_str[16];
};
-STATIC INLINE bool iavf_is_vf(struct iavf_hw *hw)
-{
- return (hw->mac.type == IAVF_MAC_VF ||
- hw->mac.type == IAVF_MAC_X722_VF);
-}
-
struct iavf_driver_version {
u8 major_version;
u8 minor_version;
@@ -1159,53 +809,6 @@ enum iavf_tx_ctx_desc_cmd_bits {
IAVF_TX_CTX_DESC_SWPE = 0x40
};
-#define IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT 30
-#define IAVF_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \
- IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT)
-
-#define IAVF_TXD_CTX_QW1_MSS_SHIFT 50
-#define IAVF_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \
- IAVF_TXD_CTX_QW1_MSS_SHIFT)
-
-#define IAVF_TXD_CTX_QW1_VSI_SHIFT 50
-#define IAVF_TXD_CTX_QW1_VSI_MASK (0x1FFULL << IAVF_TXD_CTX_QW1_VSI_SHIFT)
-
-#define IAVF_TXD_CTX_QW0_EXT_IP_SHIFT 0
-#define IAVF_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \
- IAVF_TXD_CTX_QW0_EXT_IP_SHIFT)
-
-enum iavf_tx_ctx_desc_eipt_offload {
- IAVF_TX_CTX_EXT_IP_NONE = 0x0,
- IAVF_TX_CTX_EXT_IP_IPV6 = 0x1,
- IAVF_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
- IAVF_TX_CTX_EXT_IP_IPV4 = 0x3
-};
-
-#define IAVF_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2
-#define IAVF_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
- IAVF_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
-
-#define IAVF_TXD_CTX_QW0_NATT_SHIFT 9
-#define IAVF_TXD_CTX_QW0_NATT_MASK (0x3ULL << IAVF_TXD_CTX_QW0_NATT_SHIFT)
-
-#define IAVF_TXD_CTX_UDP_TUNNELING BIT_ULL(IAVF_TXD_CTX_QW0_NATT_SHIFT)
-#define IAVF_TXD_CTX_GRE_TUNNELING (0x2ULL << IAVF_TXD_CTX_QW0_NATT_SHIFT)
-
-#define IAVF_TXD_CTX_QW0_EIP_NOINC_SHIFT 11
-#define IAVF_TXD_CTX_QW0_EIP_NOINC_MASK BIT_ULL(IAVF_TXD_CTX_QW0_EIP_NOINC_SHIFT)
-
-#define IAVF_TXD_CTX_EIP_NOINC_IPID_CONST IAVF_TXD_CTX_QW0_EIP_NOINC_MASK
-
-#define IAVF_TXD_CTX_QW0_NATLEN_SHIFT 12
-#define IAVF_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \
- IAVF_TXD_CTX_QW0_NATLEN_SHIFT)
-
-#define IAVF_TXD_CTX_QW0_DECTTL_SHIFT 19
-#define IAVF_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \
- IAVF_TXD_CTX_QW0_DECTTL_SHIFT)
-
-#define IAVF_TXD_CTX_QW0_L4T_CS_SHIFT 23
-#define IAVF_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(IAVF_TXD_CTX_QW0_L4T_CS_SHIFT)
struct iavf_nop_desc {
__le64 rsvd;
__le64 dtype_cmd;
@@ -1224,22 +827,6 @@ enum iavf_tx_nop_desc_cmd_bits {
IAVF_TX_NOP_DESC_RSV_SHIFT = 2 /* 5 bits */
};
-struct iavf_filter_program_desc {
- __le32 qindex_flex_ptype_vsi;
- __le32 rsvd;
- __le32 dtype_cmd_cntindex;
- __le32 fd_id;
-};
-#define IAVF_TXD_FLTR_QW0_QINDEX_SHIFT 0
-#define IAVF_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \
- IAVF_TXD_FLTR_QW0_QINDEX_SHIFT)
-#define IAVF_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
-#define IAVF_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \
- IAVF_TXD_FLTR_QW0_FLEXOFF_SHIFT)
-#define IAVF_TXD_FLTR_QW0_PCTYPE_SHIFT 17
-#define IAVF_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \
- IAVF_TXD_FLTR_QW0_PCTYPE_SHIFT)
-
/* Packet Classifier Types for filters */
enum iavf_filter_pctype {
/* Note: Values 0-28 are reserved for future use.
@@ -1272,88 +859,61 @@ enum iavf_filter_pctype {
IAVF_FILTER_PCTYPE_L2_PAYLOAD = 63,
};
-enum iavf_filter_program_desc_dest {
- IAVF_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0,
- IAVF_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1,
- IAVF_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2,
-};
-
-enum iavf_filter_program_desc_fd_status {
- IAVF_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0,
- IAVF_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1,
- IAVF_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2,
- IAVF_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3,
-};
-
-#define IAVF_TXD_FLTR_QW0_DEST_VSI_SHIFT 23
-#define IAVF_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
- IAVF_TXD_FLTR_QW0_DEST_VSI_SHIFT)
-
#define IAVF_TXD_FLTR_QW1_DTYPE_SHIFT 0
#define IAVF_TXD_FLTR_QW1_DTYPE_MASK (0xFUL << IAVF_TXD_FLTR_QW1_DTYPE_SHIFT)
-#define IAVF_TXD_FLTR_QW1_CMD_SHIFT 4
-#define IAVF_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \
+#define IAVF_TXD_FLTR_QW1_ATR_SHIFT (0xEULL + \
IAVF_TXD_FLTR_QW1_CMD_SHIFT)
+#define IAVF_TXD_FLTR_QW1_ATR_MASK BIT_ULL(IAVF_TXD_FLTR_QW1_ATR_SHIFT)
-#define IAVF_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + IAVF_TXD_FLTR_QW1_CMD_SHIFT)
-#define IAVF_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << IAVF_TXD_FLTR_QW1_PCMD_SHIFT)
-enum iavf_filter_program_desc_pcmd {
- IAVF_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1,
- IAVF_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2,
+#define IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT 30
+#define IAVF_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \
+ IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT)
+
+#define IAVF_TXD_CTX_QW1_MSS_SHIFT 50
+#define IAVF_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \
+ IAVF_TXD_CTX_QW1_MSS_SHIFT)
+
+#define IAVF_TXD_CTX_QW1_VSI_SHIFT 50
+#define IAVF_TXD_CTX_QW1_VSI_MASK (0x1FFULL << IAVF_TXD_CTX_QW1_VSI_SHIFT)
+
+#define IAVF_TXD_CTX_QW0_EXT_IP_SHIFT 0
+#define IAVF_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \
+ IAVF_TXD_CTX_QW0_EXT_IP_SHIFT)
+
+enum iavf_tx_ctx_desc_eipt_offload {
+ IAVF_TX_CTX_EXT_IP_NONE = 0x0,
+ IAVF_TX_CTX_EXT_IP_IPV6 = 0x1,
+ IAVF_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
+ IAVF_TX_CTX_EXT_IP_IPV4 = 0x3
};
-#define IAVF_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + IAVF_TXD_FLTR_QW1_CMD_SHIFT)
-#define IAVF_TXD_FLTR_QW1_DEST_MASK (0x3ULL << IAVF_TXD_FLTR_QW1_DEST_SHIFT)
+#define IAVF_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2
+#define IAVF_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
+ IAVF_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
-#define IAVF_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + IAVF_TXD_FLTR_QW1_CMD_SHIFT)
-#define IAVF_TXD_FLTR_QW1_CNT_ENA_MASK BIT_ULL(IAVF_TXD_FLTR_QW1_CNT_ENA_SHIFT)
+#define IAVF_TXD_CTX_QW0_NATT_SHIFT 9
+#define IAVF_TXD_CTX_QW0_NATT_MASK (0x3ULL << IAVF_TXD_CTX_QW0_NATT_SHIFT)
-#define IAVF_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \
- IAVF_TXD_FLTR_QW1_CMD_SHIFT)
-#define IAVF_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
- IAVF_TXD_FLTR_QW1_FD_STATUS_SHIFT)
+#define IAVF_TXD_CTX_UDP_TUNNELING BIT_ULL(IAVF_TXD_CTX_QW0_NATT_SHIFT)
+#define IAVF_TXD_CTX_GRE_TUNNELING (0x2ULL << IAVF_TXD_CTX_QW0_NATT_SHIFT)
-#define IAVF_TXD_FLTR_QW1_ATR_SHIFT (0xEULL + \
- IAVF_TXD_FLTR_QW1_CMD_SHIFT)
-#define IAVF_TXD_FLTR_QW1_ATR_MASK BIT_ULL(IAVF_TXD_FLTR_QW1_ATR_SHIFT)
+#define IAVF_TXD_CTX_QW0_EIP_NOINC_SHIFT 11
+#define IAVF_TXD_CTX_QW0_EIP_NOINC_MASK BIT_ULL(IAVF_TXD_CTX_QW0_EIP_NOINC_SHIFT)
-#define IAVF_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
-#define IAVF_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
- IAVF_TXD_FLTR_QW1_CNTINDEX_SHIFT)
-
-enum iavf_filter_type {
- IAVF_FLOW_DIRECTOR_FLTR = 0,
- IAVF_PE_QUAD_HASH_FLTR = 1,
- IAVF_ETHERTYPE_FLTR,
- IAVF_FCOE_CTX_FLTR,
- IAVF_MAC_VLAN_FLTR,
- IAVF_HASH_FLTR
-};
+#define IAVF_TXD_CTX_EIP_NOINC_IPID_CONST IAVF_TXD_CTX_QW0_EIP_NOINC_MASK
-struct iavf_vsi_context {
- u16 seid;
- u16 uplink_seid;
- u16 vsi_number;
- u16 vsis_allocated;
- u16 vsis_unallocated;
- u16 flags;
- u8 pf_num;
- u8 vf_num;
- u8 connection_type;
- struct iavf_aqc_vsi_properties_data info;
-};
+#define IAVF_TXD_CTX_QW0_NATLEN_SHIFT 12
+#define IAVF_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \
+ IAVF_TXD_CTX_QW0_NATLEN_SHIFT)
-struct iavf_veb_context {
- u16 seid;
- u16 uplink_seid;
- u16 veb_number;
- u16 vebs_allocated;
- u16 vebs_unallocated;
- u16 flags;
- struct iavf_aqc_get_veb_parameters_completion info;
-};
+#define IAVF_TXD_CTX_QW0_DECTTL_SHIFT 19
+#define IAVF_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \
+ IAVF_TXD_CTX_QW0_DECTTL_SHIFT)
+
+#define IAVF_TXD_CTX_QW0_L4T_CS_SHIFT 23
+#define IAVF_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(IAVF_TXD_CTX_QW0_L4T_CS_SHIFT)
/* Statistics collected by each port, VSI, VEB, and S-channel */
struct iavf_eth_stats {
@@ -1370,89 +930,6 @@ struct iavf_eth_stats {
u64 tx_discards; /* tdpc */
u64 tx_errors; /* tepc */
};
-
-/* Statistics collected per VEB per TC */
-struct iavf_veb_tc_stats {
- u64 tc_rx_packets[IAVF_MAX_TRAFFIC_CLASS];
- u64 tc_rx_bytes[IAVF_MAX_TRAFFIC_CLASS];
- u64 tc_tx_packets[IAVF_MAX_TRAFFIC_CLASS];
- u64 tc_tx_bytes[IAVF_MAX_TRAFFIC_CLASS];
-};
-
-/* Statistics collected per function for FCoE */
-struct iavf_fcoe_stats {
- u64 rx_fcoe_packets; /* fcoeprc */
- u64 rx_fcoe_dwords; /* focedwrc */
- u64 rx_fcoe_dropped; /* fcoerpdc */
- u64 tx_fcoe_packets; /* fcoeptc */
- u64 tx_fcoe_dwords; /* focedwtc */
- u64 fcoe_bad_fccrc; /* fcoecrc */
- u64 fcoe_last_error; /* fcoelast */
- u64 fcoe_ddp_count; /* fcoeddpc */
-};
-
-/* offset to per function FCoE statistics block */
-#define IAVF_FCOE_VF_STAT_OFFSET 0
-#define IAVF_FCOE_PF_STAT_OFFSET 128
-#define IAVF_FCOE_STAT_MAX (IAVF_FCOE_PF_STAT_OFFSET + IAVF_MAX_PF)
-
-/* Statistics collected by the MAC */
-struct iavf_hw_port_stats {
- /* eth stats collected by the port */
- struct iavf_eth_stats eth;
-
- /* additional port specific stats */
- u64 tx_dropped_link_down; /* tdold */
- u64 crc_errors; /* crcerrs */
- u64 illegal_bytes; /* illerrc */
- u64 error_bytes; /* errbc */
- u64 mac_local_faults; /* mlfc */
- u64 mac_remote_faults; /* mrfc */
- u64 rx_length_errors; /* rlec */
- u64 link_xon_rx; /* lxonrxc */
- u64 link_xoff_rx; /* lxoffrxc */
- u64 priority_xon_rx[8]; /* pxonrxc[8] */
- u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
- u64 link_xon_tx; /* lxontxc */
- u64 link_xoff_tx; /* lxofftxc */
- u64 priority_xon_tx[8]; /* pxontxc[8] */
- u64 priority_xoff_tx[8]; /* pxofftxc[8] */
- u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
- u64 rx_size_64; /* prc64 */
- u64 rx_size_127; /* prc127 */
- u64 rx_size_255; /* prc255 */
- u64 rx_size_511; /* prc511 */
- u64 rx_size_1023; /* prc1023 */
- u64 rx_size_1522; /* prc1522 */
- u64 rx_size_big; /* prc9522 */
- u64 rx_undersize; /* ruc */
- u64 rx_fragments; /* rfc */
- u64 rx_oversize; /* roc */
- u64 rx_jabber; /* rjc */
- u64 tx_size_64; /* ptc64 */
- u64 tx_size_127; /* ptc127 */
- u64 tx_size_255; /* ptc255 */
- u64 tx_size_511; /* ptc511 */
- u64 tx_size_1023; /* ptc1023 */
- u64 tx_size_1522; /* ptc1522 */
- u64 tx_size_big; /* ptc9522 */
- u64 mac_short_packet_dropped; /* mspdc */
- u64 checksum_error; /* xec */
- /* flow director stats */
- u64 fd_atr_match;
- u64 fd_sb_match;
- u64 fd_atr_tunnel_match;
- u32 fd_atr_status;
- u32 fd_sb_status;
- /* EEE LPI */
- u32 tx_lpi_status;
- u32 rx_lpi_status;
- u64 tx_lpi_count; /* etlpic */
- u64 rx_lpi_count; /* erlpic */
-};
-
-/* Checksum and Shadow RAM pointers */
-#define IAVF_SR_NVM_CONTROL_WORD 0x00
#define IAVF_SR_PCIE_ANALOG_CONFIG_PTR 0x03
#define IAVF_SR_PHY_ANALOG_CONFIG_PTR 0x04
#define IAVF_SR_OPTION_ROM_PTR 0x05
@@ -1465,22 +942,13 @@ struct iavf_hw_port_stats {
#define IAVF_SR_PE_IMAGE_PTR 0x0C
#define IAVF_SR_CSR_PROTECTED_LIST_PTR 0x0D
#define IAVF_SR_MNG_CONFIG_PTR 0x0E
-#define IAVF_EMP_MODULE_PTR 0x0F
-#define IAVF_SR_EMP_MODULE_PTR 0x48
#define IAVF_SR_PBA_FLAGS 0x15
#define IAVF_SR_PBA_BLOCK_PTR 0x16
#define IAVF_SR_BOOT_CONFIG_PTR 0x17
-#define IAVF_NVM_OEM_VER_OFF 0x83
-#define IAVF_SR_NVM_DEV_STARTER_VERSION 0x18
-#define IAVF_SR_NVM_WAKE_ON_LAN 0x19
-#define IAVF_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27
#define IAVF_SR_PERMANENT_SAN_MAC_ADDRESS_PTR 0x28
#define IAVF_SR_NVM_MAP_VERSION 0x29
#define IAVF_SR_NVM_IMAGE_VERSION 0x2A
#define IAVF_SR_NVM_STRUCTURE_VERSION 0x2B
-#define IAVF_SR_NVM_EETRACK_LO 0x2D
-#define IAVF_SR_NVM_EETRACK_HI 0x2E
-#define IAVF_SR_VPD_PTR 0x2F
#define IAVF_SR_PXE_SETUP_PTR 0x30
#define IAVF_SR_PXE_CONFIG_CUST_OPTIONS_PTR 0x31
#define IAVF_SR_NVM_ORIGINAL_EETRACK_LO 0x34
@@ -1491,8 +959,6 @@ struct iavf_hw_port_stats {
#define IAVF_SR_GLOBR_REGS_AUTO_LOAD_PTR 0x3B
#define IAVF_SR_CORER_REGS_AUTO_LOAD_PTR 0x3C
#define IAVF_SR_PHY_ACTIVITY_LIST_PTR 0x3D
-#define IAVF_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
-#define IAVF_SR_SW_CHECKSUM_WORD 0x3F
#define IAVF_SR_1ST_FREE_PROVISION_AREA_PTR 0x40
#define IAVF_SR_4TH_FREE_PROVISION_AREA_PTR 0x42
#define IAVF_SR_3RD_FREE_PROVISION_AREA_PTR 0x44
@@ -1501,334 +967,11 @@ struct iavf_hw_port_stats {
#define IAVF_SR_FEATURE_CONFIGURATION_PTR 0x49
#define IAVF_SR_CONFIGURATION_METADATA_PTR 0x4D
#define IAVF_SR_IMMEDIATE_VALUES_PTR 0x4E
-
-/* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
-#define IAVF_SR_VPD_MODULE_MAX_SIZE 1024
-#define IAVF_SR_PCIE_ALT_MODULE_MAX_SIZE 1024
-#define IAVF_SR_CONTROL_WORD_1_SHIFT 0x06
-#define IAVF_SR_CONTROL_WORD_1_MASK (0x03 << IAVF_SR_CONTROL_WORD_1_SHIFT)
-#define IAVF_SR_CONTROL_WORD_1_NVM_BANK_VALID BIT(5)
-#define IAVF_SR_NVM_MAP_STRUCTURE_TYPE BIT(12)
-#define IAVF_PTR_TYPE BIT(15)
-
-/* Shadow RAM related */
-#define IAVF_SR_SECTOR_SIZE_IN_WORDS 0x800
+#define IAVF_SR_OCP_CFG_WORD0 0x2B
+#define IAVF_SR_OCP_ENABLED BIT(15)
#define IAVF_SR_BUF_ALIGNMENT 4096
-#define IAVF_SR_WORDS_IN_1KB 512
-/* Checksum should be calculated such that after adding all the words,
- * including the checksum word itself, the sum should be 0xBABA.
- */
-#define IAVF_SR_SW_CHECKSUM_BASE 0xBABA
-
-#define IAVF_SRRD_SRCTL_ATTEMPTS 100000
-
-/* FCoE Tx context descriptor - Use the iavf_tx_context_desc struct */
-
-enum i40E_fcoe_tx_ctx_desc_cmd_bits {
- IAVF_FCOE_TX_CTX_DESC_OPCODE_SINGLE_SEND = 0x00, /* 4 BITS */
- IAVF_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS2 = 0x01, /* 4 BITS */
- IAVF_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS3 = 0x05, /* 4 BITS */
- IAVF_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS2 = 0x02, /* 4 BITS */
- IAVF_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS3 = 0x06, /* 4 BITS */
- IAVF_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS2 = 0x03, /* 4 BITS */
- IAVF_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS3 = 0x07, /* 4 BITS */
- IAVF_FCOE_TX_CTX_DESC_OPCODE_DDP_CTX_INVL = 0x08, /* 4 BITS */
- IAVF_FCOE_TX_CTX_DESC_OPCODE_DWO_CTX_INVL = 0x09, /* 4 BITS */
- IAVF_FCOE_TX_CTX_DESC_RELOFF = 0x10,
- IAVF_FCOE_TX_CTX_DESC_CLRSEQ = 0x20,
- IAVF_FCOE_TX_CTX_DESC_DIFENA = 0x40,
- IAVF_FCOE_TX_CTX_DESC_IL2TAG2 = 0x80
-};
-/* FCoE DIF/DIX Context descriptor */
-struct iavf_fcoe_difdix_context_desc {
- __le64 flags_buff0_buff1_ref;
- __le64 difapp_msk_bias;
-};
-
-#define IAVF_FCOE_DIFDIX_CTX_QW0_FLAGS_SHIFT 0
-#define IAVF_FCOE_DIFDIX_CTX_QW0_FLAGS_MASK (0xFFFULL << \
- IAVF_FCOE_DIFDIX_CTX_QW0_FLAGS_SHIFT)
-
-enum iavf_fcoe_difdix_ctx_desc_flags_bits {
- /* 2 BITS */
- IAVF_FCOE_DIFDIX_CTX_DESC_RSVD = 0x0000,
- /* 1 BIT */
- IAVF_FCOE_DIFDIX_CTX_DESC_APPTYPE_TAGCHK = 0x0000,
- /* 1 BIT */
- IAVF_FCOE_DIFDIX_CTX_DESC_APPTYPE_TAGNOTCHK = 0x0004,
- /* 2 BITS */
- IAVF_FCOE_DIFDIX_CTX_DESC_GTYPE_OPAQUE = 0x0000,
- /* 2 BITS */
- IAVF_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY = 0x0008,
- /* 2 BITS */
- IAVF_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY_APPTAG = 0x0010,
- /* 2 BITS */
- IAVF_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY_APPREFTAG = 0x0018,
- /* 2 BITS */
- IAVF_FCOE_DIFDIX_CTX_DESC_REFTYPE_CNST = 0x0000,
- /* 2 BITS */
- IAVF_FCOE_DIFDIX_CTX_DESC_REFTYPE_INC1BLK = 0x0020,
- /* 2 BITS */
- IAVF_FCOE_DIFDIX_CTX_DESC_REFTYPE_APPTAG = 0x0040,
- /* 2 BITS */
- IAVF_FCOE_DIFDIX_CTX_DESC_REFTYPE_RSVD = 0x0060,
- /* 1 BIT */
- IAVF_FCOE_DIFDIX_CTX_DESC_DIXMODE_XSUM = 0x0000,
- /* 1 BIT */
- IAVF_FCOE_DIFDIX_CTX_DESC_DIXMODE_CRC = 0x0080,
- /* 2 BITS */
- IAVF_FCOE_DIFDIX_CTX_DESC_DIFHOST_UNTAG = 0x0000,
- /* 2 BITS */
- IAVF_FCOE_DIFDIX_CTX_DESC_DIFHOST_BUF = 0x0100,
- /* 2 BITS */
- IAVF_FCOE_DIFDIX_CTX_DESC_DIFHOST_RSVD = 0x0200,
- /* 2 BITS */
- IAVF_FCOE_DIFDIX_CTX_DESC_DIFHOST_EMBDTAGS = 0x0300,
- /* 1 BIT */
- IAVF_FCOE_DIFDIX_CTX_DESC_DIFLAN_UNTAG = 0x0000,
- /* 1 BIT */
- IAVF_FCOE_DIFDIX_CTX_DESC_DIFLAN_TAG = 0x0400,
- /* 1 BIT */
- IAVF_FCOE_DIFDIX_CTX_DESC_DIFBLK_512B = 0x0000,
- /* 1 BIT */
- IAVF_FCOE_DIFDIX_CTX_DESC_DIFBLK_4K = 0x0800
-};
-
-#define IAVF_FCOE_DIFDIX_CTX_QW0_BUFF0_SHIFT 12
-#define IAVF_FCOE_DIFDIX_CTX_QW0_BUFF0_MASK (0x3FFULL << \
- IAVF_FCOE_DIFDIX_CTX_QW0_BUFF0_SHIFT)
-
-#define IAVF_FCOE_DIFDIX_CTX_QW0_BUFF1_SHIFT 22
-#define IAVF_FCOE_DIFDIX_CTX_QW0_BUFF1_MASK (0x3FFULL << \
- IAVF_FCOE_DIFDIX_CTX_QW0_BUFF1_SHIFT)
-
-#define IAVF_FCOE_DIFDIX_CTX_QW0_REF_SHIFT 32
-#define IAVF_FCOE_DIFDIX_CTX_QW0_REF_MASK (0xFFFFFFFFULL << \
- IAVF_FCOE_DIFDIX_CTX_QW0_REF_SHIFT)
-
-#define IAVF_FCOE_DIFDIX_CTX_QW1_APP_SHIFT 0
-#define IAVF_FCOE_DIFDIX_CTX_QW1_APP_MASK (0xFFFFULL << \
- IAVF_FCOE_DIFDIX_CTX_QW1_APP_SHIFT)
-
-#define IAVF_FCOE_DIFDIX_CTX_QW1_APP_MSK_SHIFT 16
-#define IAVF_FCOE_DIFDIX_CTX_QW1_APP_MSK_MASK (0xFFFFULL << \
- IAVF_FCOE_DIFDIX_CTX_QW1_APP_MSK_SHIFT)
-
-#define IAVF_FCOE_DIFDIX_CTX_QW1_REF_BIAS_SHIFT 32
-#define IAVF_FCOE_DIFDIX_CTX_QW0_REF_BIAS_MASK (0xFFFFFFFFULL << \
- IAVF_FCOE_DIFDIX_CTX_QW1_REF_BIAS_SHIFT)
-
-/* FCoE DIF/DIX Buffers descriptor */
-struct iavf_fcoe_difdix_buffers_desc {
- __le64 buff_addr0;
- __le64 buff_addr1;
-};
-
-/* FCoE DDP Context descriptor */
-struct iavf_fcoe_ddp_context_desc {
- __le64 rsvd;
- __le64 type_cmd_foff_lsize;
-};
-#define IAVF_FCOE_DDP_CTX_QW1_DTYPE_SHIFT 0
-#define IAVF_FCOE_DDP_CTX_QW1_DTYPE_MASK (0xFULL << \
- IAVF_FCOE_DDP_CTX_QW1_DTYPE_SHIFT)
-
-#define IAVF_FCOE_DDP_CTX_QW1_CMD_SHIFT 4
-#define IAVF_FCOE_DDP_CTX_QW1_CMD_MASK (0xFULL << \
- IAVF_FCOE_DDP_CTX_QW1_CMD_SHIFT)
-
-enum iavf_fcoe_ddp_ctx_desc_cmd_bits {
- IAVF_FCOE_DDP_CTX_DESC_BSIZE_512B = 0x00, /* 2 BITS */
- IAVF_FCOE_DDP_CTX_DESC_BSIZE_4K = 0x01, /* 2 BITS */
- IAVF_FCOE_DDP_CTX_DESC_BSIZE_8K = 0x02, /* 2 BITS */
- IAVF_FCOE_DDP_CTX_DESC_BSIZE_16K = 0x03, /* 2 BITS */
- IAVF_FCOE_DDP_CTX_DESC_DIFENA = 0x04, /* 1 BIT */
- IAVF_FCOE_DDP_CTX_DESC_LASTSEQH = 0x08, /* 1 BIT */
-};
-
-#define IAVF_FCOE_DDP_CTX_QW1_FOFF_SHIFT 16
-#define IAVF_FCOE_DDP_CTX_QW1_FOFF_MASK (0x3FFFULL << \
- IAVF_FCOE_DDP_CTX_QW1_FOFF_SHIFT)
-
-#define IAVF_FCOE_DDP_CTX_QW1_LSIZE_SHIFT 32
-#define IAVF_FCOE_DDP_CTX_QW1_LSIZE_MASK (0x3FFFULL << \
- IAVF_FCOE_DDP_CTX_QW1_LSIZE_SHIFT)
-
-/* FCoE DDP/DWO Queue Context descriptor */
-struct iavf_fcoe_queue_context_desc {
- __le64 dmaindx_fbase; /* 0:11 DMAINDX, 12:63 FBASE */
- __le64 flen_tph; /* 0:12 FLEN, 13:15 TPH */
-};
-
-#define IAVF_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT 0
-#define IAVF_FCOE_QUEUE_CTX_QW0_DMAINDX_MASK (0xFFFULL << \
- IAVF_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT)
-
-#define IAVF_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT 12
-#define IAVF_FCOE_QUEUE_CTX_QW0_FBASE_MASK (0xFFFFFFFFFFFFFULL << \
- IAVF_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT)
-
-#define IAVF_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT 0
-#define IAVF_FCOE_QUEUE_CTX_QW1_FLEN_MASK (0x1FFFULL << \
- IAVF_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
-
-#define IAVF_FCOE_QUEUE_CTX_QW1_TPH_SHIFT 13
-#define IAVF_FCOE_QUEUE_CTX_QW1_TPH_MASK (0x7ULL << \
- IAVF_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
-
-enum iavf_fcoe_queue_ctx_desc_tph_bits {
- IAVF_FCOE_QUEUE_CTX_DESC_TPHRDESC = 0x1,
- IAVF_FCOE_QUEUE_CTX_DESC_TPHDATA = 0x2
-};
-
-#define IAVF_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT 30
-#define IAVF_FCOE_QUEUE_CTX_QW1_RECIPE_MASK (0x3ULL << \
- IAVF_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT)
-
-/* FCoE DDP/DWO Filter Context descriptor */
-struct iavf_fcoe_filter_context_desc {
- __le32 param;
- __le16 seqn;
-
- /* 48:51(0:3) RSVD, 52:63(4:15) DMAINDX */
- __le16 rsvd_dmaindx;
-
- /* 0:7 FLAGS, 8:52 RSVD, 53:63 LANQ */
- __le64 flags_rsvd_lanq;
-};
-
-#define IAVF_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT 4
-#define IAVF_FCOE_FILTER_CTX_QW0_DMAINDX_MASK (0xFFF << \
- IAVF_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT)
-
-enum iavf_fcoe_filter_ctx_desc_flags_bits {
- IAVF_FCOE_FILTER_CTX_DESC_CTYP_DDP = 0x00,
- IAVF_FCOE_FILTER_CTX_DESC_CTYP_DWO = 0x01,
- IAVF_FCOE_FILTER_CTX_DESC_ENODE_INIT = 0x00,
- IAVF_FCOE_FILTER_CTX_DESC_ENODE_RSP = 0x02,
- IAVF_FCOE_FILTER_CTX_DESC_FC_CLASS2 = 0x00,
- IAVF_FCOE_FILTER_CTX_DESC_FC_CLASS3 = 0x04
-};
-
-#define IAVF_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT 0
-#define IAVF_FCOE_FILTER_CTX_QW1_FLAGS_MASK (0xFFULL << \
- IAVF_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT)
-
-#define IAVF_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT 8
-#define IAVF_FCOE_FILTER_CTX_QW1_PCTYPE_MASK (0x3FULL << \
- IAVF_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT)
-
-#define IAVF_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT 53
-#define IAVF_FCOE_FILTER_CTX_QW1_LANQINDX_MASK (0x7FFULL << \
- IAVF_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT)
-
-enum iavf_switch_element_types {
- IAVF_SWITCH_ELEMENT_TYPE_MAC = 1,
- IAVF_SWITCH_ELEMENT_TYPE_PF = 2,
- IAVF_SWITCH_ELEMENT_TYPE_VF = 3,
- IAVF_SWITCH_ELEMENT_TYPE_EMP = 4,
- IAVF_SWITCH_ELEMENT_TYPE_BMC = 6,
- IAVF_SWITCH_ELEMENT_TYPE_PE = 16,
- IAVF_SWITCH_ELEMENT_TYPE_VEB = 17,
- IAVF_SWITCH_ELEMENT_TYPE_PA = 18,
- IAVF_SWITCH_ELEMENT_TYPE_VSI = 19,
-};
-
-/* Supported EtherType filters */
-enum iavf_ether_type_index {
- IAVF_ETHER_TYPE_1588 = 0,
- IAVF_ETHER_TYPE_FIP = 1,
- IAVF_ETHER_TYPE_OUI_EXTENDED = 2,
- IAVF_ETHER_TYPE_MAC_CONTROL = 3,
- IAVF_ETHER_TYPE_LLDP = 4,
- IAVF_ETHER_TYPE_EVB_PROTOCOL1 = 5,
- IAVF_ETHER_TYPE_EVB_PROTOCOL2 = 6,
- IAVF_ETHER_TYPE_QCN_CNM = 7,
- IAVF_ETHER_TYPE_8021X = 8,
- IAVF_ETHER_TYPE_ARP = 9,
- IAVF_ETHER_TYPE_RSV1 = 10,
- IAVF_ETHER_TYPE_RSV2 = 11,
-};
-
-/* Filter context base size is 1K */
-#define IAVF_HASH_FILTER_BASE_SIZE 1024
-/* Supported Hash filter values */
-enum iavf_hash_filter_size {
- IAVF_HASH_FILTER_SIZE_1K = 0,
- IAVF_HASH_FILTER_SIZE_2K = 1,
- IAVF_HASH_FILTER_SIZE_4K = 2,
- IAVF_HASH_FILTER_SIZE_8K = 3,
- IAVF_HASH_FILTER_SIZE_16K = 4,
- IAVF_HASH_FILTER_SIZE_32K = 5,
- IAVF_HASH_FILTER_SIZE_64K = 6,
- IAVF_HASH_FILTER_SIZE_128K = 7,
- IAVF_HASH_FILTER_SIZE_256K = 8,
- IAVF_HASH_FILTER_SIZE_512K = 9,
- IAVF_HASH_FILTER_SIZE_1M = 10,
-};
-
-/* DMA context base size is 0.5K */
-#define IAVF_DMA_CNTX_BASE_SIZE 512
-/* Supported DMA context values */
-enum iavf_dma_cntx_size {
- IAVF_DMA_CNTX_SIZE_512 = 0,
- IAVF_DMA_CNTX_SIZE_1K = 1,
- IAVF_DMA_CNTX_SIZE_2K = 2,
- IAVF_DMA_CNTX_SIZE_4K = 3,
- IAVF_DMA_CNTX_SIZE_8K = 4,
- IAVF_DMA_CNTX_SIZE_16K = 5,
- IAVF_DMA_CNTX_SIZE_32K = 6,
- IAVF_DMA_CNTX_SIZE_64K = 7,
- IAVF_DMA_CNTX_SIZE_128K = 8,
- IAVF_DMA_CNTX_SIZE_256K = 9,
-};
-
-/* Supported Hash look up table (LUT) sizes */
-enum iavf_hash_lut_size {
- IAVF_HASH_LUT_SIZE_128 = 0,
- IAVF_HASH_LUT_SIZE_512 = 1,
-};
-
-/* Structure to hold a per PF filter control settings */
-struct iavf_filter_control_settings {
- /* number of PE Quad Hash filter buckets */
- enum iavf_hash_filter_size pe_filt_num;
- /* number of PE Quad Hash contexts */
- enum iavf_dma_cntx_size pe_cntx_num;
- /* number of FCoE filter buckets */
- enum iavf_hash_filter_size fcoe_filt_num;
- /* number of FCoE DDP contexts */
- enum iavf_dma_cntx_size fcoe_cntx_num;
- /* size of the Hash LUT */
- enum iavf_hash_lut_size hash_lut_size;
- /* enable FDIR filters for PF and its VFs */
- bool enable_fdir;
- /* enable Ethertype filters for PF and its VFs */
- bool enable_ethtype;
- /* enable MAC/VLAN filters for PF and its VFs */
- bool enable_macvlan;
-};
-
-/* Structure to hold device level control filter counts */
-struct iavf_control_filter_stats {
- u16 mac_etype_used; /* Used perfect match MAC/EtherType filters */
- u16 etype_used; /* Used perfect EtherType filters */
- u16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */
- u16 etype_free; /* Un-used perfect EtherType filters */
-};
-
-enum iavf_reset_type {
- IAVF_RESET_POR = 0,
- IAVF_RESET_CORER = 1,
- IAVF_RESET_GLOBR = 2,
- IAVF_RESET_EMPR = 3,
-};
-
-/* IEEE 802.1AB LLDP Agent Variables from NVM */
-#define IAVF_NVM_LLDP_CFG_PTR 0x06
-#define IAVF_SR_LLDP_CFG_PTR 0x31
struct iavf_lldp_variables {
u16 length;
u16 adminstatus;
@@ -1852,118 +995,13 @@ struct iavf_lldp_variables {
#define IAVF_ALT_BW_RELATIVE_MASK 0x40000000
#define IAVF_ALT_BW_VALID_MASK 0x80000000
-/* RSS Hash Table Size */
-#define IAVF_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
-
-/* INPUT SET MASK for RSS, flow director, and flexible payload */
-#define IAVF_L3_SRC_SHIFT 47
-#define IAVF_L3_SRC_MASK (0x3ULL << IAVF_L3_SRC_SHIFT)
-#define IAVF_L3_V6_SRC_SHIFT 43
-#define IAVF_L3_V6_SRC_MASK (0xFFULL << IAVF_L3_V6_SRC_SHIFT)
-#define IAVF_L3_DST_SHIFT 35
-#define IAVF_L3_DST_MASK (0x3ULL << IAVF_L3_DST_SHIFT)
-#define IAVF_L3_V6_DST_SHIFT 35
-#define IAVF_L3_V6_DST_MASK (0xFFULL << IAVF_L3_V6_DST_SHIFT)
-#define IAVF_L4_SRC_SHIFT 34
-#define IAVF_L4_SRC_MASK (0x1ULL << IAVF_L4_SRC_SHIFT)
-#define IAVF_L4_DST_SHIFT 33
-#define IAVF_L4_DST_MASK (0x1ULL << IAVF_L4_DST_SHIFT)
-#define IAVF_VERIFY_TAG_SHIFT 31
-#define IAVF_VERIFY_TAG_MASK (0x3ULL << IAVF_VERIFY_TAG_SHIFT)
-
-#define IAVF_FLEX_50_SHIFT 13
-#define IAVF_FLEX_50_MASK (0x1ULL << IAVF_FLEX_50_SHIFT)
-#define IAVF_FLEX_51_SHIFT 12
-#define IAVF_FLEX_51_MASK (0x1ULL << IAVF_FLEX_51_SHIFT)
-#define IAVF_FLEX_52_SHIFT 11
-#define IAVF_FLEX_52_MASK (0x1ULL << IAVF_FLEX_52_SHIFT)
-#define IAVF_FLEX_53_SHIFT 10
-#define IAVF_FLEX_53_MASK (0x1ULL << IAVF_FLEX_53_SHIFT)
-#define IAVF_FLEX_54_SHIFT 9
-#define IAVF_FLEX_54_MASK (0x1ULL << IAVF_FLEX_54_SHIFT)
-#define IAVF_FLEX_55_SHIFT 8
-#define IAVF_FLEX_55_MASK (0x1ULL << IAVF_FLEX_55_SHIFT)
-#define IAVF_FLEX_56_SHIFT 7
-#define IAVF_FLEX_56_MASK (0x1ULL << IAVF_FLEX_56_SHIFT)
-#define IAVF_FLEX_57_SHIFT 6
-#define IAVF_FLEX_57_MASK (0x1ULL << IAVF_FLEX_57_SHIFT)
-
-/* Version format for Dynamic Device Personalization(DDP) */
-struct iavf_ddp_version {
- u8 major;
- u8 minor;
- u8 update;
- u8 draft;
-};
-
-#define IAVF_DDP_NAME_SIZE 32
-
-/* Package header */
-struct iavf_package_header {
- struct iavf_ddp_version version;
- u32 segment_count;
- u32 segment_offset[1];
-};
-
-/* Generic segment header */
-struct iavf_generic_seg_header {
-#define SEGMENT_TYPE_METADATA 0x00000001
-#define SEGMENT_TYPE_NOTES 0x00000002
-#define SEGMENT_TYPE_IAVF 0x00000011
-#define SEGMENT_TYPE_X722 0x00000012
- u32 type;
- struct iavf_ddp_version version;
- u32 size;
- char name[IAVF_DDP_NAME_SIZE];
-};
-
-struct iavf_metadata_segment {
- struct iavf_generic_seg_header header;
- struct iavf_ddp_version version;
#define IAVF_DDP_TRACKID_RDONLY 0
#define IAVF_DDP_TRACKID_INVALID 0xFFFFFFFF
- u32 track_id;
- char name[IAVF_DDP_NAME_SIZE];
-};
-
-struct iavf_device_id_entry {
- u32 vendor_dev_id;
- u32 sub_vendor_dev_id;
-};
-
-struct iavf_profile_segment {
- struct iavf_generic_seg_header header;
- struct iavf_ddp_version version;
- char name[IAVF_DDP_NAME_SIZE];
- u32 device_table_count;
- struct iavf_device_id_entry device_table[1];
-};
-
-struct iavf_section_table {
- u32 section_count;
- u32 section_offset[1];
-};
-
-struct iavf_profile_section_header {
- u16 tbl_size;
- u16 data_end;
- struct {
-#define SECTION_TYPE_INFO 0x00000010
-#define SECTION_TYPE_MMIO 0x00000800
#define SECTION_TYPE_RB_MMIO 0x00001800
-#define SECTION_TYPE_AQ 0x00000801
#define SECTION_TYPE_RB_AQ 0x00001801
-#define SECTION_TYPE_NOTE 0x80000000
-#define SECTION_TYPE_NAME 0x80000001
#define SECTION_TYPE_PROTO 0x80000002
#define SECTION_TYPE_PCTYPE 0x80000003
#define SECTION_TYPE_PTYPE 0x80000004
- u32 type;
- u32 offset;
- u32 size;
- } section;
-};
-
struct iavf_profile_tlv_section_record {
u8 rtype;
u8 type;
@@ -1980,13 +1018,4 @@ struct iavf_profile_aq_section {
u8 data[1];
};
-struct iavf_profile_info {
- u32 track_id;
- struct iavf_ddp_version version;
- u8 op;
-#define IAVF_DDP_ADD_TRACKID 0x01
-#define IAVF_DDP_REMOVE_TRACKID 0x02
- u8 reserved[7];
- u8 name[IAVF_DDP_NAME_SIZE];
-};
#endif /* _IAVF_TYPE_H_ */
--
2.13.6
^ permalink raw reply [flat|nested] 21+ messages in thread* [dpdk-dev] [PATCH 06/17] net/iavf/base: remove unnecessary compile option
2019-12-03 7:03 [dpdk-dev] [PATCH 00/17] iavf base code update Qi Zhang
` (4 preceding siblings ...)
2019-12-03 7:03 ` [dpdk-dev] [PATCH 05/17] net/iavf/base: remove unused code Qi Zhang
@ 2019-12-03 7:03 ` Qi Zhang
2019-12-03 7:03 ` [dpdk-dev] [PATCH 07/17] net/iavf/base: rename functions Qi Zhang
` (11 subsequent siblings)
17 siblings, 0 replies; 21+ messages in thread
From: Qi Zhang @ 2019-12-03 7:03 UTC (permalink / raw)
To: xiaolong.ye; +Cc: haiyue.wang, dev, Qi Zhang, Paul M Stillwell Jr
Remove compile option INTEGRATED_VF.
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/iavf/base/iavf_adminq.c | 19 -------------------
drivers/net/iavf/base/iavf_common.c | 9 ++-------
drivers/net/iavf/base/iavf_type.h | 8 --------
3 files changed, 2 insertions(+), 34 deletions(-)
diff --git a/drivers/net/iavf/base/iavf_adminq.c b/drivers/net/iavf/base/iavf_adminq.c
index 68c51daac..ef352ac4c 100644
--- a/drivers/net/iavf/base/iavf_adminq.c
+++ b/drivers/net/iavf/base/iavf_adminq.c
@@ -262,14 +262,8 @@ STATIC enum iavf_status iavf_config_asq_regs(struct iavf_hw *hw)
wr32(hw, hw->aq.asq.tail, 0);
/* set starting point */
-#ifdef INTEGRATED_VF
- if (iavf_is_vf(hw))
- wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries |
- IAVF_VF_ATQLEN1_ATQENABLE_MASK));
-#else
wr32(hw, hw->aq.asq.len, (hw->aq.num_asq_entries |
IAVF_VF_ATQLEN1_ATQENABLE_MASK));
-#endif /* INTEGRATED_VF */
wr32(hw, hw->aq.asq.bal, IAVF_LO_DWORD(hw->aq.asq.desc_buf.pa));
wr32(hw, hw->aq.asq.bah, IAVF_HI_DWORD(hw->aq.asq.desc_buf.pa));
@@ -297,14 +291,8 @@ STATIC enum iavf_status iavf_config_arq_regs(struct iavf_hw *hw)
wr32(hw, hw->aq.arq.tail, 0);
/* set starting point */
-#ifdef INTEGRATED_VF
- if (iavf_is_vf(hw))
- wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries |
- IAVF_VF_ARQLEN1_ARQENABLE_MASK));
-#else
wr32(hw, hw->aq.arq.len, (hw->aq.num_arq_entries |
IAVF_VF_ARQLEN1_ARQENABLE_MASK));
-#endif /* INTEGRATED_VF */
wr32(hw, hw->aq.arq.bal, IAVF_LO_DWORD(hw->aq.arq.desc_buf.pa));
wr32(hw, hw->aq.arq.bah, IAVF_HI_DWORD(hw->aq.arq.desc_buf.pa));
@@ -897,14 +885,7 @@ enum iavf_status iavf_clean_arq_element(struct iavf_hw *hw,
}
/* set next_to_use to head */
-#ifdef INTEGRATED_VF
- if (!iavf_is_vf(hw))
- ntu = rd32(hw, hw->aq.arq.head) & IAVF_PF_ARQH_ARQH_MASK;
- else
- ntu = rd32(hw, hw->aq.arq.head) & IAVF_VF_ARQH1_ARQH_MASK;
-#else
ntu = rd32(hw, hw->aq.arq.head) & IAVF_VF_ARQH1_ARQH_MASK;
-#endif /* INTEGRATED_VF */
if (ntu == ntc) {
/* nothing to do - shouldn't need to update ring's values */
ret_code = IAVF_ERR_ADMIN_QUEUE_NO_WORK;
diff --git a/drivers/net/iavf/base/iavf_common.c b/drivers/net/iavf/base/iavf_common.c
index 926081e87..53e877732 100644
--- a/drivers/net/iavf/base/iavf_common.c
+++ b/drivers/net/iavf/base/iavf_common.c
@@ -331,15 +331,10 @@ void iavf_debug_aq(struct iavf_hw *hw, enum iavf_debug_mask mask, void *desc,
bool iavf_check_asq_alive(struct iavf_hw *hw)
{
if (hw->aq.asq.len)
-#ifdef INTEGRATED_VF
- if (iavf_is_vf(hw))
- return !!(rd32(hw, hw->aq.asq.len) &
- IAVF_VF_ATQLEN1_ATQENABLE_MASK);
-#else
return !!(rd32(hw, hw->aq.asq.len) &
IAVF_VF_ATQLEN1_ATQENABLE_MASK);
-#endif /* INTEGRATED_VF */
- return false;
+ else
+ return false;
}
/**
diff --git a/drivers/net/iavf/base/iavf_type.h b/drivers/net/iavf/base/iavf_type.h
index 487352f51..c1910ff75 100644
--- a/drivers/net/iavf/base/iavf_type.h
+++ b/drivers/net/iavf/base/iavf_type.h
@@ -20,14 +20,8 @@
#define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) (_p); (_q); (_r); (_s);
#define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t) (_p); (_q); (_r); (_s); (_t);
-#ifndef LINUX_MACROS
-#ifndef BIT
#define BIT(a) (1UL << (a))
-#endif /* BIT */
-#ifndef BIT_ULL
#define BIT_ULL(a) (1ULL << (a))
-#endif /* BIT_ULL */
-#endif /* LINUX_MACROS */
/* IAVF_MASK is a macro used on 32 bit registers */
#define IAVF_MASK(mask, shift) (mask << shift)
@@ -56,9 +50,7 @@
struct iavf_hw;
typedef void (*IAVF_ADMINQ_CALLBACK)(struct iavf_hw *, struct iavf_aq_desc *);
-#ifndef ETH_ALEN
#define ETH_ALEN 6
-#endif
/* Data type manipulation macros. */
#define IAVF_HI_DWORD(x) ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
#define IAVF_LO_DWORD(x) ((u32)((x) & 0xFFFFFFFF))
--
2.13.6
^ permalink raw reply [flat|nested] 21+ messages in thread* [dpdk-dev] [PATCH 07/17] net/iavf/base: rename functions
2019-12-03 7:03 [dpdk-dev] [PATCH 00/17] iavf base code update Qi Zhang
` (5 preceding siblings ...)
2019-12-03 7:03 ` [dpdk-dev] [PATCH 06/17] net/iavf/base: remove unnecessary compile option Qi Zhang
@ 2019-12-03 7:03 ` Qi Zhang
2019-12-03 7:03 ` [dpdk-dev] [PATCH 08/17] net/iavf/base: update virtual channel Qi Zhang
` (10 subsequent siblings)
17 siblings, 0 replies; 21+ messages in thread
From: Qi Zhang @ 2019-12-03 7:03 UTC (permalink / raw)
To: xiaolong.ye; +Cc: haiyue.wang, dev, Qi Zhang, Paul M Stillwell Jr
Rename iavf_parse_hw_config to iavf_vf_parse_hw_config.
Rename iavf_reset to iavf_vf_reset.
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/iavf/base/iavf_common.c | 8 ++++----
drivers/net/iavf/base/iavf_prototype.h | 4 ++--
drivers/net/iavf/iavf_vchnl.c | 2 +-
3 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/net/iavf/base/iavf_common.c b/drivers/net/iavf/base/iavf_common.c
index 53e877732..b6e875440 100644
--- a/drivers/net/iavf/base/iavf_common.c
+++ b/drivers/net/iavf/base/iavf_common.c
@@ -955,14 +955,14 @@ enum iavf_status iavf_aq_send_msg_to_pf(struct iavf_hw *hw,
}
/**
- * iavf_parse_hw_config
+ * iavf_vf_parse_hw_config
* @hw: pointer to the hardware structure
* @msg: pointer to the virtual channel VF resource structure
*
* Given a VF resource message from the PF, populate the hw struct
* with appropriate information.
**/
-void iavf_parse_hw_config(struct iavf_hw *hw,
+void iavf_vf_parse_hw_config(struct iavf_hw *hw,
struct virtchnl_vf_resource *msg)
{
struct virtchnl_vsi_resource *vsi_res;
@@ -991,14 +991,14 @@ void iavf_parse_hw_config(struct iavf_hw *hw,
}
/**
- * iavf_reset
+ * iavf_vf_reset
* @hw: pointer to the hardware structure
*
* Send a VF_RESET message to the PF. Does not wait for response from PF
* as none will be forthcoming. Immediately after calling this function,
* the admin queue should be shut down and (optionally) reinitialized.
**/
-enum iavf_status iavf_reset(struct iavf_hw *hw)
+enum iavf_status iavf_vf_reset(struct iavf_hw *hw)
{
return iavf_aq_send_msg_to_pf(hw, VIRTCHNL_OP_RESET_VF,
IAVF_SUCCESS, NULL, 0, NULL);
diff --git a/drivers/net/iavf/base/iavf_prototype.h b/drivers/net/iavf/base/iavf_prototype.h
index 5b61b43d9..36b5a17f8 100644
--- a/drivers/net/iavf/base/iavf_prototype.h
+++ b/drivers/net/iavf/base/iavf_prototype.h
@@ -76,9 +76,9 @@ void iavf_acquire_spinlock(struct iavf_spinlock *sp);
void iavf_release_spinlock(struct iavf_spinlock *sp);
void iavf_destroy_spinlock(struct iavf_spinlock *sp);
-void iavf_parse_hw_config(struct iavf_hw *hw,
+void iavf_vf_parse_hw_config(struct iavf_hw *hw,
struct virtchnl_vf_resource *msg);
-enum iavf_status iavf_reset(struct iavf_hw *hw);
+enum iavf_status iavf_vf_reset(struct iavf_hw *hw);
enum iavf_status iavf_aq_send_msg_to_pf(struct iavf_hw *hw,
enum virtchnl_ops v_opcode,
enum iavf_status v_retval,
diff --git a/drivers/net/iavf/iavf_vchnl.c b/drivers/net/iavf/iavf_vchnl.c
index 4320a7f91..bf87ab611 100644
--- a/drivers/net/iavf/iavf_vchnl.c
+++ b/drivers/net/iavf/iavf_vchnl.c
@@ -363,7 +363,7 @@ iavf_get_vf_resource(struct iavf_adapter *adapter)
rte_memcpy(vf->vf_res, args.out_buffer,
RTE_MIN(args.out_size, len));
/* parse VF config message back from PF*/
- iavf_parse_hw_config(hw, vf->vf_res);
+ iavf_vf_parse_hw_config(hw, vf->vf_res);
for (i = 0; i < vf->vf_res->num_vsis; i++) {
if (vf->vf_res->vsi_res[i].vsi_type == VIRTCHNL_VSI_SRIOV)
vf->vsi_res = &vf->vf_res->vsi_res[i];
--
2.13.6
^ permalink raw reply [flat|nested] 21+ messages in thread* [dpdk-dev] [PATCH 08/17] net/iavf/base: update virtual channel
2019-12-03 7:03 [dpdk-dev] [PATCH 00/17] iavf base code update Qi Zhang
` (6 preceding siblings ...)
2019-12-03 7:03 ` [dpdk-dev] [PATCH 07/17] net/iavf/base: rename functions Qi Zhang
@ 2019-12-03 7:03 ` Qi Zhang
2019-12-03 7:03 ` [dpdk-dev] [PATCH 09/17] net/iavf/base: adjust code indent Qi Zhang
` (9 subsequent siblings)
17 siblings, 0 replies; 21+ messages in thread
From: Qi Zhang @ 2019-12-03 7:03 UTC (permalink / raw)
To: xiaolong.ye; +Cc: haiyue.wang, dev, Qi Zhang, Paul M Stillwell Jr
Update virtual channel API to align with latest spec.
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/iavf/base/virtchnl.h | 343 ++++++++++++++++++++++++++-------------
1 file changed, 232 insertions(+), 111 deletions(-)
diff --git a/drivers/net/iavf/base/virtchnl.h b/drivers/net/iavf/base/virtchnl.h
index 50f7c8e49..1604f19e3 100644
--- a/drivers/net/iavf/base/virtchnl.h
+++ b/drivers/net/iavf/base/virtchnl.h
@@ -40,19 +40,27 @@
/* Error Codes */
enum virtchnl_status_code {
VIRTCHNL_STATUS_SUCCESS = 0,
- VIRTCHNL_ERR_PARAM = -5,
+ VIRTCHNL_STATUS_ERR_PARAM = -5,
+ VIRTCHNL_STATUS_ERR_NO_MEMORY = -18,
VIRTCHNL_STATUS_ERR_OPCODE_MISMATCH = -38,
VIRTCHNL_STATUS_ERR_CQP_COMPL_ERROR = -39,
VIRTCHNL_STATUS_ERR_INVALID_VF_ID = -40,
- VIRTCHNL_STATUS_NOT_SUPPORTED = -64,
+ VIRTCHNL_STATUS_ERR_ADMIN_QUEUE_ERROR = -53,
+ VIRTCHNL_STATUS_ERR_NOT_SUPPORTED = -64,
};
+/* Backward compatibility */
+#define VIRTCHNL_ERR_PARAM VIRTCHNL_STATUS_ERR_PARAM
+#define VIRTCHNL_STATUS_NOT_SUPPORTED VIRTCHNL_STATUS_ERR_NOT_SUPPORTED
+
+#define VIRTCHNL_LINK_SPEED_2_5GB_SHIFT 0x0
#define VIRTCHNL_LINK_SPEED_100MB_SHIFT 0x1
#define VIRTCHNL_LINK_SPEED_1000MB_SHIFT 0x2
#define VIRTCHNL_LINK_SPEED_10GB_SHIFT 0x3
#define VIRTCHNL_LINK_SPEED_40GB_SHIFT 0x4
#define VIRTCHNL_LINK_SPEED_20GB_SHIFT 0x5
#define VIRTCHNL_LINK_SPEED_25GB_SHIFT 0x6
+#define VIRTCHNL_LINK_SPEED_5GB_SHIFT 0x7
enum virtchnl_link_speed {
VIRTCHNL_LINK_SPEED_UNKNOWN = 0,
@@ -62,6 +70,8 @@ enum virtchnl_link_speed {
VIRTCHNL_LINK_SPEED_40GB = BIT(VIRTCHNL_LINK_SPEED_40GB_SHIFT),
VIRTCHNL_LINK_SPEED_20GB = BIT(VIRTCHNL_LINK_SPEED_20GB_SHIFT),
VIRTCHNL_LINK_SPEED_25GB = BIT(VIRTCHNL_LINK_SPEED_25GB_SHIFT),
+ VIRTCHNL_LINK_SPEED_2_5GB = BIT(VIRTCHNL_LINK_SPEED_2_5GB_SHIFT),
+ VIRTCHNL_LINK_SPEED_5GB = BIT(VIRTCHNL_LINK_SPEED_5GB_SHIFT),
};
/* for hsplit_0 field of Rx HMC context */
@@ -105,14 +115,8 @@ enum virtchnl_ops {
VIRTCHNL_OP_GET_STATS = 15,
VIRTCHNL_OP_RSVD = 16,
VIRTCHNL_OP_EVENT = 17, /* must ALWAYS be 17 */
-#ifdef VIRTCHNL_SOL_VF_SUPPORT
- VIRTCHNL_OP_GET_ADDNL_SOL_CONFIG = 19,
-#endif
-#ifdef VIRTCHNL_IWARP
- VIRTCHNL_OP_IWARP = 20, /* advanced opcode */
- VIRTCHNL_OP_CONFIG_IWARP_IRQ_MAP = 21, /* advanced opcode */
- VIRTCHNL_OP_RELEASE_IWARP_IRQ_MAP = 22, /* advanced opcode */
-#endif
+ /* opcode 19 is reserved */
+ /* opcodes 20, 21, and 22 are reserved */
VIRTCHNL_OP_CONFIG_RSS_KEY = 23,
VIRTCHNL_OP_CONFIG_RSS_LUT = 24,
VIRTCHNL_OP_GET_RSS_HENA_CAPS = 25,
@@ -120,16 +124,22 @@ enum virtchnl_ops {
VIRTCHNL_OP_ENABLE_VLAN_STRIPPING = 27,
VIRTCHNL_OP_DISABLE_VLAN_STRIPPING = 28,
VIRTCHNL_OP_REQUEST_QUEUES = 29,
-
+ VIRTCHNL_OP_ENABLE_CHANNELS = 30,
+ VIRTCHNL_OP_DISABLE_CHANNELS = 31,
+ VIRTCHNL_OP_ADD_CLOUD_FILTER = 32,
+ VIRTCHNL_OP_DEL_CLOUD_FILTER = 33,
+ /* opcodes 34, 35, 36, 37 and 38 are reserved */
};
-/* This macro is used to generate a compilation error if a structure
+/* These macros are used to generate compilation errors if a structure/union
* is not exactly the correct length. It gives a divide by zero error if the
- * structure is not of the correct size, otherwise it creates an enum that is
- * never used.
+ * structure/union is not of the correct size, otherwise it creates an enum
+ * that is never used.
*/
#define VIRTCHNL_CHECK_STRUCT_LEN(n, X) enum virtchnl_static_assert_enum_##X \
- {virtchnl_static_assert_##X = (n) / ((sizeof(struct X) == (n)) ? 1 : 0)}
+ { virtchnl_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
+#define VIRTCHNL_CHECK_UNION_LEN(n, X) enum virtchnl_static_asset_enum_##X \
+ { virtchnl_static_assert_##X = (n)/((sizeof(union X) == (n)) ? 1 : 0) }
/* Virtual channel message descriptor. This overlays the admin queue
* descriptor. All other data is passed in external buffers.
@@ -144,7 +154,7 @@ struct virtchnl_msg {
VIRTCHNL_CHECK_STRUCT_LEN(20, virtchnl_msg);
-/* Message descriptions and data structures.*/
+/* Message descriptions and data structures. */
/* VIRTCHNL_OP_VERSION
* VF posts its version number to the PF. PF responds with its version number
@@ -222,6 +232,7 @@ VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_vsi_resource);
#define VIRTCHNL_VF_OFFLOAD_RSS_REG 0x00000010
#define VIRTCHNL_VF_OFFLOAD_WB_ON_ITR 0x00000020
#define VIRTCHNL_VF_OFFLOAD_REQ_QUEUES 0x00000040
+#define VIRTCHNL_VF_OFFLOAD_CRC 0x00000080
#define VIRTCHNL_VF_OFFLOAD_VLAN 0x00010000
#define VIRTCHNL_VF_OFFLOAD_RX_POLLING 0x00020000
#define VIRTCHNL_VF_OFFLOAD_RSS_PCTYPE_V2 0x00040000
@@ -229,9 +240,13 @@ VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_vsi_resource);
#define VIRTCHNL_VF_OFFLOAD_ENCAP 0X00100000
#define VIRTCHNL_VF_OFFLOAD_ENCAP_CSUM 0X00200000
#define VIRTCHNL_VF_OFFLOAD_RX_ENCAP_CSUM 0X00400000
-/* Define below the capability flags that are not offloads */
-#define VIRTCHNL_VF_CAP_ADV_LINK_SPEED 0x00000080
+#define VIRTCHNL_VF_OFFLOAD_ADQ 0X00800000
+#define VIRTCHNL_VF_OFFLOAD_ADQ_V2 0X01000000
+#define VIRTCHNL_VF_OFFLOAD_USO 0X02000000
+ /* 0X80000000 is reserved */
+/* Define below the capability flags that are not offloads */
+#define VIRTCHNL_VF_CAP_ADV_LINK_SPEED 0x00000080
#define VF_BASE_MODE_OFFLOADS (VIRTCHNL_VF_OFFLOAD_L2 | \
VIRTCHNL_VF_OFFLOAD_VLAN | \
VIRTCHNL_VF_OFFLOAD_RSS_PF)
@@ -262,9 +277,9 @@ struct virtchnl_txq_info {
u16 vsi_id;
u16 queue_id;
u16 ring_len; /* number of descriptors, multiple of 8 */
- u16 headwb_enabled; /* deprecated with IAVF 1.0 */
+ u16 headwb_enabled; /* deprecated with AVF 1.0 */
u64 dma_ring_addr;
- u64 dma_headwb_addr; /* deprecated with IAVF 1.0 */
+ u64 dma_headwb_addr; /* deprecated with AVF 1.0 */
};
VIRTCHNL_CHECK_STRUCT_LEN(24, virtchnl_txq_info);
@@ -272,7 +287,13 @@ VIRTCHNL_CHECK_STRUCT_LEN(24, virtchnl_txq_info);
/* VIRTCHNL_OP_CONFIG_RX_QUEUE
* VF sends this message to set up parameters for one RX queue.
* External data buffer contains one instance of virtchnl_rxq_info.
- * PF configures requested queue and returns a status code.
+ * PF configures requested queue and returns a status code. The
+ * crc_disable flag disables CRC stripping on the VF. Setting
+ * the crc_disable flag to 1 will disable CRC stripping for each
+ * queue in the VF where the flag is set. The VIRTCHNL_VF_OFFLOAD_CRC
+ * offload must have been set prior to sending this info or the PF
+ * will ignore the request. This flag should be set the same for
+ * all of the queues for a VF.
*/
/* Rx queue config info */
@@ -281,23 +302,27 @@ struct virtchnl_rxq_info {
u16 queue_id;
u32 ring_len; /* number of descriptors, multiple of 32 */
u16 hdr_size;
- u16 splithdr_enabled; /* deprecated with IAVF 1.0 */
+ u16 splithdr_enabled; /* deprecated with AVF 1.0 */
u32 databuffer_size;
u32 max_pkt_size;
- u32 pad1;
+ u8 crc_disable;
+ u8 pad1[3];
u64 dma_ring_addr;
- enum virtchnl_rx_hsplit rx_split_pos; /* deprecated with IAVF 1.0 */
+ enum virtchnl_rx_hsplit rx_split_pos; /* deprecated with AVF 1.0 */
u32 pad2;
};
VIRTCHNL_CHECK_STRUCT_LEN(40, virtchnl_rxq_info);
/* VIRTCHNL_OP_CONFIG_VSI_QUEUES
- * VF sends this message to set parameters for all active TX and RX queues
+ * VF sends this message to set parameters for active TX and RX queues
* associated with the specified VSI.
* PF configures queues and returns status.
* If the number of queues specified is greater than the number of queues
* associated with the VSI, an error is returned and no queues are configured.
+ * NOTE: The VF is not required to configure all queues in a single request.
+ * It may send multiple messages. PF drivers must correctly handle all VF
+ * requests.
*/
struct virtchnl_queue_pair_info {
/* NOTE: vsi_id and queue_id should be identical for both queues. */
@@ -335,8 +360,13 @@ struct virtchnl_vf_res_request {
* VF uses this message to map vectors to queues.
* The rxq_map and txq_map fields are bitmaps used to indicate which queues
* are to be associated with the specified vector.
- * The "other" causes are always mapped to vector 0.
+ * The "other" causes are always mapped to vector 0. The VF may not request
+ * that vector 0 be used for traffic.
* PF configures interrupt mapping and returns status.
+ * NOTE: due to hardware requirements, all active queues (both TX and RX)
+ * should be mapped to interrupts, even if the driver intends to operate
+ * only in polling mode. In this case the interrupt may be disabled, but
+ * the ITR timer will still run to trigger writebacks.
*/
struct virtchnl_vector_map {
u16 vsi_id;
@@ -363,6 +393,9 @@ VIRTCHNL_CHECK_STRUCT_LEN(14, virtchnl_irq_map_info);
* (Currently, we only support 16 queues per VF, but we make the field
* u32 to allow for expansion.)
* PF performs requested action and returns status.
+ * NOTE: The VF is not required to enable/disable all queues in a single
+ * request. It may send multiple messages.
+ * PF drivers must correctly handle all VF requests.
*/
struct virtchnl_queue_select {
u16 vsi_id;
@@ -400,23 +433,6 @@ struct virtchnl_ether_addr_list {
VIRTCHNL_CHECK_STRUCT_LEN(12, virtchnl_ether_addr_list);
-#ifdef VIRTCHNL_SOL_VF_SUPPORT
-/* VIRTCHNL_OP_GET_ADDNL_SOL_CONFIG
- * VF sends this message to get the default MTU and list of additional ethernet
- * addresses it is allowed to use.
- * PF responds with an indirect message containing
- * virtchnl_addnl_solaris_config with zero or more
- * virtchnl_ether_addr structures.
- *
- * It is expected that this operation will only ever be needed for Solaris VFs
- * running under a Solaris PF.
- */
-struct virtchnl_addnl_solaris_config {
- u16 default_mtu;
- struct virtchnl_ether_addr_list al;
-};
-
-#endif
/* VIRTCHNL_OP_ADD_VLAN
* VF sends this message to add one or more VLAN tag filters for receives.
* PF adds the filters and returns status.
@@ -469,7 +485,7 @@ struct virtchnl_eth_stats {
u64 rx_broadcast; /* received broadcast pkts */
u64 rx_discards;
u64 rx_unknown_protocol;
- u64 tx_bytes; /* transmitted bytes*/
+ u64 tx_bytes; /* transmitted bytes */
u64 tx_unicast; /* transmitted unicast pkts */
u64 tx_multicast; /* transmitted multicast pkts */
u64 tx_broadcast; /* transmitted broadcast pkts */
@@ -515,6 +531,95 @@ struct virtchnl_rss_hena {
VIRTCHNL_CHECK_STRUCT_LEN(8, virtchnl_rss_hena);
+/* This is used by PF driver to enforce how many channels can be supported.
+ * When ADQ_V2 capability is negotiated, it will allow 16 channels otherwise
+ * PF driver will allow only max 4 channels
+ */
+#define VIRTCHNL_MAX_ADQ_CHANNELS 4
+#define VIRTCHNL_MAX_ADQ_V2_CHANNELS 16
+
+/* VIRTCHNL_OP_ENABLE_CHANNELS
+ * VIRTCHNL_OP_DISABLE_CHANNELS
+ * VF sends these messages to enable or disable channels based on
+ * the user specified queue count and queue offset for each traffic class.
+ * This struct encompasses all the information that the PF needs from
+ * VF to create a channel.
+ */
+struct virtchnl_channel_info {
+ u16 count; /* number of queues in a channel */
+ u16 offset; /* queues in a channel start from 'offset' */
+ u32 pad;
+ u64 max_tx_rate;
+};
+
+VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_channel_info);
+
+struct virtchnl_tc_info {
+ u32 num_tc;
+ u32 pad;
+ struct virtchnl_channel_info list[1];
+};
+
+VIRTCHNL_CHECK_STRUCT_LEN(24, virtchnl_tc_info);
+
+/* VIRTCHNL_ADD_CLOUD_FILTER
+ * VIRTCHNL_DEL_CLOUD_FILTER
+ * VF sends these messages to add or delete a cloud filter based on the
+ * user specified match and action filters. These structures encompass
+ * all the information that the PF needs from the VF to add/delete a
+ * cloud filter.
+ */
+
+struct virtchnl_l4_spec {
+ u8 src_mac[ETH_ALEN];
+ u8 dst_mac[ETH_ALEN];
+ /* vlan_prio is part of this 16 bit field even from OS perspective
+ * vlan_id:12 is actual vlan_id, then vlanid:bit14..12 is vlan_prio
+ * in future, when decided to offload vlan_prio, pass that information
+ * as part of the "vlan_id" field, Bit14..12
+ */
+ __be16 vlan_id;
+ __be16 pad; /* reserved for future use */
+ __be32 src_ip[4];
+ __be32 dst_ip[4];
+ __be16 src_port;
+ __be16 dst_port;
+};
+
+VIRTCHNL_CHECK_STRUCT_LEN(52, virtchnl_l4_spec);
+
+union virtchnl_flow_spec {
+ struct virtchnl_l4_spec tcp_spec;
+ u8 buffer[128]; /* reserved for future use */
+};
+
+VIRTCHNL_CHECK_UNION_LEN(128, virtchnl_flow_spec);
+
+enum virtchnl_action {
+ /* action types */
+ VIRTCHNL_ACTION_DROP = 0,
+ VIRTCHNL_ACTION_TC_REDIRECT,
+};
+
+enum virtchnl_flow_type {
+ /* flow types */
+ VIRTCHNL_TCP_V4_FLOW = 0,
+ VIRTCHNL_TCP_V6_FLOW,
+ VIRTCHNL_UDP_V4_FLOW,
+ VIRTCHNL_UDP_V6_FLOW,
+};
+
+struct virtchnl_filter {
+ union virtchnl_flow_spec data;
+ union virtchnl_flow_spec mask;
+ enum virtchnl_flow_type flow_type;
+ enum virtchnl_action action;
+ u32 action_meta;
+ u8 field_flags;
+};
+
+VIRTCHNL_CHECK_STRUCT_LEN(272, virtchnl_filter);
+
/* VIRTCHNL_OP_EVENT
* PF sends this message to inform the VF driver of events that may affect it.
* No direct response is expected from the VF, though it may generate other
@@ -559,44 +664,33 @@ struct virtchnl_pf_event {
VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_pf_event);
-#ifdef VIRTCHNL_IWARP
-
-/* VIRTCHNL_OP_CONFIG_IWARP_IRQ_MAP
- * VF uses this message to request PF to map IWARP vectors to IWARP queues.
- * The request for this originates from the VF IWARP driver through
- * a client interface between VF LAN and VF IWARP driver.
- * A vector could have an AEQ and CEQ attached to it although
- * there is a single AEQ per VF IWARP instance in which case
- * most vectors will have an INVALID_IDX for aeq and valid idx for ceq.
- * There will never be a case where there will be multiple CEQs attached
- * to a single vector.
- * PF configures interrupt mapping and returns status.
- */
-/* HW does not define a type value for AEQ; only for RX/TX and CEQ.
- * In order for us to keep the interface simple, SW will define a
- * unique type value for AEQ.
+/* Since VF messages are limited by u16 size, precalculate the maximum possible
+ * values of nested elements in virtchnl structures that virtual channel can
+ * possibly handle in a single message.
*/
-#define QUEUE_TYPE_PE_AEQ 0x80
-#define QUEUE_INVALID_IDX 0xFFFF
+enum virtchnl_vector_limits {
+ VIRTCHNL_OP_CONFIG_VSI_QUEUES_MAX =
+ ((u16)(~0) - sizeof(struct virtchnl_vsi_queue_config_info)) /
+ sizeof(struct virtchnl_queue_pair_info),
-struct virtchnl_iwarp_qv_info {
- u32 v_idx; /* msix_vector */
- u16 ceq_idx;
- u16 aeq_idx;
- u8 itr_idx;
-};
+ VIRTCHNL_OP_CONFIG_IRQ_MAP_MAX =
+ ((u16)(~0) - sizeof(struct virtchnl_irq_map_info)) /
+ sizeof(struct virtchnl_vector_map),
-VIRTCHNL_CHECK_STRUCT_LEN(12, virtchnl_iwarp_qv_info);
+ VIRTCHNL_OP_ADD_DEL_ETH_ADDR_MAX =
+ ((u16)(~0) - sizeof(struct virtchnl_ether_addr_list)) /
+ sizeof(struct virtchnl_ether_addr),
-struct virtchnl_iwarp_qvlist_info {
- u32 num_vectors;
- struct virtchnl_iwarp_qv_info qv_info[1];
-};
+ VIRTCHNL_OP_ADD_DEL_VLAN_MAX =
+ ((u16)(~0) - sizeof(struct virtchnl_vlan_filter_list)) /
+ sizeof(u16),
-VIRTCHNL_CHECK_STRUCT_LEN(16, virtchnl_iwarp_qvlist_info);
-#endif
+ VIRTCHNL_OP_ENABLE_CHANNELS_MAX =
+ ((u16)(~0) - sizeof(struct virtchnl_tc_info)) /
+ sizeof(struct virtchnl_channel_info),
+};
/* VF reset states - these are written into the RSTAT register:
* VFGEN_RSTAT on the VF
@@ -653,11 +747,16 @@ virtchnl_vc_validate_vf_msg(struct virtchnl_version_info *ver, u32 v_opcode,
if (msglen >= valid_len) {
struct virtchnl_vsi_queue_config_info *vqc =
(struct virtchnl_vsi_queue_config_info *)msg;
+
+ if (vqc->num_queue_pairs == 0 || vqc->num_queue_pairs >
+ VIRTCHNL_OP_CONFIG_VSI_QUEUES_MAX) {
+ err_msg_format = true;
+ break;
+ }
+
valid_len += (vqc->num_queue_pairs *
sizeof(struct
virtchnl_queue_pair_info));
- if (vqc->num_queue_pairs == 0)
- err_msg_format = true;
}
break;
case VIRTCHNL_OP_CONFIG_IRQ_MAP:
@@ -665,10 +764,15 @@ virtchnl_vc_validate_vf_msg(struct virtchnl_version_info *ver, u32 v_opcode,
if (msglen >= valid_len) {
struct virtchnl_irq_map_info *vimi =
(struct virtchnl_irq_map_info *)msg;
+
+ if (vimi->num_vectors == 0 || vimi->num_vectors >
+ VIRTCHNL_OP_CONFIG_IRQ_MAP_MAX) {
+ err_msg_format = true;
+ break;
+ }
+
valid_len += (vimi->num_vectors *
sizeof(struct virtchnl_vector_map));
- if (vimi->num_vectors == 0)
- err_msg_format = true;
}
break;
case VIRTCHNL_OP_ENABLE_QUEUES:
@@ -681,10 +785,15 @@ virtchnl_vc_validate_vf_msg(struct virtchnl_version_info *ver, u32 v_opcode,
if (msglen >= valid_len) {
struct virtchnl_ether_addr_list *veal =
(struct virtchnl_ether_addr_list *)msg;
+
+ if (veal->num_elements == 0 || veal->num_elements >
+ VIRTCHNL_OP_ADD_DEL_ETH_ADDR_MAX) {
+ err_msg_format = true;
+ break;
+ }
+
valid_len += veal->num_elements *
sizeof(struct virtchnl_ether_addr);
- if (veal->num_elements == 0)
- err_msg_format = true;
}
break;
case VIRTCHNL_OP_ADD_VLAN:
@@ -693,9 +802,14 @@ virtchnl_vc_validate_vf_msg(struct virtchnl_version_info *ver, u32 v_opcode,
if (msglen >= valid_len) {
struct virtchnl_vlan_filter_list *vfl =
(struct virtchnl_vlan_filter_list *)msg;
- valid_len += vfl->num_elements * sizeof(u16);
- if (vfl->num_elements == 0)
+
+ if (vfl->num_elements == 0 || vfl->num_elements >
+ VIRTCHNL_OP_ADD_DEL_VLAN_MAX) {
err_msg_format = true;
+ break;
+ }
+
+ valid_len += vfl->num_elements * sizeof(u16);
}
break;
case VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE:
@@ -704,38 +818,17 @@ virtchnl_vc_validate_vf_msg(struct virtchnl_version_info *ver, u32 v_opcode,
case VIRTCHNL_OP_GET_STATS:
valid_len = sizeof(struct virtchnl_queue_select);
break;
-#ifdef VIRTCHNL_IWARP
- case VIRTCHNL_OP_IWARP:
- /* These messages are opaque to us and will be validated in
- * the RDMA client code. We just need to check for nonzero
- * length. The firmware will enforce max length restrictions.
- */
- if (msglen)
- valid_len = msglen;
- else
- err_msg_format = true;
- break;
- case VIRTCHNL_OP_RELEASE_IWARP_IRQ_MAP:
- break;
- case VIRTCHNL_OP_CONFIG_IWARP_IRQ_MAP:
- valid_len = sizeof(struct virtchnl_iwarp_qvlist_info);
- if (msglen >= valid_len) {
- struct virtchnl_iwarp_qvlist_info *qv =
- (struct virtchnl_iwarp_qvlist_info *)msg;
- if (qv->num_vectors == 0) {
- err_msg_format = true;
- break;
- }
- valid_len += ((qv->num_vectors - 1) *
- sizeof(struct virtchnl_iwarp_qv_info));
- }
- break;
-#endif
case VIRTCHNL_OP_CONFIG_RSS_KEY:
valid_len = sizeof(struct virtchnl_rss_key);
if (msglen >= valid_len) {
struct virtchnl_rss_key *vrk =
(struct virtchnl_rss_key *)msg;
+
+ if (vrk->key_len == 0) {
+ /* zero length is allowed as input */
+ break;
+ }
+
valid_len += vrk->key_len - 1;
}
break;
@@ -744,6 +837,12 @@ virtchnl_vc_validate_vf_msg(struct virtchnl_version_info *ver, u32 v_opcode,
if (msglen >= valid_len) {
struct virtchnl_rss_lut *vrl =
(struct virtchnl_rss_lut *)msg;
+
+ if (vrl->lut_entries == 0) {
+ /* zero entries is allowed as input */
+ break;
+ }
+
valid_len += vrl->lut_entries - 1;
}
break;
@@ -758,11 +857,33 @@ virtchnl_vc_validate_vf_msg(struct virtchnl_version_info *ver, u32 v_opcode,
case VIRTCHNL_OP_REQUEST_QUEUES:
valid_len = sizeof(struct virtchnl_vf_res_request);
break;
+ case VIRTCHNL_OP_ENABLE_CHANNELS:
+ valid_len = sizeof(struct virtchnl_tc_info);
+ if (msglen >= valid_len) {
+ struct virtchnl_tc_info *vti =
+ (struct virtchnl_tc_info *)msg;
+
+ if (vti->num_tc == 0 || vti->num_tc >
+ VIRTCHNL_OP_ENABLE_CHANNELS_MAX) {
+ err_msg_format = true;
+ break;
+ }
+
+ valid_len += (vti->num_tc - 1) *
+ sizeof(struct virtchnl_channel_info);
+ }
+ break;
+ case VIRTCHNL_OP_DISABLE_CHANNELS:
+ break;
+ case VIRTCHNL_OP_ADD_CLOUD_FILTER:
+ case VIRTCHNL_OP_DEL_CLOUD_FILTER:
+ valid_len = sizeof(struct virtchnl_filter);
+ break;
/* These are always errors coming from the VF. */
case VIRTCHNL_OP_EVENT:
case VIRTCHNL_OP_UNKNOWN:
default:
- return VIRTCHNL_ERR_PARAM;
+ return VIRTCHNL_STATUS_ERR_PARAM;
}
/* few more checks */
if (err_msg_format || valid_len != msglen)
--
2.13.6
^ permalink raw reply [flat|nested] 21+ messages in thread* [dpdk-dev] [PATCH 09/17] net/iavf/base: adjust code indent
2019-12-03 7:03 [dpdk-dev] [PATCH 00/17] iavf base code update Qi Zhang
` (7 preceding siblings ...)
2019-12-03 7:03 ` [dpdk-dev] [PATCH 08/17] net/iavf/base: update virtual channel Qi Zhang
@ 2019-12-03 7:03 ` Qi Zhang
2019-12-03 7:03 ` [dpdk-dev] [PATCH 10/17] net/iavf/base: increase max VSI count for VFs Qi Zhang
` (8 subsequent siblings)
17 siblings, 0 replies; 21+ messages in thread
From: Qi Zhang @ 2019-12-03 7:03 UTC (permalink / raw)
To: xiaolong.ye; +Cc: haiyue.wang, dev, Qi Zhang, Paul M Stillwell Jr
Adjust the indent in function and macro defination.
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/iavf/base/iavf_alloc.h | 14 +++++++-------
drivers/net/iavf/base/iavf_common.c | 22 +++++++++++-----------
drivers/net/iavf/base/iavf_prototype.h | 16 ++++++++--------
drivers/net/iavf/base/iavf_type.h | 19 ++++++++++---------
4 files changed, 36 insertions(+), 35 deletions(-)
diff --git a/drivers/net/iavf/base/iavf_alloc.h b/drivers/net/iavf/base/iavf_alloc.h
index da872bdbb..a409bb099 100644
--- a/drivers/net/iavf/base/iavf_alloc.h
+++ b/drivers/net/iavf/base/iavf_alloc.h
@@ -22,15 +22,15 @@ enum iavf_memory_type {
/* prototype for functions used for dynamic memory allocation */
enum iavf_status iavf_allocate_dma_mem(struct iavf_hw *hw,
- struct iavf_dma_mem *mem,
- enum iavf_memory_type type,
- u64 size, u32 alignment);
+ struct iavf_dma_mem *mem,
+ enum iavf_memory_type type,
+ u64 size, u32 alignment);
enum iavf_status iavf_free_dma_mem(struct iavf_hw *hw,
- struct iavf_dma_mem *mem);
+ struct iavf_dma_mem *mem);
enum iavf_status iavf_allocate_virt_mem(struct iavf_hw *hw,
- struct iavf_virt_mem *mem,
- u32 size);
+ struct iavf_virt_mem *mem,
+ u32 size);
enum iavf_status iavf_free_virt_mem(struct iavf_hw *hw,
- struct iavf_virt_mem *mem);
+ struct iavf_virt_mem *mem);
#endif /* _IAVF_ALLOC_H_ */
diff --git a/drivers/net/iavf/base/iavf_common.c b/drivers/net/iavf/base/iavf_common.c
index b6e875440..c2c1fd1e4 100644
--- a/drivers/net/iavf/base/iavf_common.c
+++ b/drivers/net/iavf/base/iavf_common.c
@@ -346,7 +346,7 @@ bool iavf_check_asq_alive(struct iavf_hw *hw)
* or not the driver is unloading as well.
**/
enum iavf_status iavf_aq_queue_shutdown(struct iavf_hw *hw,
- bool unloading)
+ bool unloading)
{
struct iavf_aq_desc desc;
struct iavf_aqc_queue_shutdown *cmd =
@@ -375,9 +375,9 @@ enum iavf_status iavf_aq_queue_shutdown(struct iavf_hw *hw,
* Internal function to get or set RSS look up table
**/
STATIC enum iavf_status iavf_aq_get_set_rss_lut(struct iavf_hw *hw,
- u16 vsi_id, bool pf_lut,
- u8 *lut, u16 lut_size,
- bool set)
+ u16 vsi_id, bool pf_lut,
+ u8 *lut, u16 lut_size,
+ bool set)
{
enum iavf_status status;
struct iavf_aq_desc desc;
@@ -428,7 +428,7 @@ STATIC enum iavf_status iavf_aq_get_set_rss_lut(struct iavf_hw *hw,
* get the RSS lookup table, PF or VSI type
**/
enum iavf_status iavf_aq_get_rss_lut(struct iavf_hw *hw, u16 vsi_id,
- bool pf_lut, u8 *lut, u16 lut_size)
+ bool pf_lut, u8 *lut, u16 lut_size)
{
return iavf_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
false);
@@ -445,7 +445,7 @@ enum iavf_status iavf_aq_get_rss_lut(struct iavf_hw *hw, u16 vsi_id,
* set the RSS lookup table, PF or VSI type
**/
enum iavf_status iavf_aq_set_rss_lut(struct iavf_hw *hw, u16 vsi_id,
- bool pf_lut, u8 *lut, u16 lut_size)
+ bool pf_lut, u8 *lut, u16 lut_size)
{
return iavf_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
}
@@ -500,8 +500,8 @@ STATIC enum iavf_status iavf_aq_get_set_rss_key(struct iavf_hw *hw,
*
**/
enum iavf_status iavf_aq_get_rss_key(struct iavf_hw *hw,
- u16 vsi_id,
- struct iavf_aqc_get_set_rss_key_data *key)
+ u16 vsi_id,
+ struct iavf_aqc_get_set_rss_key_data *key)
{
return iavf_aq_get_set_rss_key(hw, vsi_id, key, false);
}
@@ -515,8 +515,8 @@ enum iavf_status iavf_aq_get_rss_key(struct iavf_hw *hw,
* set the RSS key per VSI
**/
enum iavf_status iavf_aq_set_rss_key(struct iavf_hw *hw,
- u16 vsi_id,
- struct iavf_aqc_get_set_rss_key_data *key)
+ u16 vsi_id,
+ struct iavf_aqc_get_set_rss_key_data *key)
{
return iavf_aq_get_set_rss_key(hw, vsi_id, key, true);
}
@@ -1012,7 +1012,7 @@ enum iavf_status iavf_vf_reset(struct iavf_hw *hw)
* Get information for the reason of a Wake Up event
**/
enum iavf_status iavf_aq_clear_all_wol_filters(struct iavf_hw *hw,
- struct iavf_asq_cmd_details *cmd_details)
+ struct iavf_asq_cmd_details *cmd_details)
{
struct iavf_aq_desc desc;
enum iavf_status status;
diff --git a/drivers/net/iavf/base/iavf_prototype.h b/drivers/net/iavf/base/iavf_prototype.h
index 36b5a17f8..a5d0b0073 100644
--- a/drivers/net/iavf/base/iavf_prototype.h
+++ b/drivers/net/iavf/base/iavf_prototype.h
@@ -31,8 +31,8 @@ void iavf_free_adminq_arq(struct iavf_hw *hw);
enum iavf_status iavf_validate_mac_addr(u8 *mac_addr);
void iavf_adminq_init_ring_data(struct iavf_hw *hw);
enum iavf_status iavf_clean_arq_element(struct iavf_hw *hw,
- struct iavf_arq_event_info *e,
- u16 *events_pending);
+ struct iavf_arq_event_info *e,
+ u16 *events_pending);
enum iavf_status iavf_asq_send_command(struct iavf_hw *hw,
struct iavf_aq_desc *desc,
void *buff, /* can be NULL */
@@ -49,9 +49,9 @@ bool iavf_check_asq_alive(struct iavf_hw *hw);
enum iavf_status iavf_aq_queue_shutdown(struct iavf_hw *hw, bool unloading);
enum iavf_status iavf_aq_get_rss_lut(struct iavf_hw *hw, u16 seid,
- bool pf_lut, u8 *lut, u16 lut_size);
+ bool pf_lut, u8 *lut, u16 lut_size);
enum iavf_status iavf_aq_set_rss_lut(struct iavf_hw *hw, u16 seid,
- bool pf_lut, u8 *lut, u16 lut_size);
+ bool pf_lut, u8 *lut, u16 lut_size);
enum iavf_status iavf_aq_get_rss_key(struct iavf_hw *hw,
u16 seid,
struct iavf_aqc_get_set_rss_key_data *key);
@@ -85,10 +85,10 @@ enum iavf_status iavf_aq_send_msg_to_pf(struct iavf_hw *hw,
u8 *msg, u16 msglen,
struct iavf_asq_cmd_details *cmd_details);
enum iavf_status iavf_aq_debug_dump(struct iavf_hw *hw, u8 cluster_id,
- u8 table_id, u32 start_index, u16 buff_size,
- void *buff, u16 *ret_buff_size,
- u8 *ret_next_table, u32 *ret_next_index,
- struct iavf_asq_cmd_details *cmd_details);
+ u8 table_id, u32 start_index, u16 buff_size,
+ void *buff, u16 *ret_buff_size,
+ u8 *ret_next_table, u32 *ret_next_index,
+ struct iavf_asq_cmd_details *cmd_details);
enum iavf_status iavf_aq_clear_all_wol_filters(struct iavf_hw *hw,
struct iavf_asq_cmd_details *cmd_details);
#endif /* _IAVF_PROTOTYPE_H_ */
diff --git a/drivers/net/iavf/base/iavf_type.h b/drivers/net/iavf/base/iavf_type.h
index c1910ff75..6d63f4396 100644
--- a/drivers/net/iavf/base/iavf_type.h
+++ b/drivers/net/iavf/base/iavf_type.h
@@ -11,7 +11,7 @@
#include "iavf_adminq.h"
#include "iavf_devids.h"
-#define IAVF_RXQ_CTX_DBUFF_SHIFT 7
+#define IAVF_RXQ_CTX_DBUFF_SHIFT 7
#define UNREFERENCED_XPARAMETER
#define UNREFERENCED_1PARAMETER(_p) (_p);
@@ -467,20 +467,20 @@ enum iavf_rx_desc_status_bits {
IAVF_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */
IAVF_RX_DESC_STATUS_LPBK_SHIFT = 14,
IAVF_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15,
- IAVF_RX_DESC_STATUS_RESERVED2_SHIFT = 16, /* 2 BITS */
+ IAVF_RX_DESC_STATUS_RESERVED_SHIFT = 16, /* 2 BITS */
IAVF_RX_DESC_STATUS_INT_UDP_0_SHIFT = 18,
IAVF_RX_DESC_STATUS_LAST /* this entry must be last!!! */
};
#define IAVF_RXD_QW1_STATUS_SHIFT 0
-#define IAVF_RXD_QW1_STATUS_MASK ((BIT(IAVF_RX_DESC_STATUS_LAST) - 1) << \
- IAVF_RXD_QW1_STATUS_SHIFT)
+#define IAVF_RXD_QW1_STATUS_MASK ((BIT(IAVF_RX_DESC_STATUS_LAST) - 1) \
+ << IAVF_RXD_QW1_STATUS_SHIFT)
-#define IAVF_RXD_QW1_STATUS_TSYNINDX_SHIFT IAVF_RX_DESC_STATUS_TSYNINDX_SHIFT
-#define IAVF_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \
- IAVF_RXD_QW1_STATUS_TSYNINDX_SHIFT)
+#define IAVF_RXD_QW1_STATUS_TSYNINDX_SHIFT IAVF_RX_DESC_STATUS_TSYNINDX_SHIFT
+#define IAVF_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \
+ IAVF_RXD_QW1_STATUS_TSYNINDX_SHIFT)
-#define IAVF_RXD_QW1_STATUS_TSYNVALID_SHIFT IAVF_RX_DESC_STATUS_TSYNVALID_SHIFT
+#define IAVF_RXD_QW1_STATUS_TSYNVALID_SHIFT IAVF_RX_DESC_STATUS_TSYNVALID_SHIFT
#define IAVF_RXD_QW1_STATUS_TSYNVALID_MASK BIT_ULL(IAVF_RXD_QW1_STATUS_TSYNVALID_SHIFT)
#define IAVF_RXD_QW1_STATUS_UMBCAST_SHIFT IAVF_RX_DESC_STATUS_UMBCAST
@@ -892,7 +892,8 @@ enum iavf_tx_ctx_desc_eipt_offload {
#define IAVF_TXD_CTX_GRE_TUNNELING (0x2ULL << IAVF_TXD_CTX_QW0_NATT_SHIFT)
#define IAVF_TXD_CTX_QW0_EIP_NOINC_SHIFT 11
-#define IAVF_TXD_CTX_QW0_EIP_NOINC_MASK BIT_ULL(IAVF_TXD_CTX_QW0_EIP_NOINC_SHIFT)
+#define IAVF_TXD_CTX_QW0_EIP_NOINC_MASK \
+ BIT_ULL(IAVF_TXD_CTX_QW0_EIP_NOINC_SHIFT)
#define IAVF_TXD_CTX_EIP_NOINC_IPID_CONST IAVF_TXD_CTX_QW0_EIP_NOINC_MASK
--
2.13.6
^ permalink raw reply [flat|nested] 21+ messages in thread* [dpdk-dev] [PATCH 10/17] net/iavf/base: increase max VSI count for VFs
2019-12-03 7:03 [dpdk-dev] [PATCH 00/17] iavf base code update Qi Zhang
` (8 preceding siblings ...)
2019-12-03 7:03 ` [dpdk-dev] [PATCH 09/17] net/iavf/base: adjust code indent Qi Zhang
@ 2019-12-03 7:03 ` Qi Zhang
2019-12-03 7:03 ` [dpdk-dev] [PATCH 11/17] net/iavf/base: fix command buffer memory free Qi Zhang
` (7 subsequent siblings)
17 siblings, 0 replies; 21+ messages in thread
From: Qi Zhang @ 2019-12-03 7:03 UTC (permalink / raw)
To: xiaolong.ye; +Cc: haiyue.wang, dev, Qi Zhang, Paul M Stillwell Jr
Change max VSI per VF from 3 to 4.
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/iavf/base/iavf_type.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/iavf/base/iavf_type.h b/drivers/net/iavf/base/iavf_type.h
index 6d63f4396..9fe5cb121 100644
--- a/drivers/net/iavf/base/iavf_type.h
+++ b/drivers/net/iavf/base/iavf_type.h
@@ -30,7 +30,7 @@
#define IAVF_MAX_PF_VSI 64
#define IAVF_MAX_PF_QP 128
#define IAVF_MAX_VSI_QP 16
-#define IAVF_MAX_VF_VSI 3
+#define IAVF_MAX_VF_VSI 4
#define IAVF_MAX_CHAINED_RX_BUFFERS 5
/* something less than 1 minute */
--
2.13.6
^ permalink raw reply [flat|nested] 21+ messages in thread* [dpdk-dev] [PATCH 11/17] net/iavf/base: fix command buffer memory free
2019-12-03 7:03 [dpdk-dev] [PATCH 00/17] iavf base code update Qi Zhang
` (9 preceding siblings ...)
2019-12-03 7:03 ` [dpdk-dev] [PATCH 10/17] net/iavf/base: increase max VSI count for VFs Qi Zhang
@ 2019-12-03 7:03 ` Qi Zhang
2019-12-03 7:03 ` [dpdk-dev] [PATCH 12/17] net/iavf/base: update FW API version for X722 Qi Zhang
` (6 subsequent siblings)
17 siblings, 0 replies; 21+ messages in thread
From: Qi Zhang @ 2019-12-03 7:03 UTC (permalink / raw)
To: xiaolong.ye
Cc: haiyue.wang, dev, Qi Zhang, stable, Maharajan Pandi Kumar,
Paul M Stillwell Jr
Allocated resources were not freed in the event of failure in
iavf_init_asq function. This patch gracefully handles all failures.
Fixes: e5b2a9e957e7 ("net/avf/base: add base code for avf PMD")
Cc: stable@dpdk.org
Signed-off-by: Maharajan Pandi Kumar <pandi.maharajan@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/iavf/base/iavf_adminq.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/net/iavf/base/iavf_adminq.c b/drivers/net/iavf/base/iavf_adminq.c
index ef352ac4c..298e77277 100644
--- a/drivers/net/iavf/base/iavf_adminq.c
+++ b/drivers/net/iavf/base/iavf_adminq.c
@@ -82,6 +82,7 @@ enum iavf_status iavf_alloc_adminq_arq_ring(struct iavf_hw *hw)
**/
void iavf_free_adminq_asq(struct iavf_hw *hw)
{
+ iavf_free_virt_mem(hw, &hw->aq.asq.cmd_buf);
iavf_free_dma_mem(hw, &hw->aq.asq.desc_buf);
}
@@ -353,7 +354,7 @@ enum iavf_status iavf_init_asq(struct iavf_hw *hw)
/* initialize base registers */
ret_code = iavf_config_asq_regs(hw);
if (ret_code != IAVF_SUCCESS)
- goto init_adminq_free_rings;
+ goto init_config_regs;
/* success! */
hw->aq.asq.count = hw->aq.num_asq_entries;
@@ -361,6 +362,10 @@ enum iavf_status iavf_init_asq(struct iavf_hw *hw)
init_adminq_free_rings:
iavf_free_adminq_asq(hw);
+ return ret_code;
+
+init_config_regs:
+ iavf_free_asq_bufs(hw);
init_adminq_exit:
return ret_code;
--
2.13.6
^ permalink raw reply [flat|nested] 21+ messages in thread* [dpdk-dev] [PATCH 12/17] net/iavf/base: update FW API version for X722
2019-12-03 7:03 [dpdk-dev] [PATCH 00/17] iavf base code update Qi Zhang
` (10 preceding siblings ...)
2019-12-03 7:03 ` [dpdk-dev] [PATCH 11/17] net/iavf/base: fix command buffer memory free Qi Zhang
@ 2019-12-03 7:03 ` Qi Zhang
2019-12-03 7:03 ` [dpdk-dev] [PATCH 13/17] net/iavf/base: add more link speed support Qi Zhang
` (5 subsequent siblings)
17 siblings, 0 replies; 21+ messages in thread
From: Qi Zhang @ 2019-12-03 7:03 UTC (permalink / raw)
To: xiaolong.ye; +Cc: haiyue.wang, dev, Qi Zhang, Paul M Stillwell Jr
Update FW API version from 1.5 to 1.6 for X722
Also added NVM update related APIs.
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/iavf/base/iavf_adminq_cmd.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/net/iavf/base/iavf_adminq_cmd.h b/drivers/net/iavf/base/iavf_adminq_cmd.h
index b0ee0b082..f7cfc0dda 100644
--- a/drivers/net/iavf/base/iavf_adminq_cmd.h
+++ b/drivers/net/iavf/base/iavf_adminq_cmd.h
@@ -12,7 +12,7 @@
*/
#define IAVF_FW_API_VERSION_MAJOR 0x0001
-#define IAVF_FW_API_VERSION_MINOR_X722 0x0005
+#define IAVF_FW_API_VERSION_MINOR_X722 0x0006
#define IAVF_FW_API_VERSION_MINOR_X710 0x0007
#define IAVF_FW_MINOR_VERSION(_h) ((_h)->mac.type == IAVF_MAC_XL710 ? \
@@ -21,6 +21,8 @@
/* API version 1.7 implements additional link and PHY-specific APIs */
#define IAVF_MINOR_VER_GET_LINK_INFO_XL710 0x0007
+/* API version 1.6 for X722 devices adds ability to stop FW LLDP agent */
+#define IAVF_MINOR_VER_FW_LLDP_STOPPABLE_X722 0x0006
struct iavf_aq_desc {
__le16 flags;
--
2.13.6
^ permalink raw reply [flat|nested] 21+ messages in thread* [dpdk-dev] [PATCH 13/17] net/iavf/base: add more link speed support
2019-12-03 7:03 [dpdk-dev] [PATCH 00/17] iavf base code update Qi Zhang
` (11 preceding siblings ...)
2019-12-03 7:03 ` [dpdk-dev] [PATCH 12/17] net/iavf/base: update FW API version for X722 Qi Zhang
@ 2019-12-03 7:03 ` Qi Zhang
2019-12-03 7:03 ` [dpdk-dev] [PATCH 14/17] net/iavf/base: update copyright date Qi Zhang
` (4 subsequent siblings)
17 siblings, 0 replies; 21+ messages in thread
From: Qi Zhang @ 2019-12-03 7:03 UTC (permalink / raw)
To: xiaolong.ye; +Cc: haiyue.wang, dev, Qi Zhang, Paul M Stillwell Jr
Add 2.5G and 5G link speed support.
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/iavf/base/iavf_adminq_cmd.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/net/iavf/base/iavf_adminq_cmd.h b/drivers/net/iavf/base/iavf_adminq_cmd.h
index f7cfc0dda..fa0cb23ac 100644
--- a/drivers/net/iavf/base/iavf_adminq_cmd.h
+++ b/drivers/net/iavf/base/iavf_adminq_cmd.h
@@ -471,17 +471,21 @@ struct iavf_aqc_get_veb_parameters_completion {
IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_veb_parameters_completion);
+#define IAVF_LINK_SPEED_2_5GB_SHIFT 0x0
#define IAVF_LINK_SPEED_100MB_SHIFT 0x1
#define IAVF_LINK_SPEED_1000MB_SHIFT 0x2
#define IAVF_LINK_SPEED_10GB_SHIFT 0x3
#define IAVF_LINK_SPEED_40GB_SHIFT 0x4
#define IAVF_LINK_SPEED_20GB_SHIFT 0x5
#define IAVF_LINK_SPEED_25GB_SHIFT 0x6
+#define IAVF_LINK_SPEED_5GB_SHIFT 0x7
enum iavf_aq_link_speed {
IAVF_LINK_SPEED_UNKNOWN = 0,
IAVF_LINK_SPEED_100MB = (1 << IAVF_LINK_SPEED_100MB_SHIFT),
IAVF_LINK_SPEED_1GB = (1 << IAVF_LINK_SPEED_1000MB_SHIFT),
+ IAVF_LINK_SPEED_2_5GB = (1 << IAVF_LINK_SPEED_2_5GB_SHIFT),
+ IAVF_LINK_SPEED_5GB = (1 << IAVF_LINK_SPEED_5GB_SHIFT),
IAVF_LINK_SPEED_10GB = (1 << IAVF_LINK_SPEED_10GB_SHIFT),
IAVF_LINK_SPEED_40GB = (1 << IAVF_LINK_SPEED_40GB_SHIFT),
IAVF_LINK_SPEED_20GB = (1 << IAVF_LINK_SPEED_20GB_SHIFT),
--
2.13.6
^ permalink raw reply [flat|nested] 21+ messages in thread* [dpdk-dev] [PATCH 14/17] net/iavf/base: update copyright date
2019-12-03 7:03 [dpdk-dev] [PATCH 00/17] iavf base code update Qi Zhang
` (12 preceding siblings ...)
2019-12-03 7:03 ` [dpdk-dev] [PATCH 13/17] net/iavf/base: add more link speed support Qi Zhang
@ 2019-12-03 7:03 ` Qi Zhang
2019-12-03 7:03 ` [dpdk-dev] [PATCH 15/17] net/iavf/base: fix send adminq return value Qi Zhang
` (3 subsequent siblings)
17 siblings, 0 replies; 21+ messages in thread
From: Qi Zhang @ 2019-12-03 7:03 UTC (permalink / raw)
To: xiaolong.ye; +Cc: haiyue.wang, dev, Qi Zhang, Paul M Stillwell Jr
Update copyright date to cover 2019.
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/iavf/base/iavf_adminq.c | 2 +-
drivers/net/iavf/base/iavf_adminq.h | 2 +-
drivers/net/iavf/base/iavf_adminq_cmd.h | 2 +-
drivers/net/iavf/base/iavf_alloc.h | 2 +-
drivers/net/iavf/base/iavf_common.c | 3 +--
drivers/net/iavf/base/iavf_devids.h | 2 +-
drivers/net/iavf/base/iavf_prototype.h | 2 +-
drivers/net/iavf/base/iavf_register.h | 2 +-
drivers/net/iavf/base/iavf_status.h | 2 +-
drivers/net/iavf/base/iavf_type.h | 2 +-
drivers/net/iavf/base/virtchnl.h | 2 +-
11 files changed, 11 insertions(+), 12 deletions(-)
diff --git a/drivers/net/iavf/base/iavf_adminq.c b/drivers/net/iavf/base/iavf_adminq.c
index 298e77277..0a5b2b281 100644
--- a/drivers/net/iavf/base/iavf_adminq.c
+++ b/drivers/net/iavf/base/iavf_adminq.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2013 - 2015 Intel Corporation
+ * Copyright(c) 2001-2019
*/
#include "iavf_status.h"
diff --git a/drivers/net/iavf/base/iavf_adminq.h b/drivers/net/iavf/base/iavf_adminq.h
index bdc5e0187..42532dca8 100644
--- a/drivers/net/iavf/base/iavf_adminq.h
+++ b/drivers/net/iavf/base/iavf_adminq.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2013 - 2015 Intel Corporation
+ * Copyright(c) 2001-2019
*/
#ifndef _IAVF_ADMINQ_H_
diff --git a/drivers/net/iavf/base/iavf_adminq_cmd.h b/drivers/net/iavf/base/iavf_adminq_cmd.h
index fa0cb23ac..dc8644a82 100644
--- a/drivers/net/iavf/base/iavf_adminq_cmd.h
+++ b/drivers/net/iavf/base/iavf_adminq_cmd.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2013 - 2015 Intel Corporation
+ * Copyright(c) 2001-2019
*/
#ifndef _IAVF_ADMINQ_CMD_H_
diff --git a/drivers/net/iavf/base/iavf_alloc.h b/drivers/net/iavf/base/iavf_alloc.h
index a409bb099..45355d5d8 100644
--- a/drivers/net/iavf/base/iavf_alloc.h
+++ b/drivers/net/iavf/base/iavf_alloc.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2013 - 2015 Intel Corporation
+ * Copyright(c) 2001-2019
*/
#ifndef _IAVF_ALLOC_H_
diff --git a/drivers/net/iavf/base/iavf_common.c b/drivers/net/iavf/base/iavf_common.c
index c2c1fd1e4..a8c252825 100644
--- a/drivers/net/iavf/base/iavf_common.c
+++ b/drivers/net/iavf/base/iavf_common.c
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2013 - 2015 Intel Corporation
+ * Copyright(c) 2001-2019
*/
#include "iavf_type.h"
@@ -7,7 +7,6 @@
#include "iavf_prototype.h"
#include "virtchnl.h"
-
/**
* iavf_set_mac_type - Sets MAC type
* @hw: pointer to the HW structure
diff --git a/drivers/net/iavf/base/iavf_devids.h b/drivers/net/iavf/base/iavf_devids.h
index cd92631f4..c02122794 100644
--- a/drivers/net/iavf/base/iavf_devids.h
+++ b/drivers/net/iavf/base/iavf_devids.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2013 - 2015 Intel Corporation
+ * Copyright(c) 2001-2019
*/
#ifndef _IAVF_DEVIDS_H_
diff --git a/drivers/net/iavf/base/iavf_prototype.h b/drivers/net/iavf/base/iavf_prototype.h
index a5d0b0073..3ea645c22 100644
--- a/drivers/net/iavf/base/iavf_prototype.h
+++ b/drivers/net/iavf/base/iavf_prototype.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2013 - 2015 Intel Corporation
+ * Copyright(c) 2001-2019
*/
#ifndef _IAVF_PROTOTYPE_H_
diff --git a/drivers/net/iavf/base/iavf_register.h b/drivers/net/iavf/base/iavf_register.h
index 7d2b20710..09a2af0c9 100644
--- a/drivers/net/iavf/base/iavf_register.h
+++ b/drivers/net/iavf/base/iavf_register.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2013 - 2015 Intel Corporation
+ * Copyright(c) 2001-2019
*/
#ifndef _IAVF_REGISTER_H_
diff --git a/drivers/net/iavf/base/iavf_status.h b/drivers/net/iavf/base/iavf_status.h
index 32b391589..e57e53c06 100644
--- a/drivers/net/iavf/base/iavf_status.h
+++ b/drivers/net/iavf/base/iavf_status.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2013 - 2015 Intel Corporation
+ * Copyright(c) 2001-2019
*/
#ifndef _IAVF_STATUS_H_
diff --git a/drivers/net/iavf/base/iavf_type.h b/drivers/net/iavf/base/iavf_type.h
index 9fe5cb121..fb175e8a6 100644
--- a/drivers/net/iavf/base/iavf_type.h
+++ b/drivers/net/iavf/base/iavf_type.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2013 - 2015 Intel Corporation
+ * Copyright(c) 2001-2019
*/
#ifndef _IAVF_TYPE_H_
diff --git a/drivers/net/iavf/base/virtchnl.h b/drivers/net/iavf/base/virtchnl.h
index 1604f19e3..2fbbb9e28 100644
--- a/drivers/net/iavf/base/virtchnl.h
+++ b/drivers/net/iavf/base/virtchnl.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2013 - 2015 Intel Corporation
+ * Copyright(c) 2001-2019
*/
#ifndef _VIRTCHNL_H_
--
2.13.6
^ permalink raw reply [flat|nested] 21+ messages in thread* [dpdk-dev] [PATCH 15/17] net/iavf/base: fix send adminq return value
2019-12-03 7:03 [dpdk-dev] [PATCH 00/17] iavf base code update Qi Zhang
` (13 preceding siblings ...)
2019-12-03 7:03 ` [dpdk-dev] [PATCH 14/17] net/iavf/base: update copyright date Qi Zhang
@ 2019-12-03 7:03 ` Qi Zhang
2020-01-02 2:48 ` Yang, Qiming
2019-12-03 7:03 ` [dpdk-dev] [PATCH 16/17] net/iavf: move device state flag Qi Zhang
` (2 subsequent siblings)
17 siblings, 1 reply; 21+ messages in thread
From: Qi Zhang @ 2019-12-03 7:03 UTC (permalink / raw)
To: xiaolong.ye; +Cc: haiyue.wang, dev, Qi Zhang, Paul M Stillwell Jr
When send a adminq, if get IAVF_AQ_RC_BUSY, we should return
IAVF_ERR_NOT_READY.
Fixes: e5b2a9e957e7 ("net/avf/base: add base code for avf PMD")
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/iavf/base/iavf_adminq.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/net/iavf/base/iavf_adminq.c b/drivers/net/iavf/base/iavf_adminq.c
index 0a5b2b281..c1668d228 100644
--- a/drivers/net/iavf/base/iavf_adminq.c
+++ b/drivers/net/iavf/base/iavf_adminq.c
@@ -803,6 +803,8 @@ enum iavf_status iavf_asq_send_command(struct iavf_hw *hw,
cmd_completed = true;
if ((enum iavf_admin_queue_err)retval == IAVF_AQ_RC_OK)
status = IAVF_SUCCESS;
+ else if ((enum iavf_admin_queue_err)retval == IAVF_AQ_RC_EBUSY)
+ status = IAVF_ERR_NOT_READY;
else
status = IAVF_ERR_ADMIN_QUEUE_ERROR;
hw->aq.asq_last_status = (enum iavf_admin_queue_err)retval;
--
2.13.6
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [dpdk-dev] [PATCH 15/17] net/iavf/base: fix send adminq return value
2019-12-03 7:03 ` [dpdk-dev] [PATCH 15/17] net/iavf/base: fix send adminq return value Qi Zhang
@ 2020-01-02 2:48 ` Yang, Qiming
0 siblings, 0 replies; 21+ messages in thread
From: Yang, Qiming @ 2020-01-02 2:48 UTC (permalink / raw)
To: Zhang, Qi Z, Ye, Xiaolong
Cc: Wang, Haiyue, dev, Zhang, Qi Z, Stillwell Jr, Paul M
> -----Original Message-----
> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Qi Zhang
> Sent: Tuesday, December 3, 2019 3:03 PM
> To: Ye, Xiaolong <xiaolong.ye@intel.com>
> Cc: Wang, Haiyue <haiyue.wang@intel.com>; dev@dpdk.org; Zhang, Qi Z
> <qi.z.zhang@intel.com>; Stillwell Jr, Paul M <paul.m.stillwell.jr@intel.com>
> Subject: [dpdk-dev] [PATCH 15/17] net/iavf/base: fix send adminq return
> value
>
> When send a adminq, if get IAVF_AQ_RC_BUSY, we should return
> IAVF_ERR_NOT_READY.
>
> Fixes: e5b2a9e957e7 ("net/avf/base: add base code for avf PMD")
>
Lack of CC stable
> Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
> Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
> ---
> drivers/net/iavf/base/iavf_adminq.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/net/iavf/base/iavf_adminq.c
> b/drivers/net/iavf/base/iavf_adminq.c
> index 0a5b2b281..c1668d228 100644
> --- a/drivers/net/iavf/base/iavf_adminq.c
> +++ b/drivers/net/iavf/base/iavf_adminq.c
> @@ -803,6 +803,8 @@ enum iavf_status iavf_asq_send_command(struct
> iavf_hw *hw,
> cmd_completed = true;
> if ((enum iavf_admin_queue_err)retval == IAVF_AQ_RC_OK)
> status = IAVF_SUCCESS;
> + else if ((enum iavf_admin_queue_err)retval ==
> IAVF_AQ_RC_EBUSY)
> + status = IAVF_ERR_NOT_READY;
> else
> status = IAVF_ERR_ADMIN_QUEUE_ERROR;
> hw->aq.asq_last_status = (enum
> iavf_admin_queue_err)retval;
> --
> 2.13.6
^ permalink raw reply [flat|nested] 21+ messages in thread
* [dpdk-dev] [PATCH 16/17] net/iavf: move device state flag
2019-12-03 7:03 [dpdk-dev] [PATCH 00/17] iavf base code update Qi Zhang
` (14 preceding siblings ...)
2019-12-03 7:03 ` [dpdk-dev] [PATCH 15/17] net/iavf/base: fix send adminq return value Qi Zhang
@ 2019-12-03 7:03 ` Qi Zhang
2019-12-03 7:03 ` [dpdk-dev] [PATCH 17/17] net/ice/base: update version info Qi Zhang
2020-01-02 2:50 ` [dpdk-dev] [PATCH 00/17] iavf base code update Yang, Qiming
17 siblings, 0 replies; 21+ messages in thread
From: Qi Zhang @ 2019-12-03 7:03 UTC (permalink / raw)
To: xiaolong.ye; +Cc: haiyue.wang, dev, Qi Zhang
Move device state flag from ice_hw to ice_adatper since it should
not be a part of base code.
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/iavf/base/iavf_type.h | 1 -
drivers/net/iavf/iavf.h | 1 +
drivers/net/iavf/iavf_ethdev.c | 13 +++++--------
3 files changed, 6 insertions(+), 9 deletions(-)
diff --git a/drivers/net/iavf/base/iavf_type.h b/drivers/net/iavf/base/iavf_type.h
index fb175e8a6..6f85f8c04 100644
--- a/drivers/net/iavf/base/iavf_type.h
+++ b/drivers/net/iavf/base/iavf_type.h
@@ -332,7 +332,6 @@ struct iavf_hw {
u16 subsystem_device_id;
u16 subsystem_vendor_id;
u8 revision_id;
- bool adapter_stopped;
/* capabilities for entire device and PCI func */
struct iavf_hw_capabilities dev_caps;
diff --git a/drivers/net/iavf/iavf.h b/drivers/net/iavf/iavf.h
index bbd4d75d0..77b706893 100644
--- a/drivers/net/iavf/iavf.h
+++ b/drivers/net/iavf/iavf.h
@@ -127,6 +127,7 @@ struct iavf_adapter {
/* For vector PMD */
bool rx_vec_allowed;
bool tx_vec_allowed;
+ bool stopped;
};
/* IAVF_DEV_PRIVATE_TO */
diff --git a/drivers/net/iavf/iavf_ethdev.c b/drivers/net/iavf/iavf_ethdev.c
index 39faf7fac..73927f1f8 100644
--- a/drivers/net/iavf/iavf_ethdev.c
+++ b/drivers/net/iavf/iavf_ethdev.c
@@ -421,12 +421,11 @@ iavf_dev_start(struct rte_eth_dev *dev)
struct iavf_adapter *adapter =
IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
- struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
struct rte_intr_handle *intr_handle = dev->intr_handle;
PMD_INIT_FUNC_TRACE();
- hw->adapter_stopped = 0;
+ adapter->stopped = 0;
vf->max_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
vf->num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,
@@ -481,12 +480,11 @@ iavf_dev_stop(struct rte_eth_dev *dev)
{
struct iavf_adapter *adapter =
IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
- struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
struct rte_intr_handle *intr_handle = dev->intr_handle;
PMD_INIT_FUNC_TRACE();
- if (hw->adapter_stopped == 1)
+ if (adapter->stopped == 1)
return;
iavf_stop_queues(dev);
@@ -501,7 +499,7 @@ iavf_dev_stop(struct rte_eth_dev *dev)
/* remove all mac addrs */
iavf_add_del_all_mac_addr(adapter, FALSE);
- hw->adapter_stopped = 1;
+ adapter->stopped = 1;
}
static int
@@ -1333,6 +1331,7 @@ iavf_dev_init(struct rte_eth_dev *eth_dev)
hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
hw->back = IAVF_DEV_PRIVATE_TO_ADAPTER(eth_dev->data->dev_private);
adapter->eth_dev = eth_dev;
+ adapter->stopped = 1;
if (iavf_init_vf(eth_dev) != 0) {
PMD_INIT_LOG(ERR, "Init vf failed");
@@ -1393,7 +1392,6 @@ static int
iavf_dev_uninit(struct rte_eth_dev *dev)
{
struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
- struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
if (rte_eal_process_type() != RTE_PROC_PRIMARY)
return -EPERM;
@@ -1401,8 +1399,7 @@ iavf_dev_uninit(struct rte_eth_dev *dev)
dev->dev_ops = NULL;
dev->rx_pkt_burst = NULL;
dev->tx_pkt_burst = NULL;
- if (hw->adapter_stopped == 0)
- iavf_dev_close(dev);
+ iavf_dev_close(dev);
rte_free(vf->vf_res);
vf->vsi_res = NULL;
--
2.13.6
^ permalink raw reply [flat|nested] 21+ messages in thread* [dpdk-dev] [PATCH 17/17] net/ice/base: update version info
2019-12-03 7:03 [dpdk-dev] [PATCH 00/17] iavf base code update Qi Zhang
` (15 preceding siblings ...)
2019-12-03 7:03 ` [dpdk-dev] [PATCH 16/17] net/iavf: move device state flag Qi Zhang
@ 2019-12-03 7:03 ` Qi Zhang
2020-01-02 2:50 ` [dpdk-dev] [PATCH 00/17] iavf base code update Yang, Qiming
17 siblings, 0 replies; 21+ messages in thread
From: Qi Zhang @ 2019-12-03 7:03 UTC (permalink / raw)
To: xiaolong.ye; +Cc: haiyue.wang, dev, Qi Zhang
Update base code version info in readme.
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/net/iavf/base/README | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/iavf/base/README b/drivers/net/iavf/base/README
index f57e1048f..e8c49c36f 100644
--- a/drivers/net/iavf/base/README
+++ b/drivers/net/iavf/base/README
@@ -1,12 +1,12 @@
/* SPDX-License-Identifier: BSD-3-Clause
- * Copyright(c) 2017 Intel Corporation
+ * Copyright(c) 2019 Intel Corporation
*/
Intel® IAVF driver
=================
This directory contains source code of FreeBSD IAVF driver of version
-cid-avf.2018.01.02.tar.gz released by the team which develops
+cid-avf.2019.08.19.tar.gz released by the team which develops
basic drivers for any IAVF NIC. The directory of base/ contains the
original source package.
--
2.13.6
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [dpdk-dev] [PATCH 00/17] iavf base code update
2019-12-03 7:03 [dpdk-dev] [PATCH 00/17] iavf base code update Qi Zhang
` (16 preceding siblings ...)
2019-12-03 7:03 ` [dpdk-dev] [PATCH 17/17] net/ice/base: update version info Qi Zhang
@ 2020-01-02 2:50 ` Yang, Qiming
2020-01-02 3:14 ` Ye Xiaolong
17 siblings, 1 reply; 21+ messages in thread
From: Yang, Qiming @ 2020-01-02 2:50 UTC (permalink / raw)
To: Zhang, Qi Z, Ye, Xiaolong; +Cc: Wang, Haiyue, dev, Zhang, Qi Z
> -----Original Message-----
> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Qi Zhang
> Sent: Tuesday, December 3, 2019 3:03 PM
> To: Ye, Xiaolong <xiaolong.ye@intel.com>
> Cc: Wang, Haiyue <haiyue.wang@intel.com>; dev@dpdk.org; Zhang, Qi Z
> <qi.z.zhang@intel.com>
> Subject: [dpdk-dev] [PATCH 00/17] iavf base code update
>
> Update iavf base code to latest.
>
> main changes
> 1) Add more supported device ID
> 2) update virtual channel to latest AVF spec.
> 3) code clean.
> 4) couple bug fixes
>
> Qi Zhang (17):
> net/iavf/base: remove unnecessary header file
> net/iavf/base: rename error code enum
> net/iavf/base: rename register macro
> net/iavf/base: update device id
> net/iavf/base: remove unused code
> net/iavf/base: remove unnecessary compile option
> net/iavf/base: rename functions
> net/iavf/base: update virtual channel
> net/iavf/base: adjust code indent
> net/iavf/base: increase max VSI count for VFs
> net/iavf/base: fix command buffer memory free
> net/iavf/base: update FW API version for X722
> net/iavf/base: add more link speed support
> net/iavf/base: update copyright date
> net/iavf/base: fix send adminq return value
> net/iavf: move device state flag
> net/ice/base: update version info
>
> drivers/net/iavf/base/README | 4 +-
> drivers/net/iavf/base/iavf_adminq.c | 121 +-
> drivers/net/iavf/base/iavf_adminq.h | 45 +-
> drivers/net/iavf/base/iavf_adminq_cmd.h | 2354 ++-----------------------------
> drivers/net/iavf/base/iavf_alloc.h | 24 +-
> drivers/net/iavf/base/iavf_common.c | 879 +-----------
> drivers/net/iavf/base/iavf_devids.h | 7 +-
> drivers/net/iavf/base/iavf_hmc.h | 216 ---
> drivers/net/iavf/base/iavf_lan_hmc.h | 171 ---
> drivers/net/iavf/base/iavf_osdep.h | 2 +-
> drivers/net/iavf/base/iavf_prototype.h | 149 +-
> drivers/net/iavf/base/iavf_register.h | 390 ++---
> drivers/net/iavf/base/iavf_status.h | 4 +-
> drivers/net/iavf/base/iavf_type.h | 1144 ++-------------
> drivers/net/iavf/base/virtchnl.h | 345 +++--
> drivers/net/iavf/iavf.h | 1 +
> drivers/net/iavf/iavf_ethdev.c | 80 +-
> drivers/net/iavf/iavf_vchnl.c | 10 +-
> 18 files changed, 692 insertions(+), 5254 deletions(-) delete mode 100644
> drivers/net/iavf/base/iavf_hmc.h delete mode 100644
> drivers/net/iavf/base/iavf_lan_hmc.h
>
> --
> 2.13.6
Only one small comments for patch 15/17.
Acked-by: Qiming Yang <qiming.yang@intel.com>
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [dpdk-dev] [PATCH 00/17] iavf base code update
2020-01-02 2:50 ` [dpdk-dev] [PATCH 00/17] iavf base code update Yang, Qiming
@ 2020-01-02 3:14 ` Ye Xiaolong
0 siblings, 0 replies; 21+ messages in thread
From: Ye Xiaolong @ 2020-01-02 3:14 UTC (permalink / raw)
To: Yang, Qiming; +Cc: Zhang, Qi Z, Wang, Haiyue, dev
On 01/02, Yang, Qiming wrote:
>
>
>> -----Original Message-----
>> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Qi Zhang
>> Sent: Tuesday, December 3, 2019 3:03 PM
>> To: Ye, Xiaolong <xiaolong.ye@intel.com>
>> Cc: Wang, Haiyue <haiyue.wang@intel.com>; dev@dpdk.org; Zhang, Qi Z
>> <qi.z.zhang@intel.com>
>> Subject: [dpdk-dev] [PATCH 00/17] iavf base code update
>>
>> Update iavf base code to latest.
>>
>> main changes
>> 1) Add more supported device ID
>> 2) update virtual channel to latest AVF spec.
>> 3) code clean.
>> 4) couple bug fixes
>>
>> Qi Zhang (17):
>> net/iavf/base: remove unnecessary header file
>> net/iavf/base: rename error code enum
>> net/iavf/base: rename register macro
>> net/iavf/base: update device id
>> net/iavf/base: remove unused code
>> net/iavf/base: remove unnecessary compile option
>> net/iavf/base: rename functions
>> net/iavf/base: update virtual channel
>> net/iavf/base: adjust code indent
>> net/iavf/base: increase max VSI count for VFs
>> net/iavf/base: fix command buffer memory free
>> net/iavf/base: update FW API version for X722
>> net/iavf/base: add more link speed support
>> net/iavf/base: update copyright date
>> net/iavf/base: fix send adminq return value
>> net/iavf: move device state flag
>> net/ice/base: update version info
>>
>> drivers/net/iavf/base/README | 4 +-
>> drivers/net/iavf/base/iavf_adminq.c | 121 +-
>> drivers/net/iavf/base/iavf_adminq.h | 45 +-
>> drivers/net/iavf/base/iavf_adminq_cmd.h | 2354 ++-----------------------------
>> drivers/net/iavf/base/iavf_alloc.h | 24 +-
>> drivers/net/iavf/base/iavf_common.c | 879 +-----------
>> drivers/net/iavf/base/iavf_devids.h | 7 +-
>> drivers/net/iavf/base/iavf_hmc.h | 216 ---
>> drivers/net/iavf/base/iavf_lan_hmc.h | 171 ---
>> drivers/net/iavf/base/iavf_osdep.h | 2 +-
>> drivers/net/iavf/base/iavf_prototype.h | 149 +-
>> drivers/net/iavf/base/iavf_register.h | 390 ++---
>> drivers/net/iavf/base/iavf_status.h | 4 +-
>> drivers/net/iavf/base/iavf_type.h | 1144 ++-------------
>> drivers/net/iavf/base/virtchnl.h | 345 +++--
>> drivers/net/iavf/iavf.h | 1 +
>> drivers/net/iavf/iavf_ethdev.c | 80 +-
>> drivers/net/iavf/iavf_vchnl.c | 10 +-
>> 18 files changed, 692 insertions(+), 5254 deletions(-) delete mode 100644
>> drivers/net/iavf/base/iavf_hmc.h delete mode 100644
>> drivers/net/iavf/base/iavf_lan_hmc.h
>>
>> --
>> 2.13.6
>
>Only one small comments for patch 15/17.
Fixed it while merging.
>
>Acked-by: Qiming Yang <qiming.yang@intel.com>
Series applied to dpdk-next-net-intel, Thanks.
^ permalink raw reply [flat|nested] 21+ messages in thread