From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 45760A04F7; Fri, 20 Dec 2019 09:17:28 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 90F041252; Fri, 20 Dec 2019 09:17:27 +0100 (CET) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id BBC13F90 for ; Fri, 20 Dec 2019 09:17:25 +0100 (CET) X-Amp-Result: UNKNOWN X-Amp-Original-Verdict: FILE UNKNOWN X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 20 Dec 2019 00:17:24 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,335,1571727600"; d="scan'208";a="298957447" Received: from dpdk-virtio-tbie-2.sh.intel.com (HELO ___) ([10.67.104.74]) by orsmga001.jf.intel.com with ESMTP; 20 Dec 2019 00:17:21 -0800 Date: Fri, 20 Dec 2019 16:17:39 +0800 From: Tiwei Bie To: Gavin Hu Cc: dev@dpdk.org, nd@arm.com, david.marchand@redhat.com, thomas@monjalon.net, rasland@mellanox.com, maxime.coquelin@redhat.com, hemant.agrawal@nxp.com, jerinj@marvell.com, pbhagavatula@marvell.com, Honnappa.Nagarahalli@arm.com, ruifeng.wang@arm.com, phil.yang@arm.com, joyce.kong@arm.com, steve.capper@arm.com Message-ID: <20191220081739.GA511131@___> References: <1571758074-16445-1-git-send-email-gavin.hu@arm.com> <1576811391-19131-3-git-send-email-gavin.hu@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <1576811391-19131-3-git-send-email-gavin.hu@arm.com> User-Agent: Mutt/1.9.4 (2018-02-28) Subject: Re: [dpdk-dev] [PATCH v2 2/3] net/virtio: virtual PCI requires smp barriers X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Fri, Dec 20, 2019 at 11:09:50AM +0800, Gavin Hu wrote: > Other than real PCI reads and writes to the device memory requiring > the io barriers, virtual pci memories are normal memory in the smp > configuration, which requires the smp barriers. > > Since the smp barriers and io barriers are identical on x86 and PPC, > this change has only effect on aarch64. > > As far as peripheral coherence order for ‘virtual’ devices, the arch > intent is that the Hypervisor view of things takes precedence – since > translations are made in holistic manner as the full stage1+stage2 > regime, there is no such thing as a transaction taking on “EL1” > mapping as far as ordering. If the Hypervisor maps stage2 as Normal > but the OS at EL1 maps it as Device-nGnRE, then it’s Normal memory and > follows the ordering rules for Normal memory. > > Signed-off-by: Gavin Hu > --- > drivers/net/virtio/virtio_pci.c | 108 +++++++++++++++++++++++++++++----------- > 1 file changed, 78 insertions(+), 30 deletions(-) > > diff --git a/drivers/net/virtio/virtio_pci.c b/drivers/net/virtio/virtio_pci.c > index 4468e89..64aa0a0 100644 > --- a/drivers/net/virtio/virtio_pci.c > +++ b/drivers/net/virtio/virtio_pci.c > @@ -24,6 +24,54 @@ > #define PCI_CAP_ID_VNDR 0x09 > #define PCI_CAP_ID_MSIX 0x11 > > +static __rte_always_inline uint8_t > +virtio_pci_read8(const volatile void *addr) > +{ > + uint8_t val; > + val = rte_read8_relaxed(addr); > + rte_smp_rmb(); > + return val; > +} > + > +static __rte_always_inline uint16_t > +virtio_pci_read16(const volatile void *addr) > +{ > + uint16_t val; > + val = rte_read16_relaxed(addr); > + rte_smp_rmb(); > + return val; > +} > + > +static __rte_always_inline uint32_t > +virtio_pci_read32(const volatile void *addr) > +{ > + uint32_t val; > + val = rte_read32_relaxed(addr); > + rte_smp_rmb(); > + return val; > +} > + > +static __rte_always_inline void > +virtio_pci_write8(uint8_t value, volatile void *addr) > +{ > + rte_smp_wmb(); > + rte_write8_relaxed(value, addr); > +} > + > +static __rte_always_inline void > +virtio_pci_write16(uint16_t value, volatile void *addr) > +{ > + rte_smp_wmb(); > + rte_write16_relaxed(value, addr); > +} > + > +static __rte_always_inline void > +virtio_pci_write32(uint32_t value, volatile void *addr) > +{ > + rte_smp_wmb(); > + rte_write32_relaxed(value, addr); > +} We can't assume that virtio device is software running in an SMP configuration unless VIRTIO_F_ORDER_PLATFORM isn't negotiated. https://github.com/oasis-tcs/virtio-spec/blob/94520b3af19c/content.tex#L5788 > +