[dpdk-dev] [PATCH v2 01/12] net/ice/base: whitelist register for NVM access

[Qi Zhang <qi.z.zhang@intel.com>]

Allow tools to access register offset 0xB8188 (GLGEN_RSTAT) for
NVMUpdate operations.  This is a read-only register, so risk of other
issues stemming from this change is low. Even so, update the write
command to prevent and reject any commands which attempt to write to
this register, just like we do for GL_HICR_EN.

Signed-off-by: Jeb Cramer <jeb.j.cramer@intel.com>
Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>
Signed-off-by: Qi Zhang <qi.z.zhang@intel.com>
Acked-by: Qiming Yang <qiming.yang@intel.com>
---
 drivers/net/ice/base/ice_nvm.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/net/ice/base/ice_nvm.c b/drivers/net/ice/base/ice_nvm.c
index 1dbfc2dcc..2d92524f2 100644
--- a/drivers/net/ice/base/ice_nvm.c
+++ b/drivers/net/ice/base/ice_nvm.c
@@ -504,6 +504,7 @@ ice_validate_nvm_rw_reg(struct ice_nvm_access_cmd *cmd)
 	case GL_FWSTS:
 	case GL_MNG_FWSM:
 	case GLGEN_CSR_DEBUG_C:
+	case GLGEN_RSTAT:
 	case GLPCI_LBARCTRL:
 	case GLNVM_GENS:
 	case GLNVM_FLA:
@@ -579,9 +580,14 @@ ice_nvm_access_write(struct ice_hw *hw, struct ice_nvm_access_cmd *cmd,
 	if (status)
 		return status;
 
-	/* The HICR_EN register is read-only */
-	if (cmd->offset == GL_HICR_EN)
+	/* Reject requests to write to read-only registers */
+	switch (cmd->offset) {
+	case GL_HICR_EN:
+	case GLGEN_RSTAT:
 		return ICE_ERR_OUT_OF_RANGE;
+	default:
+		break;
+	}
 
 	ice_debug(hw, ICE_DBG_NVM,
 		  "NVM access: writing register %08x with value %08x\n",
-- 
2.13.6