From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 36802A0528; Mon, 20 Jan 2020 13:25:02 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 55DB21515; Mon, 20 Jan 2020 13:25:01 +0100 (CET) Received: from proxy.6wind.com (host.76.145.23.62.rev.coltfrance.com [62.23.145.76]) by dpdk.org (Postfix) with ESMTP id 9CB2611A4 for ; Mon, 20 Jan 2020 13:24:59 +0100 (CET) Received: from glumotte.dev.6wind.com (unknown [10.16.0.195]) by proxy.6wind.com (Postfix) with ESMTP id 6763236F90F; Mon, 20 Jan 2020 13:24:59 +0100 (CET) Date: Mon, 20 Jan 2020 13:24:59 +0100 From: Olivier Matz To: Jerin Jacob Cc: Jerin Jacob , dpdk-dev , Thomas Monjalon , Andrew Rybchenko , "Richardson, Bruce" , "Ananyev, Konstantin" , Hemant Agrawal , Shahaf Shuler , Honnappa Nagarahalli , Gavin Hu , Jan Viktorin , David Christensen , Anatoly Burakov Message-ID: <20200120122459.GH14387@glumotte.dev.6wind.com> References: <20200113064941.2749356-1-jerinj@marvell.com> <20200114210603.1836160-1-jerinj@marvell.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) Subject: Re: [dpdk-dev] [PATCH v4] mempool: remove memory wastage on non x86 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On Thu, Jan 16, 2020 at 06:40:23PM +0530, Jerin Jacob wrote: > On Wed, Jan 15, 2020 at 2:35 AM wrote: > > > > From: Jerin Jacob > > > > The existing optimize_object_size() function address the memory object > > alignment constraint on x86 for better performance. > > > > Different (micro) architecture may have different memory alignment > > constraint for better performance and it not the same as the existing > > optimize_object_size(). > > > > Some use, XOR(kind of CRC) scheme to enable DRAM channel distribution > > based on the address and some may have a different formula. > > > > Introducing arch_mem_object_align() function to abstract > > the difference between different (micro) architectures to avoid > > wasting memory for mempool object alignment for the architecture > > that it is not required to do so. > > > > Details on the amount of memory saving: > > > > Currently, arm64 based architectures use the default (nchan=4, > > nrank=1). The worst case is for an object whose size (including mempool > > header) is 2 cache lines, where it is optimized to 3 cache lines (+50%). > > > > Examples for cache lines size = 64: > > orig optimized > > 64 -> 64 +0% > > 128 -> 192 +50% > > 192 -> 192 +0% > > 256 -> 320 +25% > > 320 -> 320 +0% > > 384 -> 448 +16% > > ... > > 2304 -> 2368 +2.7% (~mbuf size) > > > > Additional details: > > https://www.mail-archive.com/dev@dpdk.org/msg149157.html > > > > Signed-off-by: Jerin Jacob > > Reviewed-by: Gavin Hu > > Ping for merge. Acked-by: Olivier Matz