From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 7564AA052F; Fri, 24 Jan 2020 05:06:35 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 3B5FF1B9B5; Fri, 24 Jan 2020 05:06:11 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id B4BA64C81 for ; Fri, 24 Jan 2020 05:06:06 +0100 (CET) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 00O3uVe2013533; Thu, 23 Jan 2020 20:06:06 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=XUh71yLqXgdNnspOJ6kT//OmugrLzDHsAX2NDT2zhq8=; b=rXsgXjPNO4VJ3qYqyX2nSMGHIPYsteL+bI6xU6QqOK/fVz/ClaNMseAGmbi+mUTpSiyR CPprKJKeAJWVVIHQAD3tdF6q2/4ijRtSijQ2+nCS9qmcuMqtrlsK8kL+9vjbSk+VLMK0 YSiZQKRyCpY4JGOf7AbT3SA+VAIJ+FkMmBVFO5m39s6BdhIZbiM11hQet87gY5+HTiT1 ZdqVC1GketwxCwW7JoRvQMjQbtNMifZl+15cxke0PhuFSoiLRNRe/4AJQA3y+Pph5kzC K8GUF2ltVSTxaTtcu5tkCIdEL7oVU3LnOg02+lF6ecsZ11kOrl+tfuabDlsLa0jPbX9Y rQ== Received: from sc-exch04.marvell.com ([199.233.58.184]) by mx0a-0016f401.pphosted.com with ESMTP id 2xq4x4mm24-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Thu, 23 Jan 2020 20:06:05 -0800 Received: from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 23 Jan 2020 20:06:04 -0800 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 23 Jan 2020 20:06:04 -0800 Received: from BG-LT7430.marvell.com (bg-lt7430.marvell.com [10.28.10.90]) by maili.marvell.com (Postfix) with ESMTP id ADE4D3F7044; Thu, 23 Jan 2020 20:06:01 -0800 (PST) From: To: , , Marko Kovacevic , Ori Kam , Bruce Richardson , Radu Nicolau , "Akhil Goyal" , Tomasz Kantecki , Sunil Kumar Kori , Pavan Nikhilesh CC: Date: Fri, 24 Jan 2020 09:35:36 +0530 Message-ID: <20200124040542.2360-6-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200124040542.2360-1-pbhagavatula@marvell.com> References: <20200122182817.1667-1-pbhagavatula@marvell.com> <20200124040542.2360-1-pbhagavatula@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572 definitions=2020-01-23_13:2020-01-23, 2020-01-23 signatures=0 Subject: [dpdk-dev] [PATCH v5 05/11] examples/l3fwd: add event port and queue setup X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Sunil Kumar Kori Add event device queue and port setup based on event eth Tx adapter capabilities. Signed-off-by: Sunil Kumar Kori --- examples/l3fwd/l3fwd_event.c | 28 +++++- examples/l3fwd/l3fwd_event.h | 1 + examples/l3fwd/l3fwd_event_generic.c | 103 +++++++++++++++++++++ examples/l3fwd/l3fwd_event_internal_port.c | 98 ++++++++++++++++++++ 4 files changed, 229 insertions(+), 1 deletion(-) diff --git a/examples/l3fwd/l3fwd_event.c b/examples/l3fwd/l3fwd_event.c index f9491ecc6..b58f9b79a 100644 --- a/examples/l3fwd/l3fwd_event.c +++ b/examples/l3fwd/l3fwd_event.c @@ -188,10 +188,30 @@ l3fwd_event_capability_setup(void) l3fwd_event_set_internal_port_ops(&evt_rsrc->ops); } +int +l3fwd_get_free_event_port(struct l3fwd_event_resources *evt_rsrc) +{ + static int index; + int port_id; + + rte_spinlock_lock(&evt_rsrc->evp.lock); + if (index >= evt_rsrc->evp.nb_ports) { + printf("No free event port is available\n"); + return -1; + } + + port_id = evt_rsrc->evp.event_p_id[index]; + index++; + rte_spinlock_unlock(&evt_rsrc->evp.lock); + + return port_id; +} + void l3fwd_event_resource_setup(struct rte_eth_conf *port_conf) { struct l3fwd_event_resources *evt_rsrc = l3fwd_get_eventdev_rsrc(); + uint32_t event_queue_cfg; if (!evt_rsrc->enabled) return; @@ -206,5 +226,11 @@ l3fwd_event_resource_setup(struct rte_eth_conf *port_conf) l3fwd_eth_dev_port_setup(port_conf); /* Event device configuration */ - evt_rsrc->ops.event_device_setup(); + event_queue_cfg = evt_rsrc->ops.event_device_setup(); + + /* Event queue configuration */ + evt_rsrc->ops.event_queue_setup(event_queue_cfg); + + /* Event port configuration */ + evt_rsrc->ops.event_port_setup(); } diff --git a/examples/l3fwd/l3fwd_event.h b/examples/l3fwd/l3fwd_event.h index 53feea069..4bceca920 100644 --- a/examples/l3fwd/l3fwd_event.h +++ b/examples/l3fwd/l3fwd_event.h @@ -73,6 +73,7 @@ struct l3fwd_event_resources { struct l3fwd_event_resources *l3fwd_get_eventdev_rsrc(void); void l3fwd_event_resource_setup(struct rte_eth_conf *port_conf); +int l3fwd_get_free_event_port(struct l3fwd_event_resources *eventdev_rsrc); void l3fwd_event_set_generic_ops(struct l3fwd_event_setup_ops *ops); void l3fwd_event_set_internal_port_ops(struct l3fwd_event_setup_ops *ops); diff --git a/examples/l3fwd/l3fwd_event_generic.c b/examples/l3fwd/l3fwd_event_generic.c index c831cfd66..2532839bf 100644 --- a/examples/l3fwd/l3fwd_event_generic.c +++ b/examples/l3fwd/l3fwd_event_generic.c @@ -81,8 +81,111 @@ l3fwd_event_device_setup_generic(void) return event_queue_cfg; } +static void +l3fwd_event_port_setup_generic(void) +{ + struct l3fwd_event_resources *evt_rsrc = l3fwd_get_eventdev_rsrc(); + uint8_t event_d_id = evt_rsrc->event_d_id; + struct rte_event_port_conf event_p_conf = { + .dequeue_depth = 32, + .enqueue_depth = 32, + .new_event_threshold = 4096 + }; + struct rte_event_port_conf def_p_conf; + uint8_t event_p_id; + int32_t ret; + + evt_rsrc->evp.event_p_id = (uint8_t *)malloc(sizeof(uint8_t) * + evt_rsrc->evp.nb_ports); + if (!evt_rsrc->evp.event_p_id) + rte_panic("No space is available\n"); + + memset(&def_p_conf, 0, sizeof(struct rte_event_port_conf)); + rte_event_port_default_conf_get(event_d_id, 0, &def_p_conf); + + if (def_p_conf.new_event_threshold < event_p_conf.new_event_threshold) + event_p_conf.new_event_threshold = + def_p_conf.new_event_threshold; + + if (def_p_conf.dequeue_depth < event_p_conf.dequeue_depth) + event_p_conf.dequeue_depth = def_p_conf.dequeue_depth; + + if (def_p_conf.enqueue_depth < event_p_conf.enqueue_depth) + event_p_conf.enqueue_depth = def_p_conf.enqueue_depth; + + event_p_conf.disable_implicit_release = + evt_rsrc->disable_implicit_release; + evt_rsrc->deq_depth = def_p_conf.dequeue_depth; + + for (event_p_id = 0; event_p_id < evt_rsrc->evp.nb_ports; + event_p_id++) { + ret = rte_event_port_setup(event_d_id, event_p_id, + &event_p_conf); + if (ret < 0) + rte_panic("Error in configuring event port %d\n", + event_p_id); + + ret = rte_event_port_link(event_d_id, event_p_id, + evt_rsrc->evq.event_q_id, + NULL, + evt_rsrc->evq.nb_queues - 1); + if (ret != (evt_rsrc->evq.nb_queues - 1)) + rte_panic("Error in linking event port %d to queues\n", + event_p_id); + evt_rsrc->evp.event_p_id[event_p_id] = event_p_id; + } + /* init spinlock */ + rte_spinlock_init(&evt_rsrc->evp.lock); + + evt_rsrc->def_p_conf = event_p_conf; +} + +static void +l3fwd_event_queue_setup_generic(uint32_t event_queue_cfg) +{ + struct l3fwd_event_resources *evt_rsrc = l3fwd_get_eventdev_rsrc(); + uint8_t event_d_id = evt_rsrc->event_d_id; + struct rte_event_queue_conf event_q_conf = { + .nb_atomic_flows = 1024, + .nb_atomic_order_sequences = 1024, + .event_queue_cfg = event_queue_cfg, + .priority = RTE_EVENT_DEV_PRIORITY_NORMAL + }; + struct rte_event_queue_conf def_q_conf; + uint8_t event_q_id; + int32_t ret; + + event_q_conf.schedule_type = evt_rsrc->sched_type; + evt_rsrc->evq.event_q_id = (uint8_t *)malloc(sizeof(uint8_t) * + evt_rsrc->evq.nb_queues); + if (!evt_rsrc->evq.event_q_id) + rte_panic("Memory allocation failure\n"); + + rte_event_queue_default_conf_get(event_d_id, 0, &def_q_conf); + if (def_q_conf.nb_atomic_flows < event_q_conf.nb_atomic_flows) + event_q_conf.nb_atomic_flows = def_q_conf.nb_atomic_flows; + + for (event_q_id = 0; event_q_id < (evt_rsrc->evq.nb_queues - 1); + event_q_id++) { + ret = rte_event_queue_setup(event_d_id, event_q_id, + &event_q_conf); + if (ret < 0) + rte_panic("Error in configuring event queue\n"); + evt_rsrc->evq.event_q_id[event_q_id] = event_q_id; + } + + event_q_conf.event_queue_cfg |= RTE_EVENT_QUEUE_CFG_SINGLE_LINK; + event_q_conf.priority = RTE_EVENT_DEV_PRIORITY_HIGHEST, + ret = rte_event_queue_setup(event_d_id, event_q_id, &event_q_conf); + if (ret < 0) + rte_panic("Error in configuring event queue for Tx adapter\n"); + evt_rsrc->evq.event_q_id[event_q_id] = event_q_id; +} + void l3fwd_event_set_generic_ops(struct l3fwd_event_setup_ops *ops) { ops->event_device_setup = l3fwd_event_device_setup_generic; + ops->event_queue_setup = l3fwd_event_queue_setup_generic; + ops->event_port_setup = l3fwd_event_port_setup_generic; } diff --git a/examples/l3fwd/l3fwd_event_internal_port.c b/examples/l3fwd/l3fwd_event_internal_port.c index f3e1ab3a2..59b7d35b7 100644 --- a/examples/l3fwd/l3fwd_event_internal_port.c +++ b/examples/l3fwd/l3fwd_event_internal_port.c @@ -80,9 +80,107 @@ l3fwd_event_device_setup_internal_port(void) return event_queue_cfg; } +static void +l3fwd_event_port_setup_internal_port(void) +{ + struct l3fwd_event_resources *evt_rsrc = l3fwd_get_eventdev_rsrc(); + uint8_t event_d_id = evt_rsrc->event_d_id; + struct rte_event_port_conf event_p_conf = { + .dequeue_depth = 32, + .enqueue_depth = 32, + .new_event_threshold = 4096 + }; + struct rte_event_port_conf def_p_conf; + uint8_t event_p_id; + int32_t ret; + + evt_rsrc->evp.event_p_id = (uint8_t *)malloc(sizeof(uint8_t) * + evt_rsrc->evp.nb_ports); + if (!evt_rsrc->evp.event_p_id) + rte_panic("Failed to allocate memory for Event Ports\n"); + + rte_event_port_default_conf_get(event_d_id, 0, &def_p_conf); + if (def_p_conf.new_event_threshold < event_p_conf.new_event_threshold) + event_p_conf.new_event_threshold = + def_p_conf.new_event_threshold; + + if (def_p_conf.dequeue_depth < event_p_conf.dequeue_depth) + event_p_conf.dequeue_depth = def_p_conf.dequeue_depth; + + if (def_p_conf.enqueue_depth < event_p_conf.enqueue_depth) + event_p_conf.enqueue_depth = def_p_conf.enqueue_depth; + + event_p_conf.disable_implicit_release = + evt_rsrc->disable_implicit_release; + + for (event_p_id = 0; event_p_id < evt_rsrc->evp.nb_ports; + event_p_id++) { + ret = rte_event_port_setup(event_d_id, event_p_id, + &event_p_conf); + if (ret < 0) + rte_panic("Error in configuring event port %d\n", + event_p_id); + + ret = rte_event_port_link(event_d_id, event_p_id, NULL, + NULL, 0); + if (ret < 0) + rte_panic("Error in linking event port %d to queue\n", + event_p_id); + evt_rsrc->evp.event_p_id[event_p_id] = event_p_id; + + /* init spinlock */ + rte_spinlock_init(&evt_rsrc->evp.lock); + } + + evt_rsrc->def_p_conf = event_p_conf; +} + +static void +l3fwd_event_queue_setup_internal_port(uint32_t event_queue_cfg) +{ + struct l3fwd_event_resources *evt_rsrc = l3fwd_get_eventdev_rsrc(); + uint8_t event_d_id = evt_rsrc->event_d_id; + struct rte_event_queue_conf event_q_conf = { + .nb_atomic_flows = 1024, + .nb_atomic_order_sequences = 1024, + .event_queue_cfg = event_queue_cfg, + .priority = RTE_EVENT_DEV_PRIORITY_NORMAL + }; + struct rte_event_queue_conf def_q_conf; + uint8_t event_q_id = 0; + int32_t ret; + + rte_event_queue_default_conf_get(event_d_id, event_q_id, &def_q_conf); + + if (def_q_conf.nb_atomic_flows < event_q_conf.nb_atomic_flows) + event_q_conf.nb_atomic_flows = def_q_conf.nb_atomic_flows; + + if (def_q_conf.nb_atomic_order_sequences < + event_q_conf.nb_atomic_order_sequences) + event_q_conf.nb_atomic_order_sequences = + def_q_conf.nb_atomic_order_sequences; + + event_q_conf.event_queue_cfg = event_queue_cfg; + event_q_conf.schedule_type = evt_rsrc->sched_type; + evt_rsrc->evq.event_q_id = (uint8_t *)malloc(sizeof(uint8_t) * + evt_rsrc->evq.nb_queues); + if (!evt_rsrc->evq.event_q_id) + rte_panic("Memory allocation failure\n"); + + for (event_q_id = 0; event_q_id < evt_rsrc->evq.nb_queues; + event_q_id++) { + ret = rte_event_queue_setup(event_d_id, event_q_id, + &event_q_conf); + if (ret < 0) + rte_panic("Error in configuring event queue\n"); + evt_rsrc->evq.event_q_id[event_q_id] = event_q_id; + } +} void l3fwd_event_set_internal_port_ops(struct l3fwd_event_setup_ops *ops) { ops->event_device_setup = l3fwd_event_device_setup_internal_port; + ops->event_queue_setup = l3fwd_event_queue_setup_internal_port; + ops->event_port_setup = l3fwd_event_port_setup_internal_port; } -- 2.17.1