From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 8FF7EA04B3; Mon, 3 Feb 2020 06:08:22 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 740441BFEF; Mon, 3 Feb 2020 06:08:22 +0100 (CET) Received: from NAM02-SN1-obe.outbound.protection.outlook.com (mail-eopbgr770083.outbound.protection.outlook.com [40.107.77.83]) by dpdk.org (Postfix) with ESMTP id BDE581BFE0; Mon, 3 Feb 2020 06:08:20 +0100 (CET) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Uu25tIeMmuZoAOlHgt6lrv/rfgMmN8hJb8wGXrHa1Qyp6r5U2GDL250bl+RZRTLQrJAIkZDmSTOvnMG+Hozioc+1g5VilA9JaKo2Dhc3QKtlsmMVcx/hwVvxNilz2Q+CXULUMvlR69H8VFnrOloLgFYIm5VN1ZaYafb845HnJy3WiN7StIlmi7GenT7YJolmH2xfAgfNYdsIjAOc1V4m/wDNt+qf6y3xlA3afwL3Taks4v2SCzJ5XAWyDOn5i81uas7X+5lr38d6mb6bB81lr8zL057gCjc98mRKfEPplEjjCd8MN8f6InVocBAyqMGbV7nXMW1yDt/5Ws9g4HjLnw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=9KFCIvYV1GsGBQDPMJ1OVzV0daBU8t61s5j6qIZSu+Q=; b=Qoj/bkbmfzeKSFCUXhT4PLWFPL5NrHSCxRZs98ryTYjcqD2DT8PBJTZWQdKXvfRmTVp2LHCLDX611JcWLA1grtYyosE4CacyNISoVs1/viYB/Aek4ds2Hh7AM6q6g3PksMn8nOaVf7H3V4DO9E4JxDbjn+pCp1wvAkwxeB6rwrQJcMcHo0LCQNANLQNrMrhZxEpwSc40iJUjaMVUR3RCrqAK46oQR1oFphvnKdbeGalMYA0FM78eyv4BUPxtTto1HD22oaBVxpt8HSPSku2cFglLNkQWYC8zxj8fXU2HzcvHTEOvlJDrwHhHsiDDm8FkIst2e0iZpBC3z+DorDwyYw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=amd.com; dmarc=pass action=none header.from=amd.com; dkim=pass header.d=amd.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector2-amdcloud-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=9KFCIvYV1GsGBQDPMJ1OVzV0daBU8t61s5j6qIZSu+Q=; b=gBCOlJ5Nm7feXn5CCXli4DA+ir//9K49OOUIBP6OYQna+kOko45aLoJNsCX5EIo9dN1DmyMxPtL/LZDMC7kZMmph8hUKnxSBM4CwyzNGX80smLRRwG4cqJEKsO04Fmk6Q2EDl72vzLDimoTfxju9ya/XuFmlt/MPk0ZQIyOywFY= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Amaranath.Somalapuram@amd.com; Received: from DM5PR1201MB2474.namprd12.prod.outlook.com (10.172.87.136) by DM5PR1201MB0123.namprd12.prod.outlook.com (10.174.104.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2686.27; Mon, 3 Feb 2020 05:08:19 +0000 Received: from DM5PR1201MB2474.namprd12.prod.outlook.com ([fe80::3d24:2943:582c:c7b5]) by DM5PR1201MB2474.namprd12.prod.outlook.com ([fe80::3d24:2943:582c:c7b5%6]) with mapi id 15.20.2686.031; Mon, 3 Feb 2020 05:08:19 +0000 From: asomalap@amd.com To: dev@dpdk.org Cc: stable@dpdk.org Date: Mon, 3 Feb 2020 10:34:59 +0530 Message-Id: <20200203050459.62241-1-asomalap@amd.com> X-Mailer: git-send-email 2.17.1 Content-Type: text/plain X-ClientProxiedBy: MA1PR0101CA0029.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:22::15) To DM5PR1201MB2474.namprd12.prod.outlook.com (2603:10b6:3:e3::8) MIME-Version: 1.0 Received: from amd.amd.com (165.204.157.251) by MA1PR0101CA0029.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:22::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2686.27 via Frontend Transport; Mon, 3 Feb 2020 05:08:18 +0000 X-Mailer: git-send-email 2.17.1 X-Originating-IP: [165.204.157.251] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: f4d3ea0e-50e8-440c-e7e7-08d7a8671591 X-MS-TrafficTypeDiagnostic: DM5PR1201MB0123: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:1122; X-Forefront-PRVS: 0302D4F392 X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(4636009)(376002)(39860400002)(346002)(136003)(396003)(366004)(189003)(199004)(6916009)(2616005)(36756003)(7696005)(52116002)(956004)(5660300002)(450100002)(316002)(4326008)(66556008)(16526019)(66476007)(26005)(478600001)(8936002)(186003)(81156014)(81166006)(66946007)(8676002)(1076003)(9686003)(6486002)(2906002)(6666004); DIR:OUT; SFP:1101; SCL:1; SRVR:DM5PR1201MB0123; H:DM5PR1201MB2474.namprd12.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: AOma7JYYcvWE5PVnWzdhw3uNJYj/nIK1AeWNVbgLHGvhGwoCXk7rePN3lVrW1yi7AnS5XMeuFhO10Edx30PJL0r3Wen46IBOEf/41VE3T39jTjoytyqMDB/d/Q14pxKpi2XFScJufQASaz/8MmbeDRXJeSprMfdcyJ0p7hpwUfCNoAe64pRaVep1hGVXJbODhRpzwl13INKmUBmeMwMAxMLfHVZC7kIycT/S9DZrp3r1sudqvT5D9rrYZE2Jl2EPYFA9bHcpUe2GJRLz4rfD0NmUkHtKASKf+V9M2qvLvUZzfSHbOjaIxUSExKq99utOSCJ73xmf/GxkV+rWbCr+SvD4O8a2Pt3GzAwBU0PwHzs6Y+s8w6K6JLyg+PsfB6xfPtO3wwIuDOYTEyR0zsyGYjmFFEQ9I7jjaaSWp3uiSX7xupz0asznenupbEgAzvLX X-MS-Exchange-AntiSpam-MessageData: g7GzrtR2+buXrYUlmCxE5fO52LOczG/Op3QqfnPRADx5s1eGgnWNP2r4VRvpSd4Bw74UTjUCqcuDZDhqNH0lXLIgcoCmQSRushououy7YS2lHktYGbPvTS4WWGZzutN2tUanJBxPx/T3+taH+DR0CA== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: f4d3ea0e-50e8-440c-e7e7-08d7a8671591 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Feb 2020 05:08:19.4775 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Sg0O2yEjLB6Otomn5i7ST3/9GYCNUUZIRHJNtSY/vbdaHe2zFot1hnE15eZkFm693NmlMIhEFCjeZ72PG4UELQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR1201MB0123 Subject: [dpdk-dev] [PATCH v3 2/2] net/axgbe: support priority flow control API X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Amaranath Somalapuram Adding API for priority_flow_ctrl_set. Priority flow control to set water high and low, pause_time and priority. Cc: stable@dpdk.org Signed-off-by: Amaranath Somalapuram --- drivers/net/axgbe/axgbe_common.h | 17 ++++++ drivers/net/axgbe/axgbe_dev.c | 1 + drivers/net/axgbe/axgbe_ethdev.c | 96 ++++++++++++++++++++++++++++++++ drivers/net/axgbe/axgbe_ethdev.h | 1 + 4 files changed, 115 insertions(+) diff --git a/drivers/net/axgbe/axgbe_common.h b/drivers/net/axgbe/axgbe_common.h index fdb037dd5..bc7bc6af5 100644 --- a/drivers/net/axgbe/axgbe_common.h +++ b/drivers/net/axgbe/axgbe_common.h @@ -833,6 +833,23 @@ #define MTL_TC_QWR_QW_INDEX 0 #define MTL_TC_QWR_QW_WIDTH 21 +#define MTL_TCPM0R_PSTC0_INDEX 0 +#define MTL_TCPM0R_PSTC0_WIDTH 8 +#define MTL_TCPM0R_PSTC1_INDEX 8 +#define MTL_TCPM0R_PSTC1_WIDTH 8 +#define MTL_TCPM0R_PSTC2_INDEX 16 +#define MTL_TCPM0R_PSTC2_WIDTH 8 +#define MTL_TCPM0R_PSTC3_INDEX 24 +#define MTL_TCPM0R_PSTC3_WIDTH 8 +#define MTL_TCPM1R_PSTC4_INDEX 0 +#define MTL_TCPM1R_PSTC4_WIDTH 8 +#define MTL_TCPM1R_PSTC5_INDEX 8 +#define MTL_TCPM1R_PSTC5_WIDTH 8 +#define MTL_TCPM1R_PSTC6_INDEX 16 +#define MTL_TCPM1R_PSTC6_WIDTH 8 +#define MTL_TCPM1R_PSTC7_INDEX 24 +#define MTL_TCPM1R_PSTC7_WIDTH 8 + /* MTL traffic class register value */ #define MTL_TSA_SP 0x00 #define MTL_TSA_ETS 0x02 diff --git a/drivers/net/axgbe/axgbe_dev.c b/drivers/net/axgbe/axgbe_dev.c index 83089f20d..9a68bea63 100644 --- a/drivers/net/axgbe/axgbe_dev.c +++ b/drivers/net/axgbe/axgbe_dev.c @@ -958,6 +958,7 @@ static void axgbe_config_queue_mapping(struct axgbe_port *pdata) if (i < qptc_extra) AXGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR, Q2TCMAP, i); + pdata->pfc_map[queue++] = i; } if (pdata->rss_enable) { diff --git a/drivers/net/axgbe/axgbe_ethdev.c b/drivers/net/axgbe/axgbe_ethdev.c index b88ad55ac..686a9a20d 100644 --- a/drivers/net/axgbe/axgbe_ethdev.c +++ b/drivers/net/axgbe/axgbe_ethdev.c @@ -48,6 +48,8 @@ static int axgbe_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf); static int axgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf); +static int axgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, + struct rte_eth_pfc_conf *pfc_conf); struct axgbe_xstats { char name[RTE_ETH_XSTATS_NAME_SIZE]; @@ -176,6 +178,7 @@ static const struct eth_dev_ops axgbe_eth_dev_ops = { .tx_queue_release = axgbe_dev_tx_queue_release, .flow_ctrl_get = axgbe_flow_ctrl_get, .flow_ctrl_set = axgbe_flow_ctrl_set, + .priority_flow_ctrl_set = axgbe_priority_flow_ctrl_set, }; static int axgbe_phy_reset(struct axgbe_port *pdata) @@ -899,6 +902,99 @@ axgbe_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf) return 0; } +static int +axgbe_priority_flow_ctrl_set(struct rte_eth_dev *dev, + struct rte_eth_pfc_conf *pfc_conf) +{ + struct axgbe_port *pdata = dev->data->dev_private; + struct xgbe_fc_info fc = pdata->fc; + uint8_t tc_num; + + tc_num = pdata->pfc_map[pfc_conf->priority]; + + if (pfc_conf->priority >= pdata->hw_feat.tc_cnt) { + PMD_INIT_LOG(ERR, "Max supported traffic class: %d\n", + pdata->hw_feat.tc_cnt); + return -EINVAL; + } + + pdata->pause_autoneg = pfc_conf->fc.autoneg; + pdata->phy.pause_autoneg = pdata->pause_autoneg; + fc.send_xon = pfc_conf->fc.send_xon; + AXGMAC_MTL_IOWRITE_BITS(pdata, tc_num, MTL_Q_RQFCR, RFA, + AXGMAC_FLOW_CONTROL_VALUE(1024 * pfc_conf->fc.high_water)); + AXGMAC_MTL_IOWRITE_BITS(pdata, tc_num, MTL_Q_RQFCR, RFD, + AXGMAC_FLOW_CONTROL_VALUE(1024 * pfc_conf->fc.low_water)); + + switch (tc_num) { + case 0: + AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R, + PSTC0, pfc_conf->fc.pause_time); + break; + case 1: + AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R, + PSTC1, pfc_conf->fc.pause_time); + break; + case 2: + AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R, + PSTC2, pfc_conf->fc.pause_time); + break; + case 3: + AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM0R, + PSTC3, pfc_conf->fc.pause_time); + break; + case 4: + AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R, + PSTC4, pfc_conf->fc.pause_time); + break; + case 5: + AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R, + PSTC5, pfc_conf->fc.pause_time); + break; + case 7: + AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R, + PSTC6, pfc_conf->fc.pause_time); + break; + case 6: + AXGMAC_IOWRITE_BITS(pdata, MTL_TCPM1R, + PSTC7, pfc_conf->fc.pause_time); + break; + } + + fc.mode = pfc_conf->fc.mode; + + if (fc.mode == RTE_FC_FULL) { + pdata->tx_pause = 1; + pdata->rx_pause = 1; + AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 1); + } else if (fc.mode == RTE_FC_RX_PAUSE) { + pdata->tx_pause = 0; + pdata->rx_pause = 1; + AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 1); + } else if (fc.mode == RTE_FC_TX_PAUSE) { + pdata->tx_pause = 1; + pdata->rx_pause = 0; + AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 0); + } else { + pdata->tx_pause = 0; + pdata->rx_pause = 0; + AXGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE, 0); + } + + if (pdata->tx_pause != (unsigned int)pdata->phy.tx_pause) + pdata->hw_if.config_tx_flow_control(pdata); + + if (pdata->rx_pause != (unsigned int)pdata->phy.rx_pause) + pdata->hw_if.config_rx_flow_control(pdata); + pdata->hw_if.config_flow_control(pdata); + pdata->phy.tx_pause = pdata->tx_pause; + pdata->phy.rx_pause = pdata->rx_pause; + + return 0; +} + + + static void axgbe_get_all_hw_features(struct axgbe_port *pdata) { unsigned int mac_hfr0, mac_hfr1, mac_hfr2; diff --git a/drivers/net/axgbe/axgbe_ethdev.h b/drivers/net/axgbe/axgbe_ethdev.h index 746fb2f15..c884f5642 100644 --- a/drivers/net/axgbe/axgbe_ethdev.h +++ b/drivers/net/axgbe/axgbe_ethdev.h @@ -585,6 +585,7 @@ struct axgbe_port { unsigned int rx_rfa[AXGBE_MAX_QUEUES]; unsigned int rx_rfd[AXGBE_MAX_QUEUES]; unsigned int fifo; + unsigned int pfc_map[AXGBE_MAX_QUEUES]; /* Receive Side Scaling settings */ u8 rss_key[AXGBE_RSS_HASH_KEY_SIZE]; -- 2.17.1