From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id A2203A0542; Thu, 13 Feb 2020 13:44:16 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id D9E851BFEF; Thu, 13 Feb 2020 13:44:10 +0100 (CET) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by dpdk.org (Postfix) with ESMTP id 771D31BFEF; Thu, 13 Feb 2020 13:44:09 +0100 (CET) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 00BCF1045; Thu, 13 Feb 2020 04:44:09 -0800 (PST) Received: from net-arm-thunderx2-04.shanghai.arm.com (net-arm-thunderx2-04.shanghai.arm.com [10.169.40.184]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 2A3C33F6CF; Thu, 13 Feb 2020 04:44:01 -0800 (PST) From: Gavin Hu To: dev@dpdk.org Cc: nd@arm.com, david.marchand@redhat.com, thomas@monjalon.net, rasland@mellanox.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, matan@mellanox.com, shahafs@mellanox.com, viacheslavo@mellanox.com, jerinj@marvell.com, Honnappa.Nagarahalli@arm.com, ruifeng.wang@arm.com, phil.yang@arm.com, joyce.kong@arm.com, steve.capper@arm.com, stable@dpdk.org Date: Thu, 13 Feb 2020 20:38:51 +0800 Message-Id: <20200213123854.203566-4-gavin.hu@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200213123854.203566-1-gavin.hu@arm.com> References: <20200213123854.203566-1-gavin.hu@arm.com> Subject: [dpdk-dev] [PATCH RFC v1 3/6] net/mlx5: add missing barrier X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" To keep order of the modification of RX queue descriptor(rxq->cq_db) and the CQ doorbell register, a rte_cio_wmb barrier is required. The situation was rescued by the stronger than required barrier in the mlx5_uar_write64, it becomes a must when the barrier is relaxed. Fixes: 6bf10ab69be0 ("net/mlx5: support 32-bit systems") Cc: stable@dpdk.org Suggested-by: Phil Yang Signed-off-by: Gavin Hu Reviewed-by: Phil Yang --- drivers/net/mlx5/mlx5_rxq.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c index dc0fd8211..2d1b153a3 100644 --- a/drivers/net/mlx5/mlx5_rxq.c +++ b/drivers/net/mlx5/mlx5_rxq.c @@ -856,7 +856,8 @@ mlx5_arm_cq(struct mlx5_rxq_data *rxq, int sq_n_rxq) doorbell = (uint64_t)doorbell_hi << 32; doorbell |= rxq->cqn; rxq->cq_db[MLX5_CQ_ARM_DB] = rte_cpu_to_be_32(doorbell_hi); - mlx5_uar_write64(rte_cpu_to_be_64(doorbell), + rte_cio_wmb(); + mlx5_uar_write64_relaxed(rte_cpu_to_be_64(doorbell), cq_db_reg, rxq->uar_lock_cq); } -- 2.17.1