From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id A5BCFA056B; Thu, 12 Mar 2020 12:19:28 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id DDBA91C01F; Thu, 12 Mar 2020 12:19:24 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 942291C01B for ; Thu, 12 Mar 2020 12:19:22 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 02CBFhrB017716 for ; Thu, 12 Mar 2020 04:19:22 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0818; bh=6XXEZ0esLS/K476xp7K6jtQ8tg3ja9ps5nZw95L4+LE=; b=N37zXS6COg/9dI7S2USQRjkDR2F/A2UQcrNuccco6ai6XdbEHDGM9KleajjX/fQuLJP5 O9oLpOii/Qum85x6yh5zpBgoKr+aOzMBOPMnnDlRf7TcLf4Jjzpktb9Ot8F9znMGVGUC XuJFVvCx5niYHb5ivNwV1nzjl6tkHvhgXk9a8Q2rR7Nbrq3e8mEkj+LNnQNSQXeGH21S AUeODbDxZqIJyqFscoVTYBRSTy10bNB/A50u6ZBPE2XsLnl6acjbi96zoPWN+NGlrsB/ KqTrMMbXR+rAnqL3sCWqiOZyi+NSC720l6pG9UZ9gFQj8cFNd/Bgsp/PBtZNinMdOPHP +Q== Received: from sc-exch04.marvell.com ([199.233.58.184]) by mx0b-0016f401.pphosted.com with ESMTP id 2yqfggs6dq-2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT) for ; Thu, 12 Mar 2020 04:19:21 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 12 Mar 2020 04:19:18 -0700 Received: from SC-EXCH04.marvell.com (10.93.176.84) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 12 Mar 2020 04:19:17 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 12 Mar 2020 04:19:17 -0700 Received: from hyd1588t430.marvell.com (unknown [10.29.52.204]) by maili.marvell.com (Postfix) with ESMTP id E2BA13F704E; Thu, 12 Mar 2020 04:19:15 -0700 (PDT) From: Nithin Dabilpuram To: Jerin Jacob , Nithin Dabilpuram , Kiran Kumar K CC: Krzysztof Kanas , Date: Thu, 12 Mar 2020 16:48:57 +0530 Message-ID: <20200312111907.31555-2-ndabilpuram@marvell.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20200312111907.31555-1-ndabilpuram@marvell.com> References: <20200312111907.31555-1-ndabilpuram@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.572 definitions=2020-03-12_03:2020-03-11, 2020-03-12 signatures=0 Subject: [dpdk-dev] [PATCH 01/11] net/octeontx2: setup link config based on BP level X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Configure NIX_AF_TL3_TL2X_LINKX_CFG using schq at level based on NIX_AF_PSE_CHANNEL_LEVEL[BP_LEVEL]. Signed-off-by: Nithin Dabilpuram --- drivers/net/octeontx2/otx2_ethdev.h | 1 + drivers/net/octeontx2/otx2_tm.c | 16 +++++++++++++++- 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/net/octeontx2/otx2_ethdev.h b/drivers/net/octeontx2/otx2_ethdev.h index e5684f9..b7d5386 100644 --- a/drivers/net/octeontx2/otx2_ethdev.h +++ b/drivers/net/octeontx2/otx2_ethdev.h @@ -304,6 +304,7 @@ struct otx2_eth_dev { /* Contiguous queues */ uint16_t txschq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC]; uint16_t otx2_tm_root_lvl; + uint16_t link_cfg_lvl; uint16_t tm_flags; uint16_t tm_leaf_cnt; struct otx2_nix_tm_node_list node_list; diff --git a/drivers/net/octeontx2/otx2_tm.c b/drivers/net/octeontx2/otx2_tm.c index ba615ce..2364e03 100644 --- a/drivers/net/octeontx2/otx2_tm.c +++ b/drivers/net/octeontx2/otx2_tm.c @@ -437,6 +437,16 @@ populate_tm_registers(struct otx2_eth_dev *dev, *reg++ = NIX_AF_TL3X_SCHEDULE(schq); *regval++ = (strict_schedul_prio << 24) | rr_quantum; req->num_regs++; + + /* Link configuration */ + if (!otx2_dev_is_sdp(dev) && + dev->link_cfg_lvl == NIX_TXSCH_LVL_TL3) { + *reg++ = NIX_AF_TL3_TL2X_LINKX_CFG(schq, + nix_get_link(dev)); + *regval++ = BIT_ULL(12) | nix_get_relchan(dev); + req->num_regs++; + } + if (pir.rate && pir.burst) { *reg++ = NIX_AF_TL3X_PIR(schq); *regval++ = shaper2regval(&pir) | 1; @@ -471,7 +481,10 @@ populate_tm_registers(struct otx2_eth_dev *dev, else *regval++ = (strict_schedul_prio << 24) | rr_quantum; req->num_regs++; - if (!otx2_dev_is_sdp(dev)) { + + /* Link configuration */ + if (!otx2_dev_is_sdp(dev) && + dev->link_cfg_lvl == NIX_TXSCH_LVL_TL2) { *reg++ = NIX_AF_TL3_TL2X_LINKX_CFG(schq, nix_get_link(dev)); *regval++ = BIT_ULL(12) | nix_get_relchan(dev); @@ -1144,6 +1157,7 @@ nix_tm_send_txsch_alloc_msg(struct otx2_eth_dev *dev) return rc; nix_tm_copy_rsp_to_dev(dev, rsp); + dev->link_cfg_lvl = rsp->link_cfg_lvl; nix_tm_assign_hw_id(dev); return 0; -- 2.8.4