From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4EC85A0559; Mon, 16 Mar 2020 08:59:21 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 836FB1C10D; Mon, 16 Mar 2020 08:57:42 +0100 (CET) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by dpdk.org (Postfix) with ESMTP id 3CDE41C0CD for ; Mon, 16 Mar 2020 08:57:39 +0100 (CET) IronPort-SDR: 29wQXimoQRcgxVW6QMrNUpe7GtZzD+6aZ4P5Fp4ihSmdUi1xC77zW1pMGDJpa0Ag5P685r5PII +6FnfhbtP8GA== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Mar 2020 00:57:38 -0700 IronPort-SDR: 0OIXltztx8E++QU7J8qBSB+b1c2zF5FO3ooLm+GuUrj14bMCmwPwLioJ+1peYH+xk0NhQ3yU9f rcGdum7pWsDA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,559,1574150400"; d="scan'208";a="390622547" Received: from dpdk-lrong-srv-04.sh.intel.com ([10.67.119.221]) by orsmga004.jf.intel.com with ESMTP; 16 Mar 2020 00:57:37 -0700 From: Leyi Rong To: qi.z.zhang@intel.com, xiaolong.ye@intel.com Cc: dev@dpdk.org, Leyi Rong Date: Mon, 16 Mar 2020 15:46:01 +0800 Message-Id: <20200316074603.10998-11-leyi.rong@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200316074603.10998-1-leyi.rong@intel.com> References: <20200316074603.10998-1-leyi.rong@intel.com> Subject: [dpdk-dev] [PATCH 10/12] net/iavf: support flow mark in SSE path X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Support Flow Director mark ID parsing from Flex Rx descriptor in SSE path. Signed-off-by: Leyi Rong --- drivers/net/iavf/iavf_rxtx_vec_sse.c | 48 +++++++++++++++++++++++++++- 1 file changed, 47 insertions(+), 1 deletion(-) diff --git a/drivers/net/iavf/iavf_rxtx_vec_sse.c b/drivers/net/iavf/iavf_rxtx_vec_sse.c index 9c1f2a445..eb784938f 100644 --- a/drivers/net/iavf/iavf_rxtx_vec_sse.c +++ b/drivers/net/iavf/iavf_rxtx_vec_sse.c @@ -189,6 +189,25 @@ desc_to_olflags_v(struct iavf_rx_queue *rxq, __m128i descs[4], _mm_store_si128((__m128i *)&rx_pkts[3]->rearm_data, rearm3); } +static inline __m128i +flex_rxd_to_fdir_flags_vec(const __m128i fdir_id0_3) +{ +#define FDID_MIS_MAGIC 0xFFFFFFFF + RTE_BUILD_BUG_ON(PKT_RX_FDIR != (1 << 2)); + RTE_BUILD_BUG_ON(PKT_RX_FDIR_ID != (1 << 13)); + const __m128i pkt_fdir_bit = _mm_set1_epi32(PKT_RX_FDIR | + PKT_RX_FDIR_ID); + /* desc->flow_id field == 0xFFFFFFFF means fdir mismatch */ + const __m128i fdir_mis_mask = _mm_set1_epi32(FDID_MIS_MAGIC); + __m128i fdir_mask = _mm_cmpeq_epi32(fdir_id0_3, + fdir_mis_mask); + /* this XOR op results to bit-reverse the fdir_mask */ + fdir_mask = _mm_xor_si128(fdir_mask, fdir_mis_mask); + const __m128i fdir_flags = _mm_and_si128(fdir_mask, pkt_fdir_bit); + + return fdir_flags; +} + static inline void flex_desc_to_olflags_v(struct iavf_rx_queue *rxq, __m128i descs[4], struct rte_mbuf **rx_pkts) @@ -267,6 +286,32 @@ flex_desc_to_olflags_v(struct iavf_rx_queue *rxq, __m128i descs[4], /* merge the flags */ flags = _mm_or_si128(flags, rss_vlan); + if (rxq->vsi->adapter->fdir_enabled) { + const __m128i fdir_id0_1 = + _mm_unpackhi_epi32(descs[0], descs[1]); + + const __m128i fdir_id2_3 = + _mm_unpackhi_epi32(descs[2], descs[3]); + + const __m128i fdir_id0_3 = + _mm_unpackhi_epi64(fdir_id0_1, fdir_id2_3); + + const __m128i fdir_flags = + flex_rxd_to_fdir_flags_vec(fdir_id0_3); + + /* merge with fdir_flags */ + flags = _mm_or_si128(flags, fdir_flags); + + /* write fdir_id to mbuf if FDIR match */ + uint32_t fdir_id_extr, i; + + for (i = 0; i < IAVF_VPMD_DESCS_PER_LOOP; i++) { + fdir_id_extr = _mm_extract_epi32(fdir_id0_3, i); + if (fdir_id_extr != FDID_MIS_MAGIC) + rx_pkts[i]->hash.fdir.hi = fdir_id_extr; + } + } /* if() on fdir_enabled */ + /** * At this point, we have the 4 sets of flags in the low 16-bits * of each 32-bit value in flags. @@ -604,7 +649,8 @@ _recv_raw_pkts_vec_flex_rxd(struct iavf_rx_queue *rxq, const __m128i zero = _mm_setzero_si128(); /* mask to shuffle from desc. to mbuf */ const __m128i shuf_msk = _mm_set_epi8 - (15, 14, 13, 12, /* octet 12~15, 32 bits rss */ + (0xFF, 0xFF, + 0xFF, 0xFF, /* rss not supported */ 11, 10, /* octet 10~11, 16 bits vlan_macip */ 5, 4, /* octet 4~5, 16 bits data_len */ 0xFF, 0xFF, /* skip high 16 bits pkt_len, zero out */ -- 2.17.1