[dpdk-dev] [PATCH 00/17] Add CPU flags

[dpdk-dev] [PATCH 00/17] Add CPU flags

[Kevin Laatz]

This patch set adds CPU flags which will enable the detection of ISA
features available on more recent x86 based CPUs.

The CPUID leaf information can be found in Section 1.7 of this
document:
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf

Kevin Laatz (17):
  eal/cpuflags: add avx512 doubleword and quadword
  eal/cpuflags: add avx512 integer fused multiply-add
  eal/cpuflags: add avx512 conflict detection
  eal/cpuflags: add avx512 byte and word
  eal/cpuflags: add avx512 vector length
  eal/cpuflags: add avx512 vector bit manipulation
  eal/cpuflags: add avx512 vector bit manipulation 2
  eal/cpuflags: add galois field new instructions
  eal/cpuflags: add vector AES
  eal/cpuflags: add vector carry-less multiply
  eal/cpuflags: add avx512 vector neural network instructions
  eal/cpuflags: add avx512 bit algorithms
  eal/cpuflags: add avx512 vector popcount
  eal/cpuflags: add cache line demote
  eal/cpuflags: add direct store instructions
  eal/cpuflags: add direct store instructions 64B
  eal/cpuflags: add avx512 two register intersection

 lib/librte_eal/common/arch/x86/rte_cpuflags.c  | 18 ++++++++++++++++++
 .../common/include/arch/x86/rte_cpuflags.h     | 18 ++++++++++++++++++
 2 files changed, 36 insertions(+)

-- 
2.17.1

[dpdk-dev] [PATCH 01/17] eal/cpuflags: add avx512 doubleword and quadword

[Kevin Laatz]

Add the CPU flag for AVX-512 doubleword and quadword instructions.

Signed-off-by: Kevin Laatz <kevin.laatz@intel.com>
---
 lib/librte_eal/common/arch/x86/rte_cpuflags.c         | 2 ++
 lib/librte_eal/common/include/arch/x86/rte_cpuflags.h | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/lib/librte_eal/common/arch/x86/rte_cpuflags.c b/lib/librte_eal/common/arch/x86/rte_cpuflags.c
index 6492df556..2e2fbec1c 100644
--- a/lib/librte_eal/common/arch/x86/rte_cpuflags.c
+++ b/lib/librte_eal/common/arch/x86/rte_cpuflags.c
@@ -120,6 +120,8 @@ const struct feature_entry rte_cpu_feature_table[] = {
 	FEAT_DEF(EM64T, 0x80000001, 0, RTE_REG_EDX, 29)
 
 	FEAT_DEF(INVTSC, 0x80000007, 0, RTE_REG_EDX,  8)
+
+	FEAT_DEF(AVX512DQ, 0x00000007, 0, RTE_REG_EBX, 17)
 };
 
 int
diff --git a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
index 25ba47b96..cec45c382 100644
--- a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
+++ b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
@@ -113,6 +113,8 @@ enum rte_cpu_flag_t {
 	/* (EAX 80000007h) EDX features */
 	RTE_CPUFLAG_INVTSC,                 /**< INVTSC */
 
+	RTE_CPUFLAG_AVX512DQ,               /**< AVX512 Doubleword and Quadword */
+
 	/* The last item */
 	RTE_CPUFLAG_NUMFLAGS,               /**< This should always be the last! */
 };
-- 
2.17.1

[dpdk-dev] [PATCH 02/17] eal/cpuflags: add avx512 integer fused multiply-add

[Kevin Laatz]

Add the CPU flag for AVX-512 integer fused multiply-add instructions.

Signed-off-by: Kevin Laatz <kevin.laatz@intel.com>
---
 lib/librte_eal/common/arch/x86/rte_cpuflags.c         | 1 +
 lib/librte_eal/common/include/arch/x86/rte_cpuflags.h | 1 +
 2 files changed, 2 insertions(+)

diff --git a/lib/librte_eal/common/arch/x86/rte_cpuflags.c b/lib/librte_eal/common/arch/x86/rte_cpuflags.c
index 2e2fbec1c..d56bd57f9 100644
--- a/lib/librte_eal/common/arch/x86/rte_cpuflags.c
+++ b/lib/librte_eal/common/arch/x86/rte_cpuflags.c
@@ -122,6 +122,7 @@ const struct feature_entry rte_cpu_feature_table[] = {
 	FEAT_DEF(INVTSC, 0x80000007, 0, RTE_REG_EDX,  8)
 
 	FEAT_DEF(AVX512DQ, 0x00000007, 0, RTE_REG_EBX, 17)
+	FEAT_DEF(AVX512IFMA, 0x00000007, 0, RTE_REG_EBX, 21)
 };
 
 int
diff --git a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
index cec45c382..81f510299 100644
--- a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
+++ b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
@@ -114,6 +114,7 @@ enum rte_cpu_flag_t {
 	RTE_CPUFLAG_INVTSC,                 /**< INVTSC */
 
 	RTE_CPUFLAG_AVX512DQ,               /**< AVX512 Doubleword and Quadword */
+	RTE_CPUFLAG_AVX512IFMA,             /**< AVX512 Integer Fused Multiply-Add */
 
 	/* The last item */
 	RTE_CPUFLAG_NUMFLAGS,               /**< This should always be the last! */
-- 
2.17.1

[dpdk-dev] [PATCH 03/17] eal/cpuflags: add avx512 conflict detection

[Kevin Laatz]

Add the CPU flag for AVX-512 conflict detection instructions.

Signed-off-by: Kevin Laatz <kevin.laatz@intel.com>
---
 lib/librte_eal/common/arch/x86/rte_cpuflags.c         | 1 +
 lib/librte_eal/common/include/arch/x86/rte_cpuflags.h | 1 +
 2 files changed, 2 insertions(+)

diff --git a/lib/librte_eal/common/arch/x86/rte_cpuflags.c b/lib/librte_eal/common/arch/x86/rte_cpuflags.c
index d56bd57f9..928b3513e 100644
--- a/lib/librte_eal/common/arch/x86/rte_cpuflags.c
+++ b/lib/librte_eal/common/arch/x86/rte_cpuflags.c
@@ -123,6 +123,7 @@ const struct feature_entry rte_cpu_feature_table[] = {
 
 	FEAT_DEF(AVX512DQ, 0x00000007, 0, RTE_REG_EBX, 17)
 	FEAT_DEF(AVX512IFMA, 0x00000007, 0, RTE_REG_EBX, 21)
+	FEAT_DEF(AVX512CD, 0x00000007, 0, RTE_REG_EBX, 28)
 };
 
 int
diff --git a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
index 81f510299..248a198a6 100644
--- a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
+++ b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
@@ -115,6 +115,7 @@ enum rte_cpu_flag_t {
 
 	RTE_CPUFLAG_AVX512DQ,               /**< AVX512 Doubleword and Quadword */
 	RTE_CPUFLAG_AVX512IFMA,             /**< AVX512 Integer Fused Multiply-Add */
+	RTE_CPUFLAG_AVX512CD,               /**< AVX512 Conflict Detection*/
 
 	/* The last item */
 	RTE_CPUFLAG_NUMFLAGS,               /**< This should always be the last! */
-- 
2.17.1

[dpdk-dev] [PATCH 04/17] eal/cpuflags: add avx512 byte and word

[Kevin Laatz]

Add the CPU flag for AVX-512 byte and word instructions.

Signed-off-by: Kevin Laatz <kevin.laatz@intel.com>
---
 lib/librte_eal/common/arch/x86/rte_cpuflags.c         | 1 +
 lib/librte_eal/common/include/arch/x86/rte_cpuflags.h | 1 +
 2 files changed, 2 insertions(+)

diff --git a/lib/librte_eal/common/arch/x86/rte_cpuflags.c b/lib/librte_eal/common/arch/x86/rte_cpuflags.c
index 928b3513e..c0bb1bd5c 100644
--- a/lib/librte_eal/common/arch/x86/rte_cpuflags.c
+++ b/lib/librte_eal/common/arch/x86/rte_cpuflags.c
@@ -124,6 +124,7 @@ const struct feature_entry rte_cpu_feature_table[] = {
 	FEAT_DEF(AVX512DQ, 0x00000007, 0, RTE_REG_EBX, 17)
 	FEAT_DEF(AVX512IFMA, 0x00000007, 0, RTE_REG_EBX, 21)
 	FEAT_DEF(AVX512CD, 0x00000007, 0, RTE_REG_EBX, 28)
+	FEAT_DEF(AVX512BW, 0x00000007, 0, RTE_REG_EBX, 30)
 };
 
 int
diff --git a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
index 248a198a6..97eeeb247 100644
--- a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
+++ b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
@@ -116,6 +116,7 @@ enum rte_cpu_flag_t {
 	RTE_CPUFLAG_AVX512DQ,               /**< AVX512 Doubleword and Quadword */
 	RTE_CPUFLAG_AVX512IFMA,             /**< AVX512 Integer Fused Multiply-Add */
 	RTE_CPUFLAG_AVX512CD,               /**< AVX512 Conflict Detection*/
+	RTE_CPUFLAG_AVX512BW,               /**< AVX512 Byte and Word */
 
 	/* The last item */
 	RTE_CPUFLAG_NUMFLAGS,               /**< This should always be the last! */
-- 
2.17.1

[dpdk-dev] [PATCH 05/17] eal/cpuflags: add avx512 vector length

[Kevin Laatz]

Add the CPU flag for AVX-512 vector length instructions.

Signed-off-by: Kevin Laatz <kevin.laatz@intel.com>
---
 lib/librte_eal/common/arch/x86/rte_cpuflags.c         | 1 +
 lib/librte_eal/common/include/arch/x86/rte_cpuflags.h | 1 +
 2 files changed, 2 insertions(+)

diff --git a/lib/librte_eal/common/arch/x86/rte_cpuflags.c b/lib/librte_eal/common/arch/x86/rte_cpuflags.c
index c0bb1bd5c..21cb4b649 100644
--- a/lib/librte_eal/common/arch/x86/rte_cpuflags.c
+++ b/lib/librte_eal/common/arch/x86/rte_cpuflags.c
@@ -125,6 +125,7 @@ const struct feature_entry rte_cpu_feature_table[] = {
 	FEAT_DEF(AVX512IFMA, 0x00000007, 0, RTE_REG_EBX, 21)
 	FEAT_DEF(AVX512CD, 0x00000007, 0, RTE_REG_EBX, 28)
 	FEAT_DEF(AVX512BW, 0x00000007, 0, RTE_REG_EBX, 30)
+	FEAT_DEF(AVX512VL, 0x00000007, 0, RTE_REG_EBX, 31)
 };
 
 int
diff --git a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
index 97eeeb247..42181e32c 100644
--- a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
+++ b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
@@ -117,6 +117,7 @@ enum rte_cpu_flag_t {
 	RTE_CPUFLAG_AVX512IFMA,             /**< AVX512 Integer Fused Multiply-Add */
 	RTE_CPUFLAG_AVX512CD,               /**< AVX512 Conflict Detection*/
 	RTE_CPUFLAG_AVX512BW,               /**< AVX512 Byte and Word */
+	RTE_CPUFLAG_AVX512VL,               /**< AVX512 Vector Length */
 
 	/* The last item */
 	RTE_CPUFLAG_NUMFLAGS,               /**< This should always be the last! */
-- 
2.17.1

[dpdk-dev] [PATCH 06/17] eal/cpuflags: add avx512 vector bit manipulation

[Kevin Laatz]

Add the CPU flag for AVX-512 vector bit manipulation instructions.

Signed-off-by: Kevin Laatz <kevin.laatz@intel.com>
---
 lib/librte_eal/common/arch/x86/rte_cpuflags.c         | 1 +
 lib/librte_eal/common/include/arch/x86/rte_cpuflags.h | 1 +
 2 files changed, 2 insertions(+)

diff --git a/lib/librte_eal/common/arch/x86/rte_cpuflags.c b/lib/librte_eal/common/arch/x86/rte_cpuflags.c
index 21cb4b649..773b14074 100644
--- a/lib/librte_eal/common/arch/x86/rte_cpuflags.c
+++ b/lib/librte_eal/common/arch/x86/rte_cpuflags.c
@@ -126,6 +126,7 @@ const struct feature_entry rte_cpu_feature_table[] = {
 	FEAT_DEF(AVX512CD, 0x00000007, 0, RTE_REG_EBX, 28)
 	FEAT_DEF(AVX512BW, 0x00000007, 0, RTE_REG_EBX, 30)
 	FEAT_DEF(AVX512VL, 0x00000007, 0, RTE_REG_EBX, 31)
+	FEAT_DEF(AVX512VBMI, 0x00000007, 0, RTE_REG_ECX, 1)
 };
 
 int
diff --git a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
index 42181e32c..453193875 100644
--- a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
+++ b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
@@ -118,6 +118,7 @@ enum rte_cpu_flag_t {
 	RTE_CPUFLAG_AVX512CD,               /**< AVX512 Conflict Detection*/
 	RTE_CPUFLAG_AVX512BW,               /**< AVX512 Byte and Word */
 	RTE_CPUFLAG_AVX512VL,               /**< AVX512 Vector Length */
+	RTE_CPUFLAG_AVX512VBMI,             /**< AVX512 Vector Bit Manipulation */
 
 	/* The last item */
 	RTE_CPUFLAG_NUMFLAGS,               /**< This should always be the last! */
-- 
2.17.1

[dpdk-dev] [PATCH 07/17] eal/cpuflags: add avx512 vector bit manipulation 2

[Kevin Laatz]

Add the CPU flag for AVX-512 vector bit manipulation 2 instructions.

Signed-off-by: Kevin Laatz <kevin.laatz@intel.com>
---
 lib/librte_eal/common/arch/x86/rte_cpuflags.c         | 1 +
 lib/librte_eal/common/include/arch/x86/rte_cpuflags.h | 1 +
 2 files changed, 2 insertions(+)

diff --git a/lib/librte_eal/common/arch/x86/rte_cpuflags.c b/lib/librte_eal/common/arch/x86/rte_cpuflags.c
index 773b14074..d1ef7e229 100644
--- a/lib/librte_eal/common/arch/x86/rte_cpuflags.c
+++ b/lib/librte_eal/common/arch/x86/rte_cpuflags.c
@@ -127,6 +127,7 @@ const struct feature_entry rte_cpu_feature_table[] = {
 	FEAT_DEF(AVX512BW, 0x00000007, 0, RTE_REG_EBX, 30)
 	FEAT_DEF(AVX512VL, 0x00000007, 0, RTE_REG_EBX, 31)
 	FEAT_DEF(AVX512VBMI, 0x00000007, 0, RTE_REG_ECX, 1)
+	FEAT_DEF(AVX512VBMI2, 0x00000007, 0, RTE_REG_ECX, 6)
 };
 
 int
diff --git a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
index 453193875..8544f9dca 100644
--- a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
+++ b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
@@ -119,6 +119,7 @@ enum rte_cpu_flag_t {
 	RTE_CPUFLAG_AVX512BW,               /**< AVX512 Byte and Word */
 	RTE_CPUFLAG_AVX512VL,               /**< AVX512 Vector Length */
 	RTE_CPUFLAG_AVX512VBMI,             /**< AVX512 Vector Bit Manipulation */
+	RTE_CPUFLAG_AVX512VBMI2,            /**< AVX512 Vector Bit Manipulation 2 */
 
 	/* The last item */
 	RTE_CPUFLAG_NUMFLAGS,               /**< This should always be the last! */
-- 
2.17.1

[dpdk-dev] [PATCH 08/17] eal/cpuflags: add galois field new instructions

[Kevin Laatz]

Add the CPU flag for Galois field new instructions.

Signed-off-by: Kevin Laatz <kevin.laatz@intel.com>
---
 lib/librte_eal/common/arch/x86/rte_cpuflags.c         | 1 +
 lib/librte_eal/common/include/arch/x86/rte_cpuflags.h | 1 +
 2 files changed, 2 insertions(+)

diff --git a/lib/librte_eal/common/arch/x86/rte_cpuflags.c b/lib/librte_eal/common/arch/x86/rte_cpuflags.c
index d1ef7e229..c2a484789 100644
--- a/lib/librte_eal/common/arch/x86/rte_cpuflags.c
+++ b/lib/librte_eal/common/arch/x86/rte_cpuflags.c
@@ -128,6 +128,7 @@ const struct feature_entry rte_cpu_feature_table[] = {
 	FEAT_DEF(AVX512VL, 0x00000007, 0, RTE_REG_EBX, 31)
 	FEAT_DEF(AVX512VBMI, 0x00000007, 0, RTE_REG_ECX, 1)
 	FEAT_DEF(AVX512VBMI2, 0x00000007, 0, RTE_REG_ECX, 6)
+	FEAT_DEF(GFNI, 0x00000007, 0, RTE_REG_ECX, 8)
 };
 
 int
diff --git a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
index 8544f9dca..94714c98b 100644
--- a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
+++ b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
@@ -120,6 +120,7 @@ enum rte_cpu_flag_t {
 	RTE_CPUFLAG_AVX512VL,               /**< AVX512 Vector Length */
 	RTE_CPUFLAG_AVX512VBMI,             /**< AVX512 Vector Bit Manipulation */
 	RTE_CPUFLAG_AVX512VBMI2,            /**< AVX512 Vector Bit Manipulation 2 */
+	RTE_CPUFLAG_GFNI,                   /**< Galois Field New Instructions */
 
 	/* The last item */
 	RTE_CPUFLAG_NUMFLAGS,               /**< This should always be the last! */
-- 
2.17.1

[dpdk-dev] [PATCH 09/17] eal/cpuflags: add vector AES

[Kevin Laatz]

Add the CPU flag for vector AES instructions.

Signed-off-by: Kevin Laatz <kevin.laatz@intel.com>
---
 lib/librte_eal/common/arch/x86/rte_cpuflags.c         | 1 +
 lib/librte_eal/common/include/arch/x86/rte_cpuflags.h | 1 +
 2 files changed, 2 insertions(+)

diff --git a/lib/librte_eal/common/arch/x86/rte_cpuflags.c b/lib/librte_eal/common/arch/x86/rte_cpuflags.c
index c2a484789..d4caf76d8 100644
--- a/lib/librte_eal/common/arch/x86/rte_cpuflags.c
+++ b/lib/librte_eal/common/arch/x86/rte_cpuflags.c
@@ -129,6 +129,7 @@ const struct feature_entry rte_cpu_feature_table[] = {
 	FEAT_DEF(AVX512VBMI, 0x00000007, 0, RTE_REG_ECX, 1)
 	FEAT_DEF(AVX512VBMI2, 0x00000007, 0, RTE_REG_ECX, 6)
 	FEAT_DEF(GFNI, 0x00000007, 0, RTE_REG_ECX, 8)
+	FEAT_DEF(VAES, 0x00000007, 0, RTE_REG_ECX, 9)
 };
 
 int
diff --git a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
index 94714c98b..22efc166f 100644
--- a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
+++ b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
@@ -121,6 +121,7 @@ enum rte_cpu_flag_t {
 	RTE_CPUFLAG_AVX512VBMI,             /**< AVX512 Vector Bit Manipulation */
 	RTE_CPUFLAG_AVX512VBMI2,            /**< AVX512 Vector Bit Manipulation 2 */
 	RTE_CPUFLAG_GFNI,                   /**< Galois Field New Instructions */
+	RTE_CPUFLAG_VAES,                   /**< Vector AES */
 
 	/* The last item */
 	RTE_CPUFLAG_NUMFLAGS,               /**< This should always be the last! */
-- 
2.17.1

[dpdk-dev] [PATCH 10/17] eal/cpuflags: add vector carry-less multiply

[Kevin Laatz]

Add the CPU flag for vector carry-less multiply instructions.

Signed-off-by: Kevin Laatz <kevin.laatz@intel.com>
---
 lib/librte_eal/common/arch/x86/rte_cpuflags.c         | 1 +
 lib/librte_eal/common/include/arch/x86/rte_cpuflags.h | 1 +
 2 files changed, 2 insertions(+)

diff --git a/lib/librte_eal/common/arch/x86/rte_cpuflags.c b/lib/librte_eal/common/arch/x86/rte_cpuflags.c
index d4caf76d8..b01f35e1a 100644
--- a/lib/librte_eal/common/arch/x86/rte_cpuflags.c
+++ b/lib/librte_eal/common/arch/x86/rte_cpuflags.c
@@ -130,6 +130,7 @@ const struct feature_entry rte_cpu_feature_table[] = {
 	FEAT_DEF(AVX512VBMI2, 0x00000007, 0, RTE_REG_ECX, 6)
 	FEAT_DEF(GFNI, 0x00000007, 0, RTE_REG_ECX, 8)
 	FEAT_DEF(VAES, 0x00000007, 0, RTE_REG_ECX, 9)
+	FEAT_DEF(VPCLMULQDQ, 0x00000007, 0, RTE_REG_ECX, 10)
 };
 
 int
diff --git a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
index 22efc166f..cbcb1cf71 100644
--- a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
+++ b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
@@ -122,6 +122,7 @@ enum rte_cpu_flag_t {
 	RTE_CPUFLAG_AVX512VBMI2,            /**< AVX512 Vector Bit Manipulation 2 */
 	RTE_CPUFLAG_GFNI,                   /**< Galois Field New Instructions */
 	RTE_CPUFLAG_VAES,                   /**< Vector AES */
+	RTE_CPUFLAG_VPCLMULQDQ,             /**< Vector Carry-less Multiply */
 
 	/* The last item */
 	RTE_CPUFLAG_NUMFLAGS,               /**< This should always be the last! */
-- 
2.17.1

[dpdk-dev] [PATCH 11/17] eal/cpuflags: add avx512 vector neural network instructions

[Kevin Laatz]

Add the CPU flag for AVX-512 vector neural network instructions.

Signed-off-by: Kevin Laatz <kevin.laatz@intel.com>
---
 lib/librte_eal/common/arch/x86/rte_cpuflags.c         | 1 +
 lib/librte_eal/common/include/arch/x86/rte_cpuflags.h | 1 +
 2 files changed, 2 insertions(+)

diff --git a/lib/librte_eal/common/arch/x86/rte_cpuflags.c b/lib/librte_eal/common/arch/x86/rte_cpuflags.c
index b01f35e1a..f82d45647 100644
--- a/lib/librte_eal/common/arch/x86/rte_cpuflags.c
+++ b/lib/librte_eal/common/arch/x86/rte_cpuflags.c
@@ -131,6 +131,7 @@ const struct feature_entry rte_cpu_feature_table[] = {
 	FEAT_DEF(GFNI, 0x00000007, 0, RTE_REG_ECX, 8)
 	FEAT_DEF(VAES, 0x00000007, 0, RTE_REG_ECX, 9)
 	FEAT_DEF(VPCLMULQDQ, 0x00000007, 0, RTE_REG_ECX, 10)
+	FEAT_DEF(AVX512VNNI, 0x00000007, 0, RTE_REG_ECX, 11)
 };
 
 int
diff --git a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
index cbcb1cf71..caf92b9f3 100644
--- a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
+++ b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
@@ -123,6 +123,7 @@ enum rte_cpu_flag_t {
 	RTE_CPUFLAG_GFNI,                   /**< Galois Field New Instructions */
 	RTE_CPUFLAG_VAES,                   /**< Vector AES */
 	RTE_CPUFLAG_VPCLMULQDQ,             /**< Vector Carry-less Multiply */
+	RTE_CPUFLAG_AVX512VNNI,             /**< AVX512 Vector Neural Network Instructions */
 
 	/* The last item */
 	RTE_CPUFLAG_NUMFLAGS,               /**< This should always be the last! */
-- 
2.17.1

[dpdk-dev] [PATCH 12/17] eal/cpuflags: add avx512 bit algorithms

[Kevin Laatz]

Add the CPU flag AVX-512 for bit algorithm instructions.

Signed-off-by: Kevin Laatz <kevin.laatz@intel.com>
---
 lib/librte_eal/common/arch/x86/rte_cpuflags.c         | 1 +
 lib/librte_eal/common/include/arch/x86/rte_cpuflags.h | 1 +
 2 files changed, 2 insertions(+)

diff --git a/lib/librte_eal/common/arch/x86/rte_cpuflags.c b/lib/librte_eal/common/arch/x86/rte_cpuflags.c
index f82d45647..472becfed 100644
--- a/lib/librte_eal/common/arch/x86/rte_cpuflags.c
+++ b/lib/librte_eal/common/arch/x86/rte_cpuflags.c
@@ -132,6 +132,7 @@ const struct feature_entry rte_cpu_feature_table[] = {
 	FEAT_DEF(VAES, 0x00000007, 0, RTE_REG_ECX, 9)
 	FEAT_DEF(VPCLMULQDQ, 0x00000007, 0, RTE_REG_ECX, 10)
 	FEAT_DEF(AVX512VNNI, 0x00000007, 0, RTE_REG_ECX, 11)
+	FEAT_DEF(AVX512BITALG, 0x00000007, 0, RTE_REG_ECX, 12)
 };
 
 int
diff --git a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
index caf92b9f3..fe4144fc0 100644
--- a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
+++ b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
@@ -124,6 +124,7 @@ enum rte_cpu_flag_t {
 	RTE_CPUFLAG_VAES,                   /**< Vector AES */
 	RTE_CPUFLAG_VPCLMULQDQ,             /**< Vector Carry-less Multiply */
 	RTE_CPUFLAG_AVX512VNNI,             /**< AVX512 Vector Neural Network Instructions */
+	RTE_CPUFLAG_AVX512BITALG,           /**< AVX512 Bit Algorithms */
 
 	/* The last item */
 	RTE_CPUFLAG_NUMFLAGS,               /**< This should always be the last! */
-- 
2.17.1

[dpdk-dev] [PATCH 13/17] eal/cpuflags: add avx512 vector popcount

[Kevin Laatz]

Add the CPU flag for AVX-512 vector popcount instructions.

Signed-off-by: Harry van Haaren <harry.van.haaren@intel.com>
Signed-off-by: Kevin Laatz <kevin.laatz@intel.com>
---
 lib/librte_eal/common/arch/x86/rte_cpuflags.c         | 1 +
 lib/librte_eal/common/include/arch/x86/rte_cpuflags.h | 1 +
 2 files changed, 2 insertions(+)

diff --git a/lib/librte_eal/common/arch/x86/rte_cpuflags.c b/lib/librte_eal/common/arch/x86/rte_cpuflags.c
index 472becfed..0b1458d77 100644
--- a/lib/librte_eal/common/arch/x86/rte_cpuflags.c
+++ b/lib/librte_eal/common/arch/x86/rte_cpuflags.c
@@ -133,6 +133,7 @@ const struct feature_entry rte_cpu_feature_table[] = {
 	FEAT_DEF(VPCLMULQDQ, 0x00000007, 0, RTE_REG_ECX, 10)
 	FEAT_DEF(AVX512VNNI, 0x00000007, 0, RTE_REG_ECX, 11)
 	FEAT_DEF(AVX512BITALG, 0x00000007, 0, RTE_REG_ECX, 12)
+	FEAT_DEF(AVX512VPOPCNTDQ, 0x00000007, 0, RTE_REG_ECX,  14)
 };
 
 int
diff --git a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
index fe4144fc0..63281ef5e 100644
--- a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
+++ b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
@@ -125,6 +125,7 @@ enum rte_cpu_flag_t {
 	RTE_CPUFLAG_VPCLMULQDQ,             /**< Vector Carry-less Multiply */
 	RTE_CPUFLAG_AVX512VNNI,             /**< AVX512 Vector Neural Network Instructions */
 	RTE_CPUFLAG_AVX512BITALG,           /**< AVX512 Bit Algorithms */
+	RTE_CPUFLAG_AVX512VPOPCNTDQ,        /**< AVX512 Vector Popcount */
 
 	/* The last item */
 	RTE_CPUFLAG_NUMFLAGS,               /**< This should always be the last! */
-- 
2.17.1

[dpdk-dev] [PATCH 14/17] eal/cpuflags: add cache line demote

[Kevin Laatz]

Add the CPU flag for cache line demote instructions.

Signed-off-by: Kevin Laatz <kevin.laatz@intel.com>
---
 lib/librte_eal/common/arch/x86/rte_cpuflags.c         | 1 +
 lib/librte_eal/common/include/arch/x86/rte_cpuflags.h | 1 +
 2 files changed, 2 insertions(+)

diff --git a/lib/librte_eal/common/arch/x86/rte_cpuflags.c b/lib/librte_eal/common/arch/x86/rte_cpuflags.c
index 0b1458d77..ac1de715d 100644
--- a/lib/librte_eal/common/arch/x86/rte_cpuflags.c
+++ b/lib/librte_eal/common/arch/x86/rte_cpuflags.c
@@ -134,6 +134,7 @@ const struct feature_entry rte_cpu_feature_table[] = {
 	FEAT_DEF(AVX512VNNI, 0x00000007, 0, RTE_REG_ECX, 11)
 	FEAT_DEF(AVX512BITALG, 0x00000007, 0, RTE_REG_ECX, 12)
 	FEAT_DEF(AVX512VPOPCNTDQ, 0x00000007, 0, RTE_REG_ECX,  14)
+	FEAT_DEF(CLDEMOTE, 0x00000007, 0, RTE_REG_ECX, 25)
 };
 
 int
diff --git a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
index 63281ef5e..3a60f3e68 100644
--- a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
+++ b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
@@ -126,6 +126,7 @@ enum rte_cpu_flag_t {
 	RTE_CPUFLAG_AVX512VNNI,             /**< AVX512 Vector Neural Network Instructions */
 	RTE_CPUFLAG_AVX512BITALG,           /**< AVX512 Bit Algorithms */
 	RTE_CPUFLAG_AVX512VPOPCNTDQ,        /**< AVX512 Vector Popcount */
+	RTE_CPUFLAG_CLDEMOTE,               /**< Cache Line Demote */
 
 	/* The last item */
 	RTE_CPUFLAG_NUMFLAGS,               /**< This should always be the last! */
-- 
2.17.1

[dpdk-dev] [PATCH 15/17] eal/cpuflags: add direct store instructions

[Kevin Laatz]

Add the CPU flag for direct store instructions.

Signed-off-by: Kevin Laatz <kevin.laatz@intel.com>
---
 lib/librte_eal/common/arch/x86/rte_cpuflags.c         | 1 +
 lib/librte_eal/common/include/arch/x86/rte_cpuflags.h | 1 +
 2 files changed, 2 insertions(+)

diff --git a/lib/librte_eal/common/arch/x86/rte_cpuflags.c b/lib/librte_eal/common/arch/x86/rte_cpuflags.c
index ac1de715d..eb9f6b59d 100644
--- a/lib/librte_eal/common/arch/x86/rte_cpuflags.c
+++ b/lib/librte_eal/common/arch/x86/rte_cpuflags.c
@@ -135,6 +135,7 @@ const struct feature_entry rte_cpu_feature_table[] = {
 	FEAT_DEF(AVX512BITALG, 0x00000007, 0, RTE_REG_ECX, 12)
 	FEAT_DEF(AVX512VPOPCNTDQ, 0x00000007, 0, RTE_REG_ECX,  14)
 	FEAT_DEF(CLDEMOTE, 0x00000007, 0, RTE_REG_ECX, 25)
+	FEAT_DEF(MOVDIRI, 0x00000007, 0, RTE_REG_ECX, 27)
 };
 
 int
diff --git a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
index 3a60f3e68..b39abfc38 100644
--- a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
+++ b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
@@ -127,6 +127,7 @@ enum rte_cpu_flag_t {
 	RTE_CPUFLAG_AVX512BITALG,           /**< AVX512 Bit Algorithms */
 	RTE_CPUFLAG_AVX512VPOPCNTDQ,        /**< AVX512 Vector Popcount */
 	RTE_CPUFLAG_CLDEMOTE,               /**< Cache Line Demote */
+	RTE_CPUFLAG_MOVDIRI,                /**< Direct Store Instructions */
 
 	/* The last item */
 	RTE_CPUFLAG_NUMFLAGS,               /**< This should always be the last! */
-- 
2.17.1

[dpdk-dev] [PATCH 16/17] eal/cpuflags: add direct store instructions 64B

[Kevin Laatz]

Add the CPU flag for direct store 64B instructions.

Signed-off-by: Kevin Laatz <kevin.laatz@intel.com>
---
 lib/librte_eal/common/arch/x86/rte_cpuflags.c         | 1 +
 lib/librte_eal/common/include/arch/x86/rte_cpuflags.h | 1 +
 2 files changed, 2 insertions(+)

diff --git a/lib/librte_eal/common/arch/x86/rte_cpuflags.c b/lib/librte_eal/common/arch/x86/rte_cpuflags.c
index eb9f6b59d..164381684 100644
--- a/lib/librte_eal/common/arch/x86/rte_cpuflags.c
+++ b/lib/librte_eal/common/arch/x86/rte_cpuflags.c
@@ -136,6 +136,7 @@ const struct feature_entry rte_cpu_feature_table[] = {
 	FEAT_DEF(AVX512VPOPCNTDQ, 0x00000007, 0, RTE_REG_ECX,  14)
 	FEAT_DEF(CLDEMOTE, 0x00000007, 0, RTE_REG_ECX, 25)
 	FEAT_DEF(MOVDIRI, 0x00000007, 0, RTE_REG_ECX, 27)
+	FEAT_DEF(MOVDIR64B, 0x00000007, 0, RTE_REG_ECX, 28)
 };
 
 int
diff --git a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
index b39abfc38..2379d073d 100644
--- a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
+++ b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
@@ -128,6 +128,7 @@ enum rte_cpu_flag_t {
 	RTE_CPUFLAG_AVX512VPOPCNTDQ,        /**< AVX512 Vector Popcount */
 	RTE_CPUFLAG_CLDEMOTE,               /**< Cache Line Demote */
 	RTE_CPUFLAG_MOVDIRI,                /**< Direct Store Instructions */
+	RTE_CPUFLAG_MOVDIR64B,              /**< Direct Store Instructions 64B */
 
 	/* The last item */
 	RTE_CPUFLAG_NUMFLAGS,               /**< This should always be the last! */
-- 
2.17.1

[dpdk-dev] [PATCH 17/17] eal/cpuflags: add avx512 two register intersection

[Kevin Laatz]

Add the CPU flag for AVX-512 two register intersection instructions.

Signed-off-by: Kevin Laatz <kevin.laatz@intel.com>
---
 lib/librte_eal/common/arch/x86/rte_cpuflags.c         | 1 +
 lib/librte_eal/common/include/arch/x86/rte_cpuflags.h | 1 +
 2 files changed, 2 insertions(+)

diff --git a/lib/librte_eal/common/arch/x86/rte_cpuflags.c b/lib/librte_eal/common/arch/x86/rte_cpuflags.c
index 164381684..30439e795 100644
--- a/lib/librte_eal/common/arch/x86/rte_cpuflags.c
+++ b/lib/librte_eal/common/arch/x86/rte_cpuflags.c
@@ -137,6 +137,7 @@ const struct feature_entry rte_cpu_feature_table[] = {
 	FEAT_DEF(CLDEMOTE, 0x00000007, 0, RTE_REG_ECX, 25)
 	FEAT_DEF(MOVDIRI, 0x00000007, 0, RTE_REG_ECX, 27)
 	FEAT_DEF(MOVDIR64B, 0x00000007, 0, RTE_REG_ECX, 28)
+	FEAT_DEF(AVX512VP2INTERSECT, 0x00000007, 0, RTE_REG_EDX, 8)
 };
 
 int
diff --git a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
index 2379d073d..f8f73b19f 100644
--- a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
+++ b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
@@ -129,6 +129,7 @@ enum rte_cpu_flag_t {
 	RTE_CPUFLAG_CLDEMOTE,               /**< Cache Line Demote */
 	RTE_CPUFLAG_MOVDIRI,                /**< Direct Store Instructions */
 	RTE_CPUFLAG_MOVDIR64B,              /**< Direct Store Instructions 64B */
+	RTE_CPUFLAG_AVX512VP2INTERSECT,     /**< AVX512 Two Register Intersection */
 
 	/* The last item */
 	RTE_CPUFLAG_NUMFLAGS,               /**< This should always be the last! */
-- 
2.17.1

Re: [dpdk-dev] [PATCH 00/17] Add CPU flags

[David Marchand]

On Tue, Mar 24, 2020 at 12:49 PM Kevin Laatz <kevin.laatz@intel.com> wrote:
> This patch set adds CPU flags which will enable the detection of ISA
> features available on more recent x86 based CPUs.
>
> The CPUID leaf information can be found in Section 1.7 of this
> document:
> https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
>
> Kevin Laatz (17):
>   eal/cpuflags: add avx512 doubleword and quadword
>   eal/cpuflags: add avx512 integer fused multiply-add
>   eal/cpuflags: add avx512 conflict detection
>   eal/cpuflags: add avx512 byte and word
>   eal/cpuflags: add avx512 vector length
>   eal/cpuflags: add avx512 vector bit manipulation
>   eal/cpuflags: add avx512 vector bit manipulation 2
>   eal/cpuflags: add galois field new instructions
>   eal/cpuflags: add vector AES
>   eal/cpuflags: add vector carry-less multiply
>   eal/cpuflags: add avx512 vector neural network instructions
>   eal/cpuflags: add avx512 bit algorithms
>   eal/cpuflags: add avx512 vector popcount
>   eal/cpuflags: add cache line demote
>   eal/cpuflags: add direct store instructions
>   eal/cpuflags: add direct store instructions 64B
>   eal/cpuflags: add avx512 two register intersection
>
>  lib/librte_eal/common/arch/x86/rte_cpuflags.c  | 18 ++++++++++++++++++
>  .../common/include/arch/x86/rte_cpuflags.h     | 18 ++++++++++++++++++
>  2 files changed, 36 insertions(+)

You are just adding definitions, the review should be straightforward
for guys in the know.
I can see little value in splitting in that many patches.


-- 
David Marchand

[dpdk-dev] [PATCH v2] eal/cpuflags: add x86 based cpu flags

[Kevin Laatz]

This patch adds CPU flags which will enable the detection of ISA
features available on more recent x86 based CPUs.

The CPUID leaf information can be found in Section 1.7 of this
document:
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf

The following CPU flags are added in this patch:
    - AVX-512 doubleword and quadword instructions.
    - AVX-512 integer fused multiply-add instructions.
    - AVX-512 conflict detection instructions.
    - AVX-512 byte and word instructions.
    - AVX-512 vector length instructions.
    - AVX-512 vector bit manipulation instructions.
    - AVX-512 vector bit manipulation 2 instructions.
    - Galois field new instructions.
    - Vector AES instructions.
    - Vector carry-less multiply instructions.
    - AVX-512 vector neural network instructions.
    - AVX-512 for bit algorithm instructions.
    - AVX-512 vector popcount instructions.
    - Cache line demote instructions.
    - Direct store instructions.
    - Direct store 64B instructions.
    - AVX-512 two register intersection instructions.

Signed-off-by: Kevin Laatz <kevin.laatz@intel.com>
---
 lib/librte_eal/common/arch/x86/rte_cpuflags.c  | 18 ++++++++++++++++++
 .../common/include/arch/x86/rte_cpuflags.h     | 18 ++++++++++++++++++
 2 files changed, 36 insertions(+)

diff --git a/lib/librte_eal/common/arch/x86/rte_cpuflags.c b/lib/librte_eal/common/arch/x86/rte_cpuflags.c
index 6492df556..30439e795 100644
--- a/lib/librte_eal/common/arch/x86/rte_cpuflags.c
+++ b/lib/librte_eal/common/arch/x86/rte_cpuflags.c
@@ -120,6 +120,24 @@ const struct feature_entry rte_cpu_feature_table[] = {
 	FEAT_DEF(EM64T, 0x80000001, 0, RTE_REG_EDX, 29)
 
 	FEAT_DEF(INVTSC, 0x80000007, 0, RTE_REG_EDX,  8)
+
+	FEAT_DEF(AVX512DQ, 0x00000007, 0, RTE_REG_EBX, 17)
+	FEAT_DEF(AVX512IFMA, 0x00000007, 0, RTE_REG_EBX, 21)
+	FEAT_DEF(AVX512CD, 0x00000007, 0, RTE_REG_EBX, 28)
+	FEAT_DEF(AVX512BW, 0x00000007, 0, RTE_REG_EBX, 30)
+	FEAT_DEF(AVX512VL, 0x00000007, 0, RTE_REG_EBX, 31)
+	FEAT_DEF(AVX512VBMI, 0x00000007, 0, RTE_REG_ECX, 1)
+	FEAT_DEF(AVX512VBMI2, 0x00000007, 0, RTE_REG_ECX, 6)
+	FEAT_DEF(GFNI, 0x00000007, 0, RTE_REG_ECX, 8)
+	FEAT_DEF(VAES, 0x00000007, 0, RTE_REG_ECX, 9)
+	FEAT_DEF(VPCLMULQDQ, 0x00000007, 0, RTE_REG_ECX, 10)
+	FEAT_DEF(AVX512VNNI, 0x00000007, 0, RTE_REG_ECX, 11)
+	FEAT_DEF(AVX512BITALG, 0x00000007, 0, RTE_REG_ECX, 12)
+	FEAT_DEF(AVX512VPOPCNTDQ, 0x00000007, 0, RTE_REG_ECX,  14)
+	FEAT_DEF(CLDEMOTE, 0x00000007, 0, RTE_REG_ECX, 25)
+	FEAT_DEF(MOVDIRI, 0x00000007, 0, RTE_REG_ECX, 27)
+	FEAT_DEF(MOVDIR64B, 0x00000007, 0, RTE_REG_ECX, 28)
+	FEAT_DEF(AVX512VP2INTERSECT, 0x00000007, 0, RTE_REG_EDX, 8)
 };
 
 int
diff --git a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
index 25ba47b96..f8f73b19f 100644
--- a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
+++ b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
@@ -113,6 +113,24 @@ enum rte_cpu_flag_t {
 	/* (EAX 80000007h) EDX features */
 	RTE_CPUFLAG_INVTSC,                 /**< INVTSC */
 
+	RTE_CPUFLAG_AVX512DQ,               /**< AVX512 Doubleword and Quadword */
+	RTE_CPUFLAG_AVX512IFMA,             /**< AVX512 Integer Fused Multiply-Add */
+	RTE_CPUFLAG_AVX512CD,               /**< AVX512 Conflict Detection*/
+	RTE_CPUFLAG_AVX512BW,               /**< AVX512 Byte and Word */
+	RTE_CPUFLAG_AVX512VL,               /**< AVX512 Vector Length */
+	RTE_CPUFLAG_AVX512VBMI,             /**< AVX512 Vector Bit Manipulation */
+	RTE_CPUFLAG_AVX512VBMI2,            /**< AVX512 Vector Bit Manipulation 2 */
+	RTE_CPUFLAG_GFNI,                   /**< Galois Field New Instructions */
+	RTE_CPUFLAG_VAES,                   /**< Vector AES */
+	RTE_CPUFLAG_VPCLMULQDQ,             /**< Vector Carry-less Multiply */
+	RTE_CPUFLAG_AVX512VNNI,             /**< AVX512 Vector Neural Network Instructions */
+	RTE_CPUFLAG_AVX512BITALG,           /**< AVX512 Bit Algorithms */
+	RTE_CPUFLAG_AVX512VPOPCNTDQ,        /**< AVX512 Vector Popcount */
+	RTE_CPUFLAG_CLDEMOTE,               /**< Cache Line Demote */
+	RTE_CPUFLAG_MOVDIRI,                /**< Direct Store Instructions */
+	RTE_CPUFLAG_MOVDIR64B,              /**< Direct Store Instructions 64B */
+	RTE_CPUFLAG_AVX512VP2INTERSECT,     /**< AVX512 Two Register Intersection */
+
 	/* The last item */
 	RTE_CPUFLAG_NUMFLAGS,               /**< This should always be the last! */
 };
-- 
2.17.1

Re: [dpdk-dev] [PATCH v2] eal/cpuflags: add x86 based cpu flags

[David Marchand]

On Wed, Mar 25, 2020 at 12:11 PM Kevin Laatz <kevin.laatz@intel.com> wrote:
>
> This patch adds CPU flags which will enable the detection of ISA
> features available on more recent x86 based CPUs.
>
> The CPUID leaf information can be found in Section 1.7 of this
> document:
> https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
>
> The following CPU flags are added in this patch:
>     - AVX-512 doubleword and quadword instructions.
>     - AVX-512 integer fused multiply-add instructions.
>     - AVX-512 conflict detection instructions.
>     - AVX-512 byte and word instructions.
>     - AVX-512 vector length instructions.
>     - AVX-512 vector bit manipulation instructions.
>     - AVX-512 vector bit manipulation 2 instructions.
>     - Galois field new instructions.
>     - Vector AES instructions.
>     - Vector carry-less multiply instructions.
>     - AVX-512 vector neural network instructions.
>     - AVX-512 for bit algorithm instructions.
>     - AVX-512 vector popcount instructions.
>     - Cache line demote instructions.
>     - Direct store instructions.
>     - Direct store 64B instructions.
>     - AVX-512 two register intersection instructions.
>
> Signed-off-by: Kevin Laatz <kevin.laatz@intel.com>
> ---
>  lib/librte_eal/common/arch/x86/rte_cpuflags.c  | 18 ++++++++++++++++++
>  .../common/include/arch/x86/rte_cpuflags.h     | 18 ++++++++++++++++++
>  2 files changed, 36 insertions(+)
>
> diff --git a/lib/librte_eal/common/arch/x86/rte_cpuflags.c b/lib/librte_eal/common/arch/x86/rte_cpuflags.c
> index 6492df556..30439e795 100644
> --- a/lib/librte_eal/common/arch/x86/rte_cpuflags.c
> +++ b/lib/librte_eal/common/arch/x86/rte_cpuflags.c
> @@ -120,6 +120,24 @@ const struct feature_entry rte_cpu_feature_table[] = {
>         FEAT_DEF(EM64T, 0x80000001, 0, RTE_REG_EDX, 29)
>
>         FEAT_DEF(INVTSC, 0x80000007, 0, RTE_REG_EDX,  8)
> +
> +       FEAT_DEF(AVX512DQ, 0x00000007, 0, RTE_REG_EBX, 17)
> +       FEAT_DEF(AVX512IFMA, 0x00000007, 0, RTE_REG_EBX, 21)
> +       FEAT_DEF(AVX512CD, 0x00000007, 0, RTE_REG_EBX, 28)
> +       FEAT_DEF(AVX512BW, 0x00000007, 0, RTE_REG_EBX, 30)
> +       FEAT_DEF(AVX512VL, 0x00000007, 0, RTE_REG_EBX, 31)
> +       FEAT_DEF(AVX512VBMI, 0x00000007, 0, RTE_REG_ECX, 1)
> +       FEAT_DEF(AVX512VBMI2, 0x00000007, 0, RTE_REG_ECX, 6)
> +       FEAT_DEF(GFNI, 0x00000007, 0, RTE_REG_ECX, 8)
> +       FEAT_DEF(VAES, 0x00000007, 0, RTE_REG_ECX, 9)
> +       FEAT_DEF(VPCLMULQDQ, 0x00000007, 0, RTE_REG_ECX, 10)
> +       FEAT_DEF(AVX512VNNI, 0x00000007, 0, RTE_REG_ECX, 11)
> +       FEAT_DEF(AVX512BITALG, 0x00000007, 0, RTE_REG_ECX, 12)
> +       FEAT_DEF(AVX512VPOPCNTDQ, 0x00000007, 0, RTE_REG_ECX,  14)
> +       FEAT_DEF(CLDEMOTE, 0x00000007, 0, RTE_REG_ECX, 25)
> +       FEAT_DEF(MOVDIRI, 0x00000007, 0, RTE_REG_ECX, 27)
> +       FEAT_DEF(MOVDIR64B, 0x00000007, 0, RTE_REG_ECX, 28)
> +       FEAT_DEF(AVX512VP2INTERSECT, 0x00000007, 0, RTE_REG_EDX, 8)
>  };
>
>  int
> diff --git a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
> index 25ba47b96..f8f73b19f 100644
> --- a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
> +++ b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
> @@ -113,6 +113,24 @@ enum rte_cpu_flag_t {
>         /* (EAX 80000007h) EDX features */
>         RTE_CPUFLAG_INVTSC,                 /**< INVTSC */
>
> +       RTE_CPUFLAG_AVX512DQ,               /**< AVX512 Doubleword and Quadword */
> +       RTE_CPUFLAG_AVX512IFMA,             /**< AVX512 Integer Fused Multiply-Add */
> +       RTE_CPUFLAG_AVX512CD,               /**< AVX512 Conflict Detection*/
> +       RTE_CPUFLAG_AVX512BW,               /**< AVX512 Byte and Word */
> +       RTE_CPUFLAG_AVX512VL,               /**< AVX512 Vector Length */
> +       RTE_CPUFLAG_AVX512VBMI,             /**< AVX512 Vector Bit Manipulation */
> +       RTE_CPUFLAG_AVX512VBMI2,            /**< AVX512 Vector Bit Manipulation 2 */
> +       RTE_CPUFLAG_GFNI,                   /**< Galois Field New Instructions */
> +       RTE_CPUFLAG_VAES,                   /**< Vector AES */
> +       RTE_CPUFLAG_VPCLMULQDQ,             /**< Vector Carry-less Multiply */
> +       RTE_CPUFLAG_AVX512VNNI,             /**< AVX512 Vector Neural Network Instructions */
> +       RTE_CPUFLAG_AVX512BITALG,           /**< AVX512 Bit Algorithms */
> +       RTE_CPUFLAG_AVX512VPOPCNTDQ,        /**< AVX512 Vector Popcount */
> +       RTE_CPUFLAG_CLDEMOTE,               /**< Cache Line Demote */
> +       RTE_CPUFLAG_MOVDIRI,                /**< Direct Store Instructions */
> +       RTE_CPUFLAG_MOVDIR64B,              /**< Direct Store Instructions 64B */
> +       RTE_CPUFLAG_AVX512VP2INTERSECT,     /**< AVX512 Two Register Intersection */
> +
>         /* The last item */
>         RTE_CPUFLAG_NUMFLAGS,               /**< This should always be the last! */

This is seen as an ABI break because of the change on _NUMFLAGS:
https://travis-ci.com/github/ovsrobot/dpdk/jobs/302524264#L2351


-- 
David Marchand

Re: [dpdk-dev] [PATCH v2] eal/cpuflags: add x86 based cpu flags

[Van Haaren, Harry]

> -----Original Message-----
> From: David Marchand <david.marchand@redhat.com>
> Sent: Friday, March 27, 2020 12:24 PM
> To: Laatz, Kevin <kevin.laatz@intel.com>
> Cc: dev <dev@dpdk.org>; Richardson, Bruce <bruce.richardson@intel.com>; Van
> Haaren, Harry <harry.van.haaren@intel.com>; Neil Horman
> <nhorman@tuxdriver.com>; Thomas Monjalon <thomas@monjalon.net>; Honnappa
> Nagarahalli <Honnappa.Nagarahalli@arm.com>; Dodji Seketeli <dodji@redhat.com>
> Subject: Re: [dpdk-dev] [PATCH v2] eal/cpuflags: add x86 based cpu flags
> 
> On Wed, Mar 25, 2020 at 12:11 PM Kevin Laatz <kevin.laatz@intel.com> wrote:
> >
> > This patch adds CPU flags which will enable the detection of ISA
> > features available on more recent x86 based CPUs.
> >
> > The CPUID leaf information can be found in Section 1.7 of this
> > document:
> > https://software.intel.com/sites/default/files/managed/c5/15/architecture-
> instruction-set-extensions-programming-reference.pdf
> >
> > The following CPU flags are added in this patch:
> >     - AVX-512 doubleword and quadword instructions.
> >     - AVX-512 integer fused multiply-add instructions.
> >     - AVX-512 conflict detection instructions.
> >     - AVX-512 byte and word instructions.
> >     - AVX-512 vector length instructions.
> >     - AVX-512 vector bit manipulation instructions.
> >     - AVX-512 vector bit manipulation 2 instructions.
> >     - Galois field new instructions.
> >     - Vector AES instructions.
> >     - Vector carry-less multiply instructions.
> >     - AVX-512 vector neural network instructions.
> >     - AVX-512 for bit algorithm instructions.
> >     - AVX-512 vector popcount instructions.
> >     - Cache line demote instructions.
> >     - Direct store instructions.
> >     - Direct store 64B instructions.
> >     - AVX-512 two register intersection instructions.
> >
> > Signed-off-by: Kevin Laatz <kevin.laatz@intel.com>
> > ---
> >  lib/librte_eal/common/arch/x86/rte_cpuflags.c  | 18 ++++++++++++++++++
> >  .../common/include/arch/x86/rte_cpuflags.h     | 18 ++++++++++++++++++
> >  2 files changed, 36 insertions(+)
> >
> > diff --git a/lib/librte_eal/common/arch/x86/rte_cpuflags.c
> b/lib/librte_eal/common/arch/x86/rte_cpuflags.c
> > index 6492df556..30439e795 100644
> > --- a/lib/librte_eal/common/arch/x86/rte_cpuflags.c
> > +++ b/lib/librte_eal/common/arch/x86/rte_cpuflags.c
> > @@ -120,6 +120,24 @@ const struct feature_entry rte_cpu_feature_table[] = {
> >         FEAT_DEF(EM64T, 0x80000001, 0, RTE_REG_EDX, 29)
> >
> >         FEAT_DEF(INVTSC, 0x80000007, 0, RTE_REG_EDX,  8)
> > +
> > +       FEAT_DEF(AVX512DQ, 0x00000007, 0, RTE_REG_EBX, 17)
> > +       FEAT_DEF(AVX512IFMA, 0x00000007, 0, RTE_REG_EBX, 21)
> > +       FEAT_DEF(AVX512CD, 0x00000007, 0, RTE_REG_EBX, 28)
> > +       FEAT_DEF(AVX512BW, 0x00000007, 0, RTE_REG_EBX, 30)
> > +       FEAT_DEF(AVX512VL, 0x00000007, 0, RTE_REG_EBX, 31)
> > +       FEAT_DEF(AVX512VBMI, 0x00000007, 0, RTE_REG_ECX, 1)
> > +       FEAT_DEF(AVX512VBMI2, 0x00000007, 0, RTE_REG_ECX, 6)
> > +       FEAT_DEF(GFNI, 0x00000007, 0, RTE_REG_ECX, 8)
> > +       FEAT_DEF(VAES, 0x00000007, 0, RTE_REG_ECX, 9)
> > +       FEAT_DEF(VPCLMULQDQ, 0x00000007, 0, RTE_REG_ECX, 10)
> > +       FEAT_DEF(AVX512VNNI, 0x00000007, 0, RTE_REG_ECX, 11)
> > +       FEAT_DEF(AVX512BITALG, 0x00000007, 0, RTE_REG_ECX, 12)
> > +       FEAT_DEF(AVX512VPOPCNTDQ, 0x00000007, 0, RTE_REG_ECX,  14)
> > +       FEAT_DEF(CLDEMOTE, 0x00000007, 0, RTE_REG_ECX, 25)
> > +       FEAT_DEF(MOVDIRI, 0x00000007, 0, RTE_REG_ECX, 27)
> > +       FEAT_DEF(MOVDIR64B, 0x00000007, 0, RTE_REG_ECX, 28)
> > +       FEAT_DEF(AVX512VP2INTERSECT, 0x00000007, 0, RTE_REG_EDX, 8)
> >  };
> >
> >  int
> > diff --git a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
> b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
> > index 25ba47b96..f8f73b19f 100644
> > --- a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
> > +++ b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
> > @@ -113,6 +113,24 @@ enum rte_cpu_flag_t {
> >         /* (EAX 80000007h) EDX features */
> >         RTE_CPUFLAG_INVTSC,                 /**< INVTSC */
> >
> > +       RTE_CPUFLAG_AVX512DQ,               /**< AVX512 Doubleword and
> Quadword */
> > +       RTE_CPUFLAG_AVX512IFMA,             /**< AVX512 Integer Fused
> Multiply-Add */
> > +       RTE_CPUFLAG_AVX512CD,               /**< AVX512 Conflict Detection*/
> > +       RTE_CPUFLAG_AVX512BW,               /**< AVX512 Byte and Word */
> > +       RTE_CPUFLAG_AVX512VL,               /**< AVX512 Vector Length */
> > +       RTE_CPUFLAG_AVX512VBMI,             /**< AVX512 Vector Bit
> Manipulation */
> > +       RTE_CPUFLAG_AVX512VBMI2,            /**< AVX512 Vector Bit
> Manipulation 2 */
> > +       RTE_CPUFLAG_GFNI,                   /**< Galois Field New
> Instructions */
> > +       RTE_CPUFLAG_VAES,                   /**< Vector AES */
> > +       RTE_CPUFLAG_VPCLMULQDQ,             /**< Vector Carry-less Multiply
> */
> > +       RTE_CPUFLAG_AVX512VNNI,             /**< AVX512 Vector Neural
> Network Instructions */
> > +       RTE_CPUFLAG_AVX512BITALG,           /**< AVX512 Bit Algorithms */
> > +       RTE_CPUFLAG_AVX512VPOPCNTDQ,        /**< AVX512 Vector Popcount */
> > +       RTE_CPUFLAG_CLDEMOTE,               /**< Cache Line Demote */
> > +       RTE_CPUFLAG_MOVDIRI,                /**< Direct Store Instructions
> */
> > +       RTE_CPUFLAG_MOVDIR64B,              /**< Direct Store Instructions
> 64B */
> > +       RTE_CPUFLAG_AVX512VP2INTERSECT,     /**< AVX512 Two Register
> Intersection */
> > +
> >         /* The last item */
> >         RTE_CPUFLAG_NUMFLAGS,               /**< This should always be the
> last! */
> 
> This is seen as an ABI break because of the change on _NUMFLAGS:
> https://travis-ci.com/github/ovsrobot/dpdk/jobs/302524264#L2351

Correct a publicly exposed enum max value has changed - I don't believe this is an ABI break, but a backward compatible ABI change was expected with this patchset.

Code compiled against eg 19.11 or 20.02 is expected to continue operating correctly.
The new flags were only added at the end of the enum, ensuring to not change the meaning of any existing flags which would be compiled-in constants to the application binary.

The actual size of the CPU flags array is a DPDK internal structure (in a .c file), and is hidden from the application, and never allocated by an application - so no possible mismatch in ABI there? Applications compiled against the older ABI will just not know about the newer flags - but suffer no breakage.

@ABI compatibility folks, please review too - but to the best of my understanding this is not an ABI break, but a backwards compatible update of CPU flag lists?

Thanks for flagging the CI results David!

Regards, -Harry

Re: [dpdk-dev] [PATCH v2] eal/cpuflags: add x86 based cpu flags

[David Marchand]

On Fri, Mar 27, 2020 at 2:18 PM Van Haaren, Harry
<harry.van.haaren@intel.com> wrote:
>
> > -----Original Message-----
> > From: David Marchand <david.marchand@redhat.com>
> > Sent: Friday, March 27, 2020 12:24 PM
> > To: Laatz, Kevin <kevin.laatz@intel.com>
> > Cc: dev <dev@dpdk.org>; Richardson, Bruce <bruce.richardson@intel.com>; Van
> > Haaren, Harry <harry.van.haaren@intel.com>; Neil Horman
> > <nhorman@tuxdriver.com>; Thomas Monjalon <thomas@monjalon.net>; Honnappa
> > Nagarahalli <Honnappa.Nagarahalli@arm.com>; Dodji Seketeli <dodji@redhat.com>
> > Subject: Re: [dpdk-dev] [PATCH v2] eal/cpuflags: add x86 based cpu flags
> >
> > On Wed, Mar 25, 2020 at 12:11 PM Kevin Laatz <kevin.laatz@intel.com> wrote:
> > >
> > > This patch adds CPU flags which will enable the detection of ISA
> > > features available on more recent x86 based CPUs.
> > >
> > > The CPUID leaf information can be found in Section 1.7 of this
> > > document:
> > > https://software.intel.com/sites/default/files/managed/c5/15/architecture-
> > instruction-set-extensions-programming-reference.pdf
> > >
> > > The following CPU flags are added in this patch:
> > >     - AVX-512 doubleword and quadword instructions.
> > >     - AVX-512 integer fused multiply-add instructions.
> > >     - AVX-512 conflict detection instructions.
> > >     - AVX-512 byte and word instructions.
> > >     - AVX-512 vector length instructions.
> > >     - AVX-512 vector bit manipulation instructions.
> > >     - AVX-512 vector bit manipulation 2 instructions.
> > >     - Galois field new instructions.
> > >     - Vector AES instructions.
> > >     - Vector carry-less multiply instructions.
> > >     - AVX-512 vector neural network instructions.
> > >     - AVX-512 for bit algorithm instructions.
> > >     - AVX-512 vector popcount instructions.
> > >     - Cache line demote instructions.
> > >     - Direct store instructions.
> > >     - Direct store 64B instructions.
> > >     - AVX-512 two register intersection instructions.
> > >
> > > Signed-off-by: Kevin Laatz <kevin.laatz@intel.com>
> > > ---
> > >  lib/librte_eal/common/arch/x86/rte_cpuflags.c  | 18 ++++++++++++++++++
> > >  .../common/include/arch/x86/rte_cpuflags.h     | 18 ++++++++++++++++++
> > >  2 files changed, 36 insertions(+)
> > >
> > > diff --git a/lib/librte_eal/common/arch/x86/rte_cpuflags.c
> > b/lib/librte_eal/common/arch/x86/rte_cpuflags.c
> > > index 6492df556..30439e795 100644
> > > --- a/lib/librte_eal/common/arch/x86/rte_cpuflags.c
> > > +++ b/lib/librte_eal/common/arch/x86/rte_cpuflags.c
> > > @@ -120,6 +120,24 @@ const struct feature_entry rte_cpu_feature_table[] = {
> > >         FEAT_DEF(EM64T, 0x80000001, 0, RTE_REG_EDX, 29)
> > >
> > >         FEAT_DEF(INVTSC, 0x80000007, 0, RTE_REG_EDX,  8)
> > > +
> > > +       FEAT_DEF(AVX512DQ, 0x00000007, 0, RTE_REG_EBX, 17)
> > > +       FEAT_DEF(AVX512IFMA, 0x00000007, 0, RTE_REG_EBX, 21)
> > > +       FEAT_DEF(AVX512CD, 0x00000007, 0, RTE_REG_EBX, 28)
> > > +       FEAT_DEF(AVX512BW, 0x00000007, 0, RTE_REG_EBX, 30)
> > > +       FEAT_DEF(AVX512VL, 0x00000007, 0, RTE_REG_EBX, 31)
> > > +       FEAT_DEF(AVX512VBMI, 0x00000007, 0, RTE_REG_ECX, 1)
> > > +       FEAT_DEF(AVX512VBMI2, 0x00000007, 0, RTE_REG_ECX, 6)
> > > +       FEAT_DEF(GFNI, 0x00000007, 0, RTE_REG_ECX, 8)
> > > +       FEAT_DEF(VAES, 0x00000007, 0, RTE_REG_ECX, 9)
> > > +       FEAT_DEF(VPCLMULQDQ, 0x00000007, 0, RTE_REG_ECX, 10)
> > > +       FEAT_DEF(AVX512VNNI, 0x00000007, 0, RTE_REG_ECX, 11)
> > > +       FEAT_DEF(AVX512BITALG, 0x00000007, 0, RTE_REG_ECX, 12)
> > > +       FEAT_DEF(AVX512VPOPCNTDQ, 0x00000007, 0, RTE_REG_ECX,  14)
> > > +       FEAT_DEF(CLDEMOTE, 0x00000007, 0, RTE_REG_ECX, 25)
> > > +       FEAT_DEF(MOVDIRI, 0x00000007, 0, RTE_REG_ECX, 27)
> > > +       FEAT_DEF(MOVDIR64B, 0x00000007, 0, RTE_REG_ECX, 28)
> > > +       FEAT_DEF(AVX512VP2INTERSECT, 0x00000007, 0, RTE_REG_EDX, 8)
> > >  };
> > >
> > >  int
> > > diff --git a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
> > b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
> > > index 25ba47b96..f8f73b19f 100644
> > > --- a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
> > > +++ b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
> > > @@ -113,6 +113,24 @@ enum rte_cpu_flag_t {
> > >         /* (EAX 80000007h) EDX features */
> > >         RTE_CPUFLAG_INVTSC,                 /**< INVTSC */
> > >
> > > +       RTE_CPUFLAG_AVX512DQ,               /**< AVX512 Doubleword and
> > Quadword */
> > > +       RTE_CPUFLAG_AVX512IFMA,             /**< AVX512 Integer Fused
> > Multiply-Add */
> > > +       RTE_CPUFLAG_AVX512CD,               /**< AVX512 Conflict Detection*/
> > > +       RTE_CPUFLAG_AVX512BW,               /**< AVX512 Byte and Word */
> > > +       RTE_CPUFLAG_AVX512VL,               /**< AVX512 Vector Length */
> > > +       RTE_CPUFLAG_AVX512VBMI,             /**< AVX512 Vector Bit
> > Manipulation */
> > > +       RTE_CPUFLAG_AVX512VBMI2,            /**< AVX512 Vector Bit
> > Manipulation 2 */
> > > +       RTE_CPUFLAG_GFNI,                   /**< Galois Field New
> > Instructions */
> > > +       RTE_CPUFLAG_VAES,                   /**< Vector AES */
> > > +       RTE_CPUFLAG_VPCLMULQDQ,             /**< Vector Carry-less Multiply
> > */
> > > +       RTE_CPUFLAG_AVX512VNNI,             /**< AVX512 Vector Neural
> > Network Instructions */
> > > +       RTE_CPUFLAG_AVX512BITALG,           /**< AVX512 Bit Algorithms */
> > > +       RTE_CPUFLAG_AVX512VPOPCNTDQ,        /**< AVX512 Vector Popcount */
> > > +       RTE_CPUFLAG_CLDEMOTE,               /**< Cache Line Demote */
> > > +       RTE_CPUFLAG_MOVDIRI,                /**< Direct Store Instructions
> > */
> > > +       RTE_CPUFLAG_MOVDIR64B,              /**< Direct Store Instructions
> > 64B */
> > > +       RTE_CPUFLAG_AVX512VP2INTERSECT,     /**< AVX512 Two Register
> > Intersection */
> > > +
> > >         /* The last item */
> > >         RTE_CPUFLAG_NUMFLAGS,               /**< This should always be the
> > last! */
> >
> > This is seen as an ABI break because of the change on _NUMFLAGS:
> > https://travis-ci.com/github/ovsrobot/dpdk/jobs/302524264#L2351
>
> Correct a publicly exposed enum max value has changed - I don't believe this is an ABI break, but a backward compatible ABI change was expected with this patchset.

A change is that if an application was passing incorrect values to the
functions taking this enum as input, then now it would succeed.
I don't really see the point in doing this :-).

>
> Code compiled against eg 19.11 or 20.02 is expected to continue operating correctly.
> The new flags were only added at the end of the enum, ensuring to not change the meaning of any existing flags which would be compiled-in constants to the application binary.
>
> The actual size of the CPU flags array is a DPDK internal structure (in a .c file), and is hidden from the application, and never allocated by an application - so no possible mismatch in ABI there? Applications compiled against the older ABI will just not know about the newer flags - but suffer no breakage.
>
> @ABI compatibility folks, please review too - but to the best of my understanding this is not an ABI break, but a backwards compatible update of CPU flag lists?
>
> Thanks for flagging the CI results David!

I'd like people to look at this by themselves, not wait for Thomas,
Aaron or me to check.

When a failure is caught by the robot, a mail is sent to the submitter
afaiu (I suppose with Travis instability wrt ARM jobs, the mail might
not have been sent this time).
It is then the responsibility of the submitter to either discuss the
report on the mailing or/and waive it in devtools/libabigail.abignore.

Thanks.


-- 
David Marchand

Re: [dpdk-dev] [PATCH v2] eal/cpuflags: add x86 based cpu flags

[Neil Horman]

On Fri, Mar 27, 2020 at 01:24:12PM +0100, David Marchand wrote:
> On Wed, Mar 25, 2020 at 12:11 PM Kevin Laatz <kevin.laatz@intel.com> wrote:
> >
> > This patch adds CPU flags which will enable the detection of ISA
> > features available on more recent x86 based CPUs.
> >
> > The CPUID leaf information can be found in Section 1.7 of this
> > document:
> > https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
> >
> > The following CPU flags are added in this patch:
> >     - AVX-512 doubleword and quadword instructions.
> >     - AVX-512 integer fused multiply-add instructions.
> >     - AVX-512 conflict detection instructions.
> >     - AVX-512 byte and word instructions.
> >     - AVX-512 vector length instructions.
> >     - AVX-512 vector bit manipulation instructions.
> >     - AVX-512 vector bit manipulation 2 instructions.
> >     - Galois field new instructions.
> >     - Vector AES instructions.
> >     - Vector carry-less multiply instructions.
> >     - AVX-512 vector neural network instructions.
> >     - AVX-512 for bit algorithm instructions.
> >     - AVX-512 vector popcount instructions.
> >     - Cache line demote instructions.
> >     - Direct store instructions.
> >     - Direct store 64B instructions.
> >     - AVX-512 two register intersection instructions.
> >
> > Signed-off-by: Kevin Laatz <kevin.laatz@intel.com>
> > ---
> >  lib/librte_eal/common/arch/x86/rte_cpuflags.c  | 18 ++++++++++++++++++
> >  .../common/include/arch/x86/rte_cpuflags.h     | 18 ++++++++++++++++++
> >  2 files changed, 36 insertions(+)
> >
> > diff --git a/lib/librte_eal/common/arch/x86/rte_cpuflags.c b/lib/librte_eal/common/arch/x86/rte_cpuflags.c
> > index 6492df556..30439e795 100644
> > --- a/lib/librte_eal/common/arch/x86/rte_cpuflags.c
> > +++ b/lib/librte_eal/common/arch/x86/rte_cpuflags.c
> > @@ -120,6 +120,24 @@ const struct feature_entry rte_cpu_feature_table[] = {
> >         FEAT_DEF(EM64T, 0x80000001, 0, RTE_REG_EDX, 29)
> >
> >         FEAT_DEF(INVTSC, 0x80000007, 0, RTE_REG_EDX,  8)
> > +
> > +       FEAT_DEF(AVX512DQ, 0x00000007, 0, RTE_REG_EBX, 17)
> > +       FEAT_DEF(AVX512IFMA, 0x00000007, 0, RTE_REG_EBX, 21)
> > +       FEAT_DEF(AVX512CD, 0x00000007, 0, RTE_REG_EBX, 28)
> > +       FEAT_DEF(AVX512BW, 0x00000007, 0, RTE_REG_EBX, 30)
> > +       FEAT_DEF(AVX512VL, 0x00000007, 0, RTE_REG_EBX, 31)
> > +       FEAT_DEF(AVX512VBMI, 0x00000007, 0, RTE_REG_ECX, 1)
> > +       FEAT_DEF(AVX512VBMI2, 0x00000007, 0, RTE_REG_ECX, 6)
> > +       FEAT_DEF(GFNI, 0x00000007, 0, RTE_REG_ECX, 8)
> > +       FEAT_DEF(VAES, 0x00000007, 0, RTE_REG_ECX, 9)
> > +       FEAT_DEF(VPCLMULQDQ, 0x00000007, 0, RTE_REG_ECX, 10)
> > +       FEAT_DEF(AVX512VNNI, 0x00000007, 0, RTE_REG_ECX, 11)
> > +       FEAT_DEF(AVX512BITALG, 0x00000007, 0, RTE_REG_ECX, 12)
> > +       FEAT_DEF(AVX512VPOPCNTDQ, 0x00000007, 0, RTE_REG_ECX,  14)
> > +       FEAT_DEF(CLDEMOTE, 0x00000007, 0, RTE_REG_ECX, 25)
> > +       FEAT_DEF(MOVDIRI, 0x00000007, 0, RTE_REG_ECX, 27)
> > +       FEAT_DEF(MOVDIR64B, 0x00000007, 0, RTE_REG_ECX, 28)
> > +       FEAT_DEF(AVX512VP2INTERSECT, 0x00000007, 0, RTE_REG_EDX, 8)
> >  };
> >
> >  int
> > diff --git a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
> > index 25ba47b96..f8f73b19f 100644
> > --- a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
> > +++ b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
> > @@ -113,6 +113,24 @@ enum rte_cpu_flag_t {
> >         /* (EAX 80000007h) EDX features */
> >         RTE_CPUFLAG_INVTSC,                 /**< INVTSC */
> >
> > +       RTE_CPUFLAG_AVX512DQ,               /**< AVX512 Doubleword and Quadword */
> > +       RTE_CPUFLAG_AVX512IFMA,             /**< AVX512 Integer Fused Multiply-Add */
> > +       RTE_CPUFLAG_AVX512CD,               /**< AVX512 Conflict Detection*/
> > +       RTE_CPUFLAG_AVX512BW,               /**< AVX512 Byte and Word */
> > +       RTE_CPUFLAG_AVX512VL,               /**< AVX512 Vector Length */
> > +       RTE_CPUFLAG_AVX512VBMI,             /**< AVX512 Vector Bit Manipulation */
> > +       RTE_CPUFLAG_AVX512VBMI2,            /**< AVX512 Vector Bit Manipulation 2 */
> > +       RTE_CPUFLAG_GFNI,                   /**< Galois Field New Instructions */
> > +       RTE_CPUFLAG_VAES,                   /**< Vector AES */
> > +       RTE_CPUFLAG_VPCLMULQDQ,             /**< Vector Carry-less Multiply */
> > +       RTE_CPUFLAG_AVX512VNNI,             /**< AVX512 Vector Neural Network Instructions */
> > +       RTE_CPUFLAG_AVX512BITALG,           /**< AVX512 Bit Algorithms */
> > +       RTE_CPUFLAG_AVX512VPOPCNTDQ,        /**< AVX512 Vector Popcount */
> > +       RTE_CPUFLAG_CLDEMOTE,               /**< Cache Line Demote */
> > +       RTE_CPUFLAG_MOVDIRI,                /**< Direct Store Instructions */
> > +       RTE_CPUFLAG_MOVDIR64B,              /**< Direct Store Instructions 64B */
> > +       RTE_CPUFLAG_AVX512VP2INTERSECT,     /**< AVX512 Two Register Intersection */
> > +
> >         /* The last item */
> >         RTE_CPUFLAG_NUMFLAGS,               /**< This should always be the last! */
> 
> This is seen as an ABI break because of the change on _NUMFLAGS:
> https://travis-ci.com/github/ovsrobot/dpdk/jobs/302524264#L2351
> 
It shouldn't be, as the only API calls we expose that use rte_cpu_flag_t accept
it as an integer parameter to see if the flag is enabled.  Theres no use of the
enum in a public array or any struct that is sized based on the number of flags,
so you should be good to go
Neil

> 
> -- 
> David Marchand
> 
> 

Re: [dpdk-dev] [PATCH v2] eal/cpuflags: add x86 based cpu flags

[Thomas Monjalon]

27/03/2020 14:44, Neil Horman:
> On Fri, Mar 27, 2020 at 01:24:12PM +0100, David Marchand wrote:
> > On Wed, Mar 25, 2020 at 12:11 PM Kevin Laatz <kevin.laatz@intel.com> wrote:
> > > --- a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
> > > +++ b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
> > > @@ -113,6 +113,24 @@ enum rte_cpu_flag_t {
> > >         /* (EAX 80000007h) EDX features */
> > >         RTE_CPUFLAG_INVTSC,                 /**< INVTSC */
> > >
> > > +       RTE_CPUFLAG_AVX512DQ,               /**< AVX512 Doubleword and Quadword */
> > > +       RTE_CPUFLAG_AVX512IFMA,             /**< AVX512 Integer Fused Multiply-Add */
> > > +       RTE_CPUFLAG_AVX512CD,               /**< AVX512 Conflict Detection*/
> > > +       RTE_CPUFLAG_AVX512BW,               /**< AVX512 Byte and Word */
> > > +       RTE_CPUFLAG_AVX512VL,               /**< AVX512 Vector Length */
> > > +       RTE_CPUFLAG_AVX512VBMI,             /**< AVX512 Vector Bit Manipulation */
> > > +       RTE_CPUFLAG_AVX512VBMI2,            /**< AVX512 Vector Bit Manipulation 2 */
> > > +       RTE_CPUFLAG_GFNI,                   /**< Galois Field New Instructions */
> > > +       RTE_CPUFLAG_VAES,                   /**< Vector AES */
> > > +       RTE_CPUFLAG_VPCLMULQDQ,             /**< Vector Carry-less Multiply */
> > > +       RTE_CPUFLAG_AVX512VNNI,             /**< AVX512 Vector Neural Network Instructions */
> > > +       RTE_CPUFLAG_AVX512BITALG,           /**< AVX512 Bit Algorithms */
> > > +       RTE_CPUFLAG_AVX512VPOPCNTDQ,        /**< AVX512 Vector Popcount */
> > > +       RTE_CPUFLAG_CLDEMOTE,               /**< Cache Line Demote */
> > > +       RTE_CPUFLAG_MOVDIRI,                /**< Direct Store Instructions */
> > > +       RTE_CPUFLAG_MOVDIR64B,              /**< Direct Store Instructions 64B */
> > > +       RTE_CPUFLAG_AVX512VP2INTERSECT,     /**< AVX512 Two Register Intersection */
> > > +
> > >         /* The last item */
> > >         RTE_CPUFLAG_NUMFLAGS,               /**< This should always be the last! */
> > 
> > This is seen as an ABI break because of the change on _NUMFLAGS:
> > https://travis-ci.com/github/ovsrobot/dpdk/jobs/302524264#L2351
> > 
> It shouldn't be, as the only API calls we expose that use rte_cpu_flag_t accept
> it as an integer parameter to see if the flag is enabled.  Theres no use of the
> enum in a public array or any struct that is sized based on the number of flags,
> so you should be good to go

Indeed I cannot imagine an ABI incompatibility in this case.
The only behaviour change is to accept new (higher) RTE_CPUFLAG values
in functions rte_cpu_get_flag_enabled() and rte_cpu_get_flag_name().
Is changing the range of valid values an ABI break?
Why is it flagged by libabigail?

Re: [dpdk-dev] [PATCH v2] eal/cpuflags: add x86 based cpu flags

[Van Haaren, Harry]

> -----Original Message-----
> From: Thomas Monjalon <thomas@monjalon.net>
> Sent: Friday, March 27, 2020 2:16 PM
> To: Neil Horman <nhorman@tuxdriver.com>; Dodji Seketeli <dodji@redhat.com>;
> mdr@ashroe.eu
> Cc: David Marchand <david.marchand@redhat.com>; Laatz, Kevin
> <kevin.laatz@intel.com>; dev <dev@dpdk.org>; Richardson, Bruce
> <bruce.richardson@intel.com>; Van Haaren, Harry <harry.van.haaren@intel.com>;
> Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>
> Subject: Re: [dpdk-dev] [PATCH v2] eal/cpuflags: add x86 based cpu flags
> 
> 27/03/2020 14:44, Neil Horman:
> > On Fri, Mar 27, 2020 at 01:24:12PM +0100, David Marchand wrote:
> > > On Wed, Mar 25, 2020 at 12:11 PM Kevin Laatz <kevin.laatz@intel.com>
> wrote:
> > > > --- a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
> > > > +++ b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
> > > > @@ -113,6 +113,24 @@ enum rte_cpu_flag_t {
> > > >         /* (EAX 80000007h) EDX features */
> > > >         RTE_CPUFLAG_INVTSC,                 /**< INVTSC */
> > > >
> > > > +       RTE_CPUFLAG_AVX512DQ,               /**< AVX512 Doubleword and
> Quadword */
> > > > +       RTE_CPUFLAG_AVX512IFMA,             /**< AVX512 Integer Fused
> Multiply-Add */
> > > > +       RTE_CPUFLAG_AVX512CD,               /**< AVX512 Conflict
> Detection*/
> > > > +       RTE_CPUFLAG_AVX512BW,               /**< AVX512 Byte and Word */
> > > > +       RTE_CPUFLAG_AVX512VL,               /**< AVX512 Vector Length */
> > > > +       RTE_CPUFLAG_AVX512VBMI,             /**< AVX512 Vector Bit
> Manipulation */
> > > > +       RTE_CPUFLAG_AVX512VBMI2,            /**< AVX512 Vector Bit
> Manipulation 2 */
> > > > +       RTE_CPUFLAG_GFNI,                   /**< Galois Field New
> Instructions */
> > > > +       RTE_CPUFLAG_VAES,                   /**< Vector AES */
> > > > +       RTE_CPUFLAG_VPCLMULQDQ,             /**< Vector Carry-less
> Multiply */
> > > > +       RTE_CPUFLAG_AVX512VNNI,             /**< AVX512 Vector Neural
> Network Instructions */
> > > > +       RTE_CPUFLAG_AVX512BITALG,           /**< AVX512 Bit Algorithms
> */
> > > > +       RTE_CPUFLAG_AVX512VPOPCNTDQ,        /**< AVX512 Vector Popcount
> */
> > > > +       RTE_CPUFLAG_CLDEMOTE,               /**< Cache Line Demote */
> > > > +       RTE_CPUFLAG_MOVDIRI,                /**< Direct Store
> Instructions */
> > > > +       RTE_CPUFLAG_MOVDIR64B,              /**< Direct Store
> Instructions 64B */
> > > > +       RTE_CPUFLAG_AVX512VP2INTERSECT,     /**< AVX512 Two Register
> Intersection */
> > > > +
> > > >         /* The last item */
> > > >         RTE_CPUFLAG_NUMFLAGS,               /**< This should always be
> the last! */
> > >
> > > This is seen as an ABI break because of the change on _NUMFLAGS:
> > > https://travis-ci.com/github/ovsrobot/dpdk/jobs/302524264#L2351
> > >
> > It shouldn't be, as the only API calls we expose that use rte_cpu_flag_t
> accept
> > it as an integer parameter to see if the flag is enabled.  Theres no use of
> the
> > enum in a public array or any struct that is sized based on the number of
> flags,
> > so you should be good to go
> 
> Indeed I cannot imagine an ABI incompatibility in this case.
> The only behaviour change is to accept new (higher) RTE_CPUFLAG values
> in functions rte_cpu_get_flag_enabled() and rte_cpu_get_flag_name().
> Is changing the range of valid values an ABI break?
> Why is it flagged by libabigail?

If this enum _MAX value was used by the application to allocate an array, that later our DPDK code would write to it could cause out-of-bounds array accesses of the application supplied array. Abigail doesn't know what applications could use the value for, so it flags it.

IMO Abigail is right to flag it to us - a manual review to understand what that _MAX enum value is used for, and then decide on a case by case basis seems the best way forward to me.

Thanks Neil/Thomas for reviewing, as reply in this thread, I also believe this is not going to break ABI.

Re: [dpdk-dev] [PATCH v2] eal/cpuflags: add x86 based cpu flags

[Ray Kinsella]

On 27/03/2020 14:32, Van Haaren, Harry wrote:
>> -----Original Message-----
>> From: Thomas Monjalon <thomas@monjalon.net>
>> Sent: Friday, March 27, 2020 2:16 PM
>> To: Neil Horman <nhorman@tuxdriver.com>; Dodji Seketeli <dodji@redhat.com>;
>> mdr@ashroe.eu
>> Cc: David Marchand <david.marchand@redhat.com>; Laatz, Kevin
>> <kevin.laatz@intel.com>; dev <dev@dpdk.org>; Richardson, Bruce
>> <bruce.richardson@intel.com>; Van Haaren, Harry <harry.van.haaren@intel.com>;
>> Honnappa Nagarahalli <Honnappa.Nagarahalli@arm.com>
>> Subject: Re: [dpdk-dev] [PATCH v2] eal/cpuflags: add x86 based cpu flags
>>
>> 27/03/2020 14:44, Neil Horman:
>>> On Fri, Mar 27, 2020 at 01:24:12PM +0100, David Marchand wrote:
>>>> On Wed, Mar 25, 2020 at 12:11 PM Kevin Laatz <kevin.laatz@intel.com>
>> wrote:
>>>>> --- a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
>>>>> +++ b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
>>>>> @@ -113,6 +113,24 @@ enum rte_cpu_flag_t {
>>>>>         /* (EAX 80000007h) EDX features */
>>>>>         RTE_CPUFLAG_INVTSC,                 /**< INVTSC */
>>>>>
>>>>> +       RTE_CPUFLAG_AVX512DQ,               /**< AVX512 Doubleword and
>> Quadword */
>>>>> +       RTE_CPUFLAG_AVX512IFMA,             /**< AVX512 Integer Fused
>> Multiply-Add */
>>>>> +       RTE_CPUFLAG_AVX512CD,               /**< AVX512 Conflict
>> Detection*/
>>>>> +       RTE_CPUFLAG_AVX512BW,               /**< AVX512 Byte and Word */
>>>>> +       RTE_CPUFLAG_AVX512VL,               /**< AVX512 Vector Length */
>>>>> +       RTE_CPUFLAG_AVX512VBMI,             /**< AVX512 Vector Bit
>> Manipulation */
>>>>> +       RTE_CPUFLAG_AVX512VBMI2,            /**< AVX512 Vector Bit
>> Manipulation 2 */
>>>>> +       RTE_CPUFLAG_GFNI,                   /**< Galois Field New
>> Instructions */
>>>>> +       RTE_CPUFLAG_VAES,                   /**< Vector AES */
>>>>> +       RTE_CPUFLAG_VPCLMULQDQ,             /**< Vector Carry-less
>> Multiply */
>>>>> +       RTE_CPUFLAG_AVX512VNNI,             /**< AVX512 Vector Neural
>> Network Instructions */
>>>>> +       RTE_CPUFLAG_AVX512BITALG,           /**< AVX512 Bit Algorithms
>> */
>>>>> +       RTE_CPUFLAG_AVX512VPOPCNTDQ,        /**< AVX512 Vector Popcount
>> */
>>>>> +       RTE_CPUFLAG_CLDEMOTE,               /**< Cache Line Demote */
>>>>> +       RTE_CPUFLAG_MOVDIRI,                /**< Direct Store
>> Instructions */
>>>>> +       RTE_CPUFLAG_MOVDIR64B,              /**< Direct Store
>> Instructions 64B */
>>>>> +       RTE_CPUFLAG_AVX512VP2INTERSECT,     /**< AVX512 Two Register
>> Intersection */
>>>>> +
>>>>>         /* The last item */
>>>>>         RTE_CPUFLAG_NUMFLAGS,               /**< This should always be
>> the last! */
>>>>
>>>> This is seen as an ABI break because of the change on _NUMFLAGS:
>>>> https://travis-ci.com/github/ovsrobot/dpdk/jobs/302524264#L2351
>>>>
>>> It shouldn't be, as the only API calls we expose that use rte_cpu_flag_t
>> accept
>>> it as an integer parameter to see if the flag is enabled.  Theres no use of
>> the
>>> enum in a public array or any struct that is sized based on the number of
>> flags,
>>> so you should be good to go
>>
>> Indeed I cannot imagine an ABI incompatibility in this case.
>> The only behaviour change is to accept new (higher) RTE_CPUFLAG values
>> in functions rte_cpu_get_flag_enabled() and rte_cpu_get_flag_name().
>> Is changing the range of valid values an ABI break?
>> Why is it flagged by libabigail?
> 
> If this enum _MAX value was used by the application to allocate an array, that later our DPDK code would write to it could cause out-of-bounds array accesses of the application supplied array. Abigail doesn't know what applications could use the value for, so it flags it.
> 
> IMO Abigail is right to flag it to us - a manual review to understand what that _MAX enum value is used for, and then decide on a case by case basis seems the best way forward to me.
> 
> Thanks Neil/Thomas for reviewing, as reply in this thread, I also believe this is not going to break ABI.
> 
 
+1 to Harrry's comments. 
I can't immediately see how this might break the ABI either. 

Re: [dpdk-dev] [PATCH v2] eal/cpuflags: add x86 based cpu flags

[Thomas Monjalon]

27/03/2020 15:36, Ray Kinsella:
> On 27/03/2020 14:32, Van Haaren, Harry wrote:
> > From: Thomas Monjalon <thomas@monjalon.net>
> >> 27/03/2020 14:44, Neil Horman:
> >>> On Fri, Mar 27, 2020 at 01:24:12PM +0100, David Marchand wrote:
> >>>> On Wed, Mar 25, 2020 at 12:11 PM Kevin Laatz <kevin.laatz@intel.com>
> >> wrote:
> >>>>> --- a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
> >>>>> +++ b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
> >>>>> @@ -113,6 +113,24 @@ enum rte_cpu_flag_t {
> >>>>>         /* (EAX 80000007h) EDX features */
> >>>>>         RTE_CPUFLAG_INVTSC,                 /**< INVTSC */
> >>>>>
> >>>>> +       RTE_CPUFLAG_AVX512DQ,               /**< AVX512 Doubleword and
> >> Quadword */
> >>>>> +       RTE_CPUFLAG_AVX512IFMA,             /**< AVX512 Integer Fused
> >> Multiply-Add */
> >>>>> +       RTE_CPUFLAG_AVX512CD,               /**< AVX512 Conflict
> >> Detection*/
> >>>>> +       RTE_CPUFLAG_AVX512BW,               /**< AVX512 Byte and Word */
> >>>>> +       RTE_CPUFLAG_AVX512VL,               /**< AVX512 Vector Length */
> >>>>> +       RTE_CPUFLAG_AVX512VBMI,             /**< AVX512 Vector Bit
> >> Manipulation */
> >>>>> +       RTE_CPUFLAG_AVX512VBMI2,            /**< AVX512 Vector Bit
> >> Manipulation 2 */
> >>>>> +       RTE_CPUFLAG_GFNI,                   /**< Galois Field New
> >> Instructions */
> >>>>> +       RTE_CPUFLAG_VAES,                   /**< Vector AES */
> >>>>> +       RTE_CPUFLAG_VPCLMULQDQ,             /**< Vector Carry-less
> >> Multiply */
> >>>>> +       RTE_CPUFLAG_AVX512VNNI,             /**< AVX512 Vector Neural
> >> Network Instructions */
> >>>>> +       RTE_CPUFLAG_AVX512BITALG,           /**< AVX512 Bit Algorithms
> >> */
> >>>>> +       RTE_CPUFLAG_AVX512VPOPCNTDQ,        /**< AVX512 Vector Popcount
> >> */
> >>>>> +       RTE_CPUFLAG_CLDEMOTE,               /**< Cache Line Demote */
> >>>>> +       RTE_CPUFLAG_MOVDIRI,                /**< Direct Store
> >> Instructions */
> >>>>> +       RTE_CPUFLAG_MOVDIR64B,              /**< Direct Store
> >> Instructions 64B */
> >>>>> +       RTE_CPUFLAG_AVX512VP2INTERSECT,     /**< AVX512 Two Register
> >> Intersection */
> >>>>> +
> >>>>>         /* The last item */
> >>>>>         RTE_CPUFLAG_NUMFLAGS,               /**< This should always be
> >> the last! */
> >>>>
> >>>> This is seen as an ABI break because of the change on _NUMFLAGS:
> >>>> https://travis-ci.com/github/ovsrobot/dpdk/jobs/302524264#L2351
> >>>>
> >>> It shouldn't be, as the only API calls we expose that use rte_cpu_flag_t
> >> accept
> >>> it as an integer parameter to see if the flag is enabled.  Theres no use of
> >> the
> >>> enum in a public array or any struct that is sized based on the number of
> >> flags,
> >>> so you should be good to go
> >>
> >> Indeed I cannot imagine an ABI incompatibility in this case.
> >> The only behaviour change is to accept new (higher) RTE_CPUFLAG values
> >> in functions rte_cpu_get_flag_enabled() and rte_cpu_get_flag_name().
> >> Is changing the range of valid values an ABI break?
> >> Why is it flagged by libabigail?
> > 
> > If this enum _MAX value was used by the application to allocate an array, that later our DPDK code would write to it could cause out-of-bounds array accesses of the application supplied array. Abigail doesn't know what applications could use the value for, so it flags it.
> > 
> > IMO Abigail is right to flag it to us - a manual review to understand what that _MAX enum value is used for, and then decide on a case by case basis seems the best way forward to me.
> > 
> > Thanks Neil/Thomas for reviewing, as reply in this thread, I also believe this is not going to break ABI.
> > 
>  
> +1 to Harrry's comments. 
> I can't immediately see how this might break the ABI either. 


So we all agree that increasing the range of valid rte_cpu_flag_t values
is OK for ABI compatibility.
This conclusion must be written as a libabigail exception in this patch.

[dpdk-dev] [PATCH v3] eal/cpuflags: add x86 based cpu flags

[Kevin Laatz]

This patch adds CPU flags which will enable the detection of ISA
features available on more recent x86 based CPUs.

The CPUID leaf information can be found in Section 1.7 of this
document:
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf

The following CPU flags are added in this patch:
    - AVX-512 doubleword and quadword instructions.
    - AVX-512 integer fused multiply-add instructions.
    - AVX-512 conflict detection instructions.
    - AVX-512 byte and word instructions.
    - AVX-512 vector length instructions.
    - AVX-512 vector bit manipulation instructions.
    - AVX-512 vector bit manipulation 2 instructions.
    - Galois field new instructions.
    - Vector AES instructions.
    - Vector carry-less multiply instructions.
    - AVX-512 vector neural network instructions.
    - AVX-512 for bit algorithm instructions.
    - AVX-512 vector popcount instructions.
    - Cache line demote instructions.
    - Direct store instructions.
    - Direct store 64B instructions.
    - AVX-512 two register intersection instructions.

Signed-off-by: Kevin Laatz <kevin.laatz@intel.com>

---
v2:
  - Squashed patch set into single patch.

v3:
  - Add abignore entry for 'rte_cpu_flag_t'.
---
 devtools/libabigail.abignore                   |  5 +++++
 lib/librte_eal/common/arch/x86/rte_cpuflags.c  | 18 ++++++++++++++++++
 .../common/include/arch/x86/rte_cpuflags.h     | 18 ++++++++++++++++++
 3 files changed, 41 insertions(+)

diff --git a/devtools/libabigail.abignore b/devtools/libabigail.abignore
index a59df8f13..eb252ae0e 100644
--- a/devtools/libabigail.abignore
+++ b/devtools/libabigail.abignore
@@ -11,3 +11,8 @@
         type_kind = enum
         name = rte_crypto_asym_xform_type
         changed_enumerators = RTE_CRYPTO_ASYM_XFORM_TYPE_LIST_END
+; Ignore this enum update as it should not be allocated by the application
+[suppress_type]
+	type_kind = enum
+	name = rte_cpu_flag_t
+	changed_enumerators = RTE_CPUFLAG_NUMFLAGS
diff --git a/lib/librte_eal/common/arch/x86/rte_cpuflags.c b/lib/librte_eal/common/arch/x86/rte_cpuflags.c
index 6492df556..30439e795 100644
--- a/lib/librte_eal/common/arch/x86/rte_cpuflags.c
+++ b/lib/librte_eal/common/arch/x86/rte_cpuflags.c
@@ -120,6 +120,24 @@ const struct feature_entry rte_cpu_feature_table[] = {
 	FEAT_DEF(EM64T, 0x80000001, 0, RTE_REG_EDX, 29)
 
 	FEAT_DEF(INVTSC, 0x80000007, 0, RTE_REG_EDX,  8)
+
+	FEAT_DEF(AVX512DQ, 0x00000007, 0, RTE_REG_EBX, 17)
+	FEAT_DEF(AVX512IFMA, 0x00000007, 0, RTE_REG_EBX, 21)
+	FEAT_DEF(AVX512CD, 0x00000007, 0, RTE_REG_EBX, 28)
+	FEAT_DEF(AVX512BW, 0x00000007, 0, RTE_REG_EBX, 30)
+	FEAT_DEF(AVX512VL, 0x00000007, 0, RTE_REG_EBX, 31)
+	FEAT_DEF(AVX512VBMI, 0x00000007, 0, RTE_REG_ECX, 1)
+	FEAT_DEF(AVX512VBMI2, 0x00000007, 0, RTE_REG_ECX, 6)
+	FEAT_DEF(GFNI, 0x00000007, 0, RTE_REG_ECX, 8)
+	FEAT_DEF(VAES, 0x00000007, 0, RTE_REG_ECX, 9)
+	FEAT_DEF(VPCLMULQDQ, 0x00000007, 0, RTE_REG_ECX, 10)
+	FEAT_DEF(AVX512VNNI, 0x00000007, 0, RTE_REG_ECX, 11)
+	FEAT_DEF(AVX512BITALG, 0x00000007, 0, RTE_REG_ECX, 12)
+	FEAT_DEF(AVX512VPOPCNTDQ, 0x00000007, 0, RTE_REG_ECX,  14)
+	FEAT_DEF(CLDEMOTE, 0x00000007, 0, RTE_REG_ECX, 25)
+	FEAT_DEF(MOVDIRI, 0x00000007, 0, RTE_REG_ECX, 27)
+	FEAT_DEF(MOVDIR64B, 0x00000007, 0, RTE_REG_ECX, 28)
+	FEAT_DEF(AVX512VP2INTERSECT, 0x00000007, 0, RTE_REG_EDX, 8)
 };
 
 int
diff --git a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
index 25ba47b96..f8f73b19f 100644
--- a/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
+++ b/lib/librte_eal/common/include/arch/x86/rte_cpuflags.h
@@ -113,6 +113,24 @@ enum rte_cpu_flag_t {
 	/* (EAX 80000007h) EDX features */
 	RTE_CPUFLAG_INVTSC,                 /**< INVTSC */
 
+	RTE_CPUFLAG_AVX512DQ,               /**< AVX512 Doubleword and Quadword */
+	RTE_CPUFLAG_AVX512IFMA,             /**< AVX512 Integer Fused Multiply-Add */
+	RTE_CPUFLAG_AVX512CD,               /**< AVX512 Conflict Detection*/
+	RTE_CPUFLAG_AVX512BW,               /**< AVX512 Byte and Word */
+	RTE_CPUFLAG_AVX512VL,               /**< AVX512 Vector Length */
+	RTE_CPUFLAG_AVX512VBMI,             /**< AVX512 Vector Bit Manipulation */
+	RTE_CPUFLAG_AVX512VBMI2,            /**< AVX512 Vector Bit Manipulation 2 */
+	RTE_CPUFLAG_GFNI,                   /**< Galois Field New Instructions */
+	RTE_CPUFLAG_VAES,                   /**< Vector AES */
+	RTE_CPUFLAG_VPCLMULQDQ,             /**< Vector Carry-less Multiply */
+	RTE_CPUFLAG_AVX512VNNI,             /**< AVX512 Vector Neural Network Instructions */
+	RTE_CPUFLAG_AVX512BITALG,           /**< AVX512 Bit Algorithms */
+	RTE_CPUFLAG_AVX512VPOPCNTDQ,        /**< AVX512 Vector Popcount */
+	RTE_CPUFLAG_CLDEMOTE,               /**< Cache Line Demote */
+	RTE_CPUFLAG_MOVDIRI,                /**< Direct Store Instructions */
+	RTE_CPUFLAG_MOVDIR64B,              /**< Direct Store Instructions 64B */
+	RTE_CPUFLAG_AVX512VP2INTERSECT,     /**< AVX512 Two Register Intersection */
+
 	/* The last item */
 	RTE_CPUFLAG_NUMFLAGS,               /**< This should always be the last! */
 };
-- 
2.17.1

Re: [dpdk-dev] [PATCH v3] eal/cpuflags: add x86 based cpu flags

[Van Haaren, Harry]

> -----Original Message-----
> From: Laatz, Kevin <kevin.laatz@intel.com>
> Sent: Monday, March 30, 2020 1:15 PM
> To: dev@dpdk.org
> Cc: Richardson, Bruce <bruce.richardson@intel.com>; Van Haaren, Harry
> <harry.van.haaren@intel.com>; thomas@monjalon.net; Kinsella, Ray
> <ray.kinsella@intel.com>; nhorman@tuxdriver.com;
> david.marchand@redhat.com; Laatz, Kevin <kevin.laatz@intel.com>
> Subject: [PATCH v3] eal/cpuflags: add x86 based cpu flags
> 
> This patch adds CPU flags which will enable the detection of ISA
> features available on more recent x86 based CPUs.
> 
> The CPUID leaf information can be found in Section 1.7 of this
> document:
> https://software.intel.com/sites/default/files/managed/c5/15/architecture-
> instruction-set-extensions-programming-reference.pdf

Section numbering has been updated, and there doesn't seem to be a stable
link to a specific version of the doc, recommend to refer to table name instead?
Table 1-2. "Information Returned by CPUID Instruction"


> The following CPU flags are added in this patch:
>     - AVX-512 doubleword and quadword instructions.
>     - AVX-512 integer fused multiply-add instructions.
>     - AVX-512 conflict detection instructions.
>     - AVX-512 byte and word instructions.
>     - AVX-512 vector length instructions.
>     - AVX-512 vector bit manipulation instructions.
>     - AVX-512 vector bit manipulation 2 instructions.
>     - Galois field new instructions.
>     - Vector AES instructions.
>     - Vector carry-less multiply instructions.
>     - AVX-512 vector neural network instructions.
>     - AVX-512 for bit algorithm instructions.
>     - AVX-512 vector popcount instructions.
>     - Cache line demote instructions.
>     - Direct store instructions.
>     - Direct store 64B instructions.
>     - AVX-512 two register intersection instructions.
> 
> Signed-off-by: Kevin Laatz <kevin.laatz@intel.com>

Required a git am --3way due to some file movements in master, but applied
cleanly on auto-merge.

Add a VNNI documentation line wrap on new line:
RTE_CPU_FLAG_AVX512VNNI,
/**< AVX512 Vector ...  */

With the above changes/updates;
Acked-by: Harry van Haaren <harry.van.haaren@intel.com>

[dpdk-dev] [PATCH v4] eal/cpuflags: add x86 based cpu flags

[Kevin Laatz]

This patch adds CPU flags which will enable the detection of ISA
features available on more recent x86 based CPUs.

The CPUID leaf information can be found in
Table 1-2. "Information Returned by CPUID Instruction" of this document:
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf

The following CPU flags are added in this patch:
    - AVX-512 doubleword and quadword instructions.
    - AVX-512 integer fused multiply-add instructions.
    - AVX-512 conflict detection instructions.
    - AVX-512 byte and word instructions.
    - AVX-512 vector length instructions.
    - AVX-512 vector bit manipulation instructions.
    - AVX-512 vector bit manipulation 2 instructions.
    - Galois field new instructions.
    - Vector AES instructions.
    - Vector carry-less multiply instructions.
    - AVX-512 vector neural network instructions.
    - AVX-512 for bit algorithm instructions.
    - AVX-512 vector popcount instructions.
    - Cache line demote instructions.
    - Direct store instructions.
    - Direct store 64B instructions.
    - AVX-512 two register intersection instructions.

Signed-off-by: Kevin Laatz <kevin.laatz@intel.com>
Acked-by: Harry van Haaren <harry.van.haaren@intel.com>

---
v2:
  - Squashed patch set into single patch.

v3:
  - Add abignore entry for 'rte_cpu_flag_t'.

v4:
  - Updated commit message to reflect updated ISA doc linked.
  - Fixed line wrap for VNNI comment.
  - Rebased on master.
---
 devtools/libabigail.abignore              |  5 +++++
 lib/librte_eal/x86/include/rte_cpuflags.h | 19 +++++++++++++++++++
 lib/librte_eal/x86/rte_cpuflags.c         | 18 ++++++++++++++++++
 3 files changed, 42 insertions(+)

diff --git a/devtools/libabigail.abignore b/devtools/libabigail.abignore
index a59df8f13..eb252ae0e 100644
--- a/devtools/libabigail.abignore
+++ b/devtools/libabigail.abignore
@@ -11,3 +11,8 @@
         type_kind = enum
         name = rte_crypto_asym_xform_type
         changed_enumerators = RTE_CRYPTO_ASYM_XFORM_TYPE_LIST_END
+; Ignore this enum update as it should not be allocated by the application
+[suppress_type]
+	type_kind = enum
+	name = rte_cpu_flag_t
+	changed_enumerators = RTE_CPUFLAG_NUMFLAGS
diff --git a/lib/librte_eal/x86/include/rte_cpuflags.h b/lib/librte_eal/x86/include/rte_cpuflags.h
index 25ba47b96..c1d20364d 100644
--- a/lib/librte_eal/x86/include/rte_cpuflags.h
+++ b/lib/librte_eal/x86/include/rte_cpuflags.h
@@ -113,6 +113,25 @@ enum rte_cpu_flag_t {
 	/* (EAX 80000007h) EDX features */
 	RTE_CPUFLAG_INVTSC,                 /**< INVTSC */
 
+	RTE_CPUFLAG_AVX512DQ,               /**< AVX512 Doubleword and Quadword */
+	RTE_CPUFLAG_AVX512IFMA,             /**< AVX512 Integer Fused Multiply-Add */
+	RTE_CPUFLAG_AVX512CD,               /**< AVX512 Conflict Detection*/
+	RTE_CPUFLAG_AVX512BW,               /**< AVX512 Byte and Word */
+	RTE_CPUFLAG_AVX512VL,               /**< AVX512 Vector Length */
+	RTE_CPUFLAG_AVX512VBMI,             /**< AVX512 Vector Bit Manipulation */
+	RTE_CPUFLAG_AVX512VBMI2,            /**< AVX512 Vector Bit Manipulation 2 */
+	RTE_CPUFLAG_GFNI,                   /**< Galois Field New Instructions */
+	RTE_CPUFLAG_VAES,                   /**< Vector AES */
+	RTE_CPUFLAG_VPCLMULQDQ,             /**< Vector Carry-less Multiply */
+	RTE_CPUFLAG_AVX512VNNI,
+	/**< AVX512 Vector Neural Network Instructions */
+	RTE_CPUFLAG_AVX512BITALG,           /**< AVX512 Bit Algorithms */
+	RTE_CPUFLAG_AVX512VPOPCNTDQ,        /**< AVX512 Vector Popcount */
+	RTE_CPUFLAG_CLDEMOTE,               /**< Cache Line Demote */
+	RTE_CPUFLAG_MOVDIRI,                /**< Direct Store Instructions */
+	RTE_CPUFLAG_MOVDIR64B,              /**< Direct Store Instructions 64B */
+	RTE_CPUFLAG_AVX512VP2INTERSECT,     /**< AVX512 Two Register Intersection */
+
 	/* The last item */
 	RTE_CPUFLAG_NUMFLAGS,               /**< This should always be the last! */
 };
diff --git a/lib/librte_eal/x86/rte_cpuflags.c b/lib/librte_eal/x86/rte_cpuflags.c
index 6492df556..30439e795 100644
--- a/lib/librte_eal/x86/rte_cpuflags.c
+++ b/lib/librte_eal/x86/rte_cpuflags.c
@@ -120,6 +120,24 @@ const struct feature_entry rte_cpu_feature_table[] = {
 	FEAT_DEF(EM64T, 0x80000001, 0, RTE_REG_EDX, 29)
 
 	FEAT_DEF(INVTSC, 0x80000007, 0, RTE_REG_EDX,  8)
+
+	FEAT_DEF(AVX512DQ, 0x00000007, 0, RTE_REG_EBX, 17)
+	FEAT_DEF(AVX512IFMA, 0x00000007, 0, RTE_REG_EBX, 21)
+	FEAT_DEF(AVX512CD, 0x00000007, 0, RTE_REG_EBX, 28)
+	FEAT_DEF(AVX512BW, 0x00000007, 0, RTE_REG_EBX, 30)
+	FEAT_DEF(AVX512VL, 0x00000007, 0, RTE_REG_EBX, 31)
+	FEAT_DEF(AVX512VBMI, 0x00000007, 0, RTE_REG_ECX, 1)
+	FEAT_DEF(AVX512VBMI2, 0x00000007, 0, RTE_REG_ECX, 6)
+	FEAT_DEF(GFNI, 0x00000007, 0, RTE_REG_ECX, 8)
+	FEAT_DEF(VAES, 0x00000007, 0, RTE_REG_ECX, 9)
+	FEAT_DEF(VPCLMULQDQ, 0x00000007, 0, RTE_REG_ECX, 10)
+	FEAT_DEF(AVX512VNNI, 0x00000007, 0, RTE_REG_ECX, 11)
+	FEAT_DEF(AVX512BITALG, 0x00000007, 0, RTE_REG_ECX, 12)
+	FEAT_DEF(AVX512VPOPCNTDQ, 0x00000007, 0, RTE_REG_ECX,  14)
+	FEAT_DEF(CLDEMOTE, 0x00000007, 0, RTE_REG_ECX, 25)
+	FEAT_DEF(MOVDIRI, 0x00000007, 0, RTE_REG_ECX, 27)
+	FEAT_DEF(MOVDIR64B, 0x00000007, 0, RTE_REG_ECX, 28)
+	FEAT_DEF(AVX512VP2INTERSECT, 0x00000007, 0, RTE_REG_EDX, 8)
 };
 
 int
-- 
2.25.1

Re: [dpdk-dev] [PATCH v4] eal/cpuflags: add x86 based cpu flags

[Thomas Monjalon]

16/04/2020 13:00, Kevin Laatz:
> This patch adds CPU flags which will enable the detection of ISA
> features available on more recent x86 based CPUs.
[...]
> --- a/devtools/libabigail.abignore
> +++ b/devtools/libabigail.abignore
> +; Ignore this enum update as it should not be allocated by the application
> +[suppress_type]
> +	type_kind = enum
> +	name = rte_cpu_flag_t
> +	changed_enumerators = RTE_CPUFLAG_NUMFLAGS

The justification is not correct.
The application is allowed to use RTE_CPUFLAG_NUMFLAGS in array allocation.
But no API is returning a CPU flag, so the new flags will remain unknown
to the application.

However, there is a behaviour change:
The functions rte_cpu_get_flag_name() and rte_cpu_get_flag_enabled()
will now accept new values, which were previously considered as an error.
Is it an ABI breakage? I would say no.


PS: Who is REALLY maintaining the ABI?
We really miss someone who carefully check all these things,
and take care of the doc and tooling.

Re: [dpdk-dev] [PATCH v4] eal/cpuflags: add x86 based cpu flags

[Kinsella, Ray]

> -----Original Message-----
> From: Thomas Monjalon <thomas@monjalon.net>
> Sent: Saturday 25 April 2020 17:04
> To: Kinsella, Ray <ray.kinsella@intel.com>; nhorman@tuxdriver.com;
> Laatz, Kevin <kevin.laatz@intel.com>
> Cc: dev@dpdk.org; Richardson, Bruce <bruce.richardson@intel.com>; Van
> Haaren, Harry <harry.van.haaren@intel.com>; david.marchand@redhat.com
> Subject: Re: [dpdk-dev] [PATCH v4] eal/cpuflags: add x86 based cpu
> flags
> 
> 16/04/2020 13:00, Kevin Laatz:
> > This patch adds CPU flags which will enable the detection of ISA
> > features available on more recent x86 based CPUs.
> [...]
> > --- a/devtools/libabigail.abignore
> > +++ b/devtools/libabigail.abignore
> > +; Ignore this enum update as it should not be allocated by the
> > +application [suppress_type]
> > +	type_kind = enum
> > +	name = rte_cpu_flag_t
> > +	changed_enumerators = RTE_CPUFLAG_NUMFLAGS
> 
> The justification is not correct.
> The application is allowed to use RTE_CPUFLAG_NUMFLAGS in array
> allocation.
> But no API is returning a CPU flag, so the new flags will remain
> unknown to the application.
> 
> However, there is a behaviour change:
> The functions rte_cpu_get_flag_name() and rte_cpu_get_flag_enabled()
> will now accept new values, which were previously considered as an
> error.
> Is it an ABI breakage? I would say no.

We saw something similar with the Cryptodev's rte_crypto_sym_xform_type also.
Libabigail appears to be particularly sensitive to changes to enumerations. 
Leaving it to the user to decide if there is a problem. 

I am seeing a bit of weirdness though between versions of libabigail.
1.7.1 seems to fine with the change, however 1.2 is reporting an issue. 

Kevin - what version are you using?

> 
> PS: Who is REALLY maintaining the ABI?
> We really miss someone who carefully check all these things, and take
> care of the doc and tooling.

I would say that I am missing these changes to libabigail.ignore, which would be useful. 
Should we consolidate the ABI Policy and ABI Versioning sections of the MAINTAINERS file?

Re: [dpdk-dev] [PATCH v4] eal/cpuflags: add x86 based cpu flags

[Ray Kinsella]

(replying this time to the list)

On 25/04/2020 17:04, Thomas Monjalon wrote:
> 16/04/2020 13:00, Kevin Laatz:
>> This patch adds CPU flags which will enable the detection of ISA
>> features available on more recent x86 based CPUs.
> [...]
>> --- a/devtools/libabigail.abignore
>> +++ b/devtools/libabigail.abignore
>> +; Ignore this enum update as it should not be allocated by the application
>> +[suppress_type]
>> +	type_kind = enum
>> +	name = rte_cpu_flag_t
>> +	changed_enumerators = RTE_CPUFLAG_NUMFLAGS
> 
> The justification is not correct.
> The application is allowed to use RTE_CPUFLAG_NUMFLAGS in array allocation.
> But no API is returning a CPU flag, so the new flags will remain unknown
> to the application.
> 
> However, there is a behaviour change:
> The functions rte_cpu_get_flag_name() and rte_cpu_get_flag_enabled()
> will now accept new values, which were previously considered as an error.
> Is it an ABI breakage? I would say no.

We saw something similar with the Cryptodev's rte_crypto_sym_xform_type also.
Libabigail appears to be particularly sensitive to changes to enumerations. 
Leaving it to the user to decide if there is a problem. 

I am seeing a bit of weirdness though between versions of libabigail.
1.7.1 seems to fine with the change, however 1.2 is reporting an issue. 

Kevin - what version are you using?

> 
> PS: Who is REALLY maintaining the ABI?
> We really miss someone who carefully check all these things,
> and take care of the doc and tooling.
> 
> 

I would say that I am missing these changes to libabigail.ignore, which would be useful. 
Should we consolidate the ABI Policy and ABI Versioning sections of the MAINTAINERS file?

Re: [dpdk-dev] [PATCH v4] eal/cpuflags: add x86 based cpu flags

[Laatz, Kevin]

 
> (replying this time to the list)
> 
> On 25/04/2020 17:04, Thomas Monjalon wrote:
> > 16/04/2020 13:00, Kevin Laatz:
> >> This patch adds CPU flags which will enable the detection of ISA
> >> features available on more recent x86 based CPUs.
> > [...]
> >> --- a/devtools/libabigail.abignore
> >> +++ b/devtools/libabigail.abignore
> >> +; Ignore this enum update as it should not be allocated by the
> >> +application [suppress_type]
> >> +	type_kind = enum
> >> +	name = rte_cpu_flag_t
> >> +	changed_enumerators = RTE_CPUFLAG_NUMFLAGS
> >
> > The justification is not correct.
> > The application is allowed to use RTE_CPUFLAG_NUMFLAGS in array
> allocation.
> > But no API is returning a CPU flag, so the new flags will remain
> > unknown to the application.
> >
> > However, there is a behaviour change:
> > The functions rte_cpu_get_flag_name() and rte_cpu_get_flag_enabled()
> > will now accept new values, which were previously considered as an error.
> > Is it an ABI breakage? I would say no.
> 
> We saw something similar with the Cryptodev's rte_crypto_sym_xform_type
> also.
> Libabigail appears to be particularly sensitive to changes to enumerations.
> Leaving it to the user to decide if there is a problem.
> 
> I am seeing a bit of weirdness though between versions of libabigail.
> 1.7.1 seems to fine with the change, however 1.2 is reporting an issue.
> 
> Kevin - what version are you using?

I'm using version 1.6.0

> 
> >
> > PS: Who is REALLY maintaining the ABI?
> > We really miss someone who carefully check all these things, and take
> > care of the doc and tooling.
> >
> >
> 
> I would say that I am missing these changes to libabigail.ignore, which would
> be useful.
> Should we consolidate the ABI Policy and ABI Versioning sections of the
> MAINTAINERS file?

Re: [dpdk-dev] [PATCH v4] eal/cpuflags: add x86 based cpu flags

[Ray Kinsella]

On 27/04/2020 10:31, Laatz, Kevin wrote:
>  
>> (replying this time to the list)
>>
>> On 25/04/2020 17:04, Thomas Monjalon wrote:
>>> 16/04/2020 13:00, Kevin Laatz:
>>>> This patch adds CPU flags which will enable the detection of ISA
>>>> features available on more recent x86 based CPUs.
>>> [...]
>>>> --- a/devtools/libabigail.abignore
>>>> +++ b/devtools/libabigail.abignore
>>>> +; Ignore this enum update as it should not be allocated by the
>>>> +application [suppress_type]
>>>> +	type_kind = enum
>>>> +	name = rte_cpu_flag_t
>>>> +	changed_enumerators = RTE_CPUFLAG_NUMFLAGS
>>>
>>> The justification is not correct.
>>> The application is allowed to use RTE_CPUFLAG_NUMFLAGS in array
>> allocation.
>>> But no API is returning a CPU flag, so the new flags will remain
>>> unknown to the application.
>>>
>>> However, there is a behaviour change:
>>> The functions rte_cpu_get_flag_name() and rte_cpu_get_flag_enabled()
>>> will now accept new values, which were previously considered as an error.
>>> Is it an ABI breakage? I would say no.
>>
>> We saw something similar with the Cryptodev's rte_crypto_sym_xform_type
>> also.
>> Libabigail appears to be particularly sensitive to changes to enumerations.
>> Leaving it to the user to decide if there is a problem.
>>
>> I am seeing a bit of weirdness though between versions of libabigail.
>> 1.7.1 seems to fine with the change, however 1.2 is reporting an issue.
>>
>> Kevin - what version are you using?
> 
> I'm using version 1.6.0

right you are either on Fedora 31 or some Ubuntu v19.xx, right?

> 
>>
>>>
>>> PS: Who is REALLY maintaining the ABI?
>>> We really miss someone who carefully check all these things, and take
>>> care of the doc and tooling.
>>>
>>>
>>
>> I would say that I am missing these changes to libabigail.ignore, which would
>> be useful.
>> Should we consolidate the ABI Policy and ABI Versioning sections of the
>> MAINTAINERS file?
> 

Re: [dpdk-dev] [PATCH v4] eal/cpuflags: add x86 based cpu flags

[Laatz, Kevin]

> On 27/04/2020 10:31, Laatz, Kevin wrote:
> >
> >> (replying this time to the list)
> >>
> >> On 25/04/2020 17:04, Thomas Monjalon wrote:
> >>> 16/04/2020 13:00, Kevin Laatz:
> >>>> This patch adds CPU flags which will enable the detection of ISA
> >>>> features available on more recent x86 based CPUs.
> >>> [...]
> >>>> --- a/devtools/libabigail.abignore
> >>>> +++ b/devtools/libabigail.abignore
> >>>> +; Ignore this enum update as it should not be allocated by the
> >>>> +application [suppress_type]
> >>>> +	type_kind = enum
> >>>> +	name = rte_cpu_flag_t
> >>>> +	changed_enumerators = RTE_CPUFLAG_NUMFLAGS
> >>>
> >>> The justification is not correct.
> >>> The application is allowed to use RTE_CPUFLAG_NUMFLAGS in array
> >> allocation.
> >>> But no API is returning a CPU flag, so the new flags will remain
> >>> unknown to the application.
> >>>
> >>> However, there is a behaviour change:
> >>> The functions rte_cpu_get_flag_name() and
> rte_cpu_get_flag_enabled()
> >>> will now accept new values, which were previously considered as an
> error.
> >>> Is it an ABI breakage? I would say no.
> >>
> >> We saw something similar with the Cryptodev's
> >> rte_crypto_sym_xform_type also.
> >> Libabigail appears to be particularly sensitive to changes to enumerations.
> >> Leaving it to the user to decide if there is a problem.
> >>
> >> I am seeing a bit of weirdness though between versions of libabigail.
> >> 1.7.1 seems to fine with the change, however 1.2 is reporting an issue.
> >>
> >> Kevin - what version are you using?
> >
> > I'm using version 1.6.0
> 
> right you are either on Fedora 31 or some Ubuntu v19.xx, right?

At the time of making the patch: Ubuntu 18.04 with a manually upgraded libabigail
Currently Ubuntu 20.04 (beta). 

> 
> >
> >>
> >>>
> >>> PS: Who is REALLY maintaining the ABI?
> >>> We really miss someone who carefully check all these things, and
> >>> take care of the doc and tooling.
> >>>
> >>>
> >>
> >> I would say that I am missing these changes to libabigail.ignore,
> >> which would be useful.
> >> Should we consolidate the ABI Policy and ABI Versioning sections of
> >> the MAINTAINERS file?
> >

Re: [dpdk-dev] [PATCH v4] eal/cpuflags: add x86 based cpu flags

[Thomas Monjalon]

27/04/2020 11:27, Ray Kinsella:
> On 25/04/2020 17:04, Thomas Monjalon wrote:
> > PS: Who is REALLY maintaining the ABI?
> > We really miss someone who carefully check all these things,
> > and take care of the doc and tooling.
> 
> I would say that I am missing these changes to libabigail.ignore, which would be useful. 
> Should we consolidate the ABI Policy and ABI Versioning sections of the MAINTAINERS file?

Yes, I think it does not make sense spliting ABI topic in 2 sections
in MAINTAINERS file.
We need to have a clear ownership covering policy, libs, tooling and doc.
Let's agree to merge all in one section please.

Re: [dpdk-dev] [PATCH v4] eal/cpuflags: add x86 based cpu flags

[Ray Kinsella]

On 27/04/2020 13:31, Thomas Monjalon wrote:
> 27/04/2020 11:27, Ray Kinsella:
>> On 25/04/2020 17:04, Thomas Monjalon wrote:
>>> PS: Who is REALLY maintaining the ABI?
>>> We really miss someone who carefully check all these things,
>>> and take care of the doc and tooling.
>>
>> I would say that I am missing these changes to libabigail.ignore, which would be useful. 
>> Should we consolidate the ABI Policy and ABI Versioning sections of the MAINTAINERS file?
> 
> Yes, I think it does not make sense spliting ABI topic in 2 sections
> in MAINTAINERS file.
> We need to have a clear ownership covering policy, libs, tooling and doc.
> Let's agree to merge all in one section please.
> 

I would suggest merging and listing myself and Neil as maintainers?
Unless you are aware of another potential owner?

Ray K
 

Re: [dpdk-dev] [PATCH v4] eal/cpuflags: add x86 based cpu flags

[Neil Horman]

On Mon, Apr 27, 2020 at 02:58:07PM +0100, Ray Kinsella wrote:
> 
> 
> On 27/04/2020 13:31, Thomas Monjalon wrote:
> > 27/04/2020 11:27, Ray Kinsella:
> >> On 25/04/2020 17:04, Thomas Monjalon wrote:
> >>> PS: Who is REALLY maintaining the ABI?
> >>> We really miss someone who carefully check all these things,
> >>> and take care of the doc and tooling.
> >>
> >> I would say that I am missing these changes to libabigail.ignore, which would be useful. 
> >> Should we consolidate the ABI Policy and ABI Versioning sections of the MAINTAINERS file?
> > 
> > Yes, I think it does not make sense spliting ABI topic in 2 sections
> > in MAINTAINERS file.
> > We need to have a clear ownership covering policy, libs, tooling and doc.
> > Let's agree to merge all in one section please.
> > 
> 
> I would suggest merging and listing myself and Neil as maintainers?
> Unless you are aware of another potential owner?
> 
I'm ok with this
Neil

> Ray K
>  
> 

Re: [dpdk-dev] [PATCH v4] eal/cpuflags: add x86 based cpu flags

[Ray Kinsella]

On 29/04/2020 12:22, Neil Horman wrote:
> On Mon, Apr 27, 2020 at 02:58:07PM +0100, Ray Kinsella wrote:
>>
>>
>> On 27/04/2020 13:31, Thomas Monjalon wrote:
>>> 27/04/2020 11:27, Ray Kinsella:
>>>> On 25/04/2020 17:04, Thomas Monjalon wrote:
>>>>> PS: Who is REALLY maintaining the ABI?
>>>>> We really miss someone who carefully check all these things,
>>>>> and take care of the doc and tooling.
>>>>
>>>> I would say that I am missing these changes to libabigail.ignore, which would be useful. 
>>>> Should we consolidate the ABI Policy and ABI Versioning sections of the MAINTAINERS file?
>>>
>>> Yes, I think it does not make sense spliting ABI topic in 2 sections
>>> in MAINTAINERS file.
>>> We need to have a clear ownership covering policy, libs, tooling and doc.
>>> Let's agree to merge all in one section please.
>>>
>>
>> I would suggest merging and listing myself and Neil as maintainers?
>> Unless you are aware of another potential owner?
>>
> I'm ok with this
> Neil

ok I will take care of it in the next rev of the 

"[PATCH] abi: change references to abi 20.0.1 to abi v21"
 
>> Ray K
>>  
>>

[dpdk-dev] [PATCH v5] eal/cpuflags: add x86 based cpu flags

[Kevin Laatz]

This patch adds CPU flags which will enable the detection of ISA
features available on more recent x86 based CPUs.

The CPUID leaf information can be found in
Table 1-2. "Information Returned by CPUID Instruction" of this document:
https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf

The following CPU flags are added in this patch:
    - AVX-512 doubleword and quadword instructions.
    - AVX-512 integer fused multiply-add instructions.
    - AVX-512 conflict detection instructions.
    - AVX-512 byte and word instructions.
    - AVX-512 vector length instructions.
    - AVX-512 vector bit manipulation instructions.
    - AVX-512 vector bit manipulation 2 instructions.
    - Galois field new instructions.
    - Vector AES instructions.
    - Vector carry-less multiply instructions.
    - AVX-512 vector neural network instructions.
    - AVX-512 for bit algorithm instructions.
    - AVX-512 vector popcount instructions.
    - Cache line demote instructions.
    - Direct store instructions.
    - Direct store 64B instructions.
    - AVX-512 two register intersection instructions.

Signed-off-by: Kevin Laatz <kevin.laatz@intel.com>
Acked-by: Harry van Haaren <harry.van.haaren@intel.com>

---
v2:
  - Squashed patch set into single patch.

v3:
  - Add abignore entry for 'rte_cpu_flag_t'.

v4:
  - Updated commit message to reflect updated ISA doc linked.
  - Fixed line wrap for VNNI comment.
  - Rebased on master.

v5:
  - Update abignore entry justification.
---
 devtools/libabigail.abignore              |  5 +++++
 lib/librte_eal/x86/include/rte_cpuflags.h | 19 +++++++++++++++++++
 lib/librte_eal/x86/rte_cpuflags.c         | 18 ++++++++++++++++++
 3 files changed, 42 insertions(+)

diff --git a/devtools/libabigail.abignore b/devtools/libabigail.abignore
index a59df8f13..045f436fb 100644
--- a/devtools/libabigail.abignore
+++ b/devtools/libabigail.abignore
@@ -11,3 +11,8 @@
         type_kind = enum
         name = rte_crypto_asym_xform_type
         changed_enumerators = RTE_CRYPTO_ASYM_XFORM_TYPE_LIST_END
+; Ignore this enum update as new flags remain unknown to applications
+[suppress_type]
+	type_kind = enum
+	name = rte_cpu_flag_t
+	changed_enumerators = RTE_CPUFLAG_NUMFLAGS
diff --git a/lib/librte_eal/x86/include/rte_cpuflags.h b/lib/librte_eal/x86/include/rte_cpuflags.h
index 25ba47b96..c1d20364d 100644
--- a/lib/librte_eal/x86/include/rte_cpuflags.h
+++ b/lib/librte_eal/x86/include/rte_cpuflags.h
@@ -113,6 +113,25 @@ enum rte_cpu_flag_t {
 	/* (EAX 80000007h) EDX features */
 	RTE_CPUFLAG_INVTSC,                 /**< INVTSC */
 
+	RTE_CPUFLAG_AVX512DQ,               /**< AVX512 Doubleword and Quadword */
+	RTE_CPUFLAG_AVX512IFMA,             /**< AVX512 Integer Fused Multiply-Add */
+	RTE_CPUFLAG_AVX512CD,               /**< AVX512 Conflict Detection*/
+	RTE_CPUFLAG_AVX512BW,               /**< AVX512 Byte and Word */
+	RTE_CPUFLAG_AVX512VL,               /**< AVX512 Vector Length */
+	RTE_CPUFLAG_AVX512VBMI,             /**< AVX512 Vector Bit Manipulation */
+	RTE_CPUFLAG_AVX512VBMI2,            /**< AVX512 Vector Bit Manipulation 2 */
+	RTE_CPUFLAG_GFNI,                   /**< Galois Field New Instructions */
+	RTE_CPUFLAG_VAES,                   /**< Vector AES */
+	RTE_CPUFLAG_VPCLMULQDQ,             /**< Vector Carry-less Multiply */
+	RTE_CPUFLAG_AVX512VNNI,
+	/**< AVX512 Vector Neural Network Instructions */
+	RTE_CPUFLAG_AVX512BITALG,           /**< AVX512 Bit Algorithms */
+	RTE_CPUFLAG_AVX512VPOPCNTDQ,        /**< AVX512 Vector Popcount */
+	RTE_CPUFLAG_CLDEMOTE,               /**< Cache Line Demote */
+	RTE_CPUFLAG_MOVDIRI,                /**< Direct Store Instructions */
+	RTE_CPUFLAG_MOVDIR64B,              /**< Direct Store Instructions 64B */
+	RTE_CPUFLAG_AVX512VP2INTERSECT,     /**< AVX512 Two Register Intersection */
+
 	/* The last item */
 	RTE_CPUFLAG_NUMFLAGS,               /**< This should always be the last! */
 };
diff --git a/lib/librte_eal/x86/rte_cpuflags.c b/lib/librte_eal/x86/rte_cpuflags.c
index 6492df556..30439e795 100644
--- a/lib/librte_eal/x86/rte_cpuflags.c
+++ b/lib/librte_eal/x86/rte_cpuflags.c
@@ -120,6 +120,24 @@ const struct feature_entry rte_cpu_feature_table[] = {
 	FEAT_DEF(EM64T, 0x80000001, 0, RTE_REG_EDX, 29)
 
 	FEAT_DEF(INVTSC, 0x80000007, 0, RTE_REG_EDX,  8)
+
+	FEAT_DEF(AVX512DQ, 0x00000007, 0, RTE_REG_EBX, 17)
+	FEAT_DEF(AVX512IFMA, 0x00000007, 0, RTE_REG_EBX, 21)
+	FEAT_DEF(AVX512CD, 0x00000007, 0, RTE_REG_EBX, 28)
+	FEAT_DEF(AVX512BW, 0x00000007, 0, RTE_REG_EBX, 30)
+	FEAT_DEF(AVX512VL, 0x00000007, 0, RTE_REG_EBX, 31)
+	FEAT_DEF(AVX512VBMI, 0x00000007, 0, RTE_REG_ECX, 1)
+	FEAT_DEF(AVX512VBMI2, 0x00000007, 0, RTE_REG_ECX, 6)
+	FEAT_DEF(GFNI, 0x00000007, 0, RTE_REG_ECX, 8)
+	FEAT_DEF(VAES, 0x00000007, 0, RTE_REG_ECX, 9)
+	FEAT_DEF(VPCLMULQDQ, 0x00000007, 0, RTE_REG_ECX, 10)
+	FEAT_DEF(AVX512VNNI, 0x00000007, 0, RTE_REG_ECX, 11)
+	FEAT_DEF(AVX512BITALG, 0x00000007, 0, RTE_REG_ECX, 12)
+	FEAT_DEF(AVX512VPOPCNTDQ, 0x00000007, 0, RTE_REG_ECX,  14)
+	FEAT_DEF(CLDEMOTE, 0x00000007, 0, RTE_REG_ECX, 25)
+	FEAT_DEF(MOVDIRI, 0x00000007, 0, RTE_REG_ECX, 27)
+	FEAT_DEF(MOVDIR64B, 0x00000007, 0, RTE_REG_ECX, 28)
+	FEAT_DEF(AVX512VP2INTERSECT, 0x00000007, 0, RTE_REG_EDX, 8)
 };
 
 int
-- 
2.25.1

Re: [dpdk-dev] [PATCH v5] eal/cpuflags: add x86 based cpu flags

[Ray Kinsella]

On 28/04/2020 13:40, Kevin Laatz wrote:
> This patch adds CPU flags which will enable the detection of ISA
> features available on more recent x86 based CPUs.
> 
> The CPUID leaf information can be found in
> Table 1-2. "Information Returned by CPUID Instruction" of this document:
> https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
> 
> The following CPU flags are added in this patch:
>     - AVX-512 doubleword and quadword instructions.
>     - AVX-512 integer fused multiply-add instructions.
>     - AVX-512 conflict detection instructions.
>     - AVX-512 byte and word instructions.
>     - AVX-512 vector length instructions.
>     - AVX-512 vector bit manipulation instructions.
>     - AVX-512 vector bit manipulation 2 instructions.
>     - Galois field new instructions.
>     - Vector AES instructions.
>     - Vector carry-less multiply instructions.
>     - AVX-512 vector neural network instructions.
>     - AVX-512 for bit algorithm instructions.
>     - AVX-512 vector popcount instructions.
>     - Cache line demote instructions.
>     - Direct store instructions.
>     - Direct store 64B instructions.
>     - AVX-512 two register intersection instructions.
> 
> Signed-off-by: Kevin Laatz <kevin.laatz@intel.com>
> Acked-by: Harry van Haaren <harry.van.haaren@intel.com>
> 
> ---
> v2:
>   - Squashed patch set into single patch.
> 
> v3:
>   - Add abignore entry for 'rte_cpu_flag_t'.
> 
> v4:
>   - Updated commit message to reflect updated ISA doc linked.
>   - Fixed line wrap for VNNI comment.
>   - Rebased on master.
> 
> v5:
>   - Update abignore entry justification.
> ---
>  devtools/libabigail.abignore              |  5 +++++
>  lib/librte_eal/x86/include/rte_cpuflags.h | 19 +++++++++++++++++++
>  lib/librte_eal/x86/rte_cpuflags.c         | 18 ++++++++++++++++++
>  3 files changed, 42 insertions(+)
> 
> diff --git a/devtools/libabigail.abignore b/devtools/libabigail.abignore
> index a59df8f13..045f436fb 100644
> --- a/devtools/libabigail.abignore
> +++ b/devtools/libabigail.abignore

Kevin - you still have the surpession.
I am testing locally with 1.7.1, and it doesn't complain when I disable the supression.
Are you seeing something different?


> @@ -11,3 +11,8 @@
>          type_kind = enum
>          name = rte_crypto_asym_xform_type
>          changed_enumerators = RTE_CRYPTO_ASYM_XFORM_TYPE_LIST_END
> +; Ignore this enum update as new flags remain unknown to applications
> +[suppress_type]
> +	type_kind = enum
> +	name = rte_cpu_flag_t
> +	changed_enumerators = RTE_CPUFLAG_NUMFLAGS
> diff --git a/lib/librte_eal/x86/include/rte_cpuflags.h b/lib/librte_eal/x86/include/rte_cpuflags.h
> index 25ba47b96..c1d20364d 100644
> --- a/lib/librte_eal/x86/include/rte_cpuflags.h
> +++ b/lib/librte_eal/x86/include/rte_cpuflags.h
> @@ -113,6 +113,25 @@ enum rte_cpu_flag_t {
>  	/* (EAX 80000007h) EDX features */
>  	RTE_CPUFLAG_INVTSC,                 /**< INVTSC */
>  
> +	RTE_CPUFLAG_AVX512DQ,               /**< AVX512 Doubleword and Quadword */
> +	RTE_CPUFLAG_AVX512IFMA,             /**< AVX512 Integer Fused Multiply-Add */
> +	RTE_CPUFLAG_AVX512CD,               /**< AVX512 Conflict Detection*/
> +	RTE_CPUFLAG_AVX512BW,               /**< AVX512 Byte and Word */
> +	RTE_CPUFLAG_AVX512VL,               /**< AVX512 Vector Length */
> +	RTE_CPUFLAG_AVX512VBMI,             /**< AVX512 Vector Bit Manipulation */
> +	RTE_CPUFLAG_AVX512VBMI2,            /**< AVX512 Vector Bit Manipulation 2 */
> +	RTE_CPUFLAG_GFNI,                   /**< Galois Field New Instructions */
> +	RTE_CPUFLAG_VAES,                   /**< Vector AES */
> +	RTE_CPUFLAG_VPCLMULQDQ,             /**< Vector Carry-less Multiply */
> +	RTE_CPUFLAG_AVX512VNNI,
> +	/**< AVX512 Vector Neural Network Instructions */
> +	RTE_CPUFLAG_AVX512BITALG,           /**< AVX512 Bit Algorithms */
> +	RTE_CPUFLAG_AVX512VPOPCNTDQ,        /**< AVX512 Vector Popcount */
> +	RTE_CPUFLAG_CLDEMOTE,               /**< Cache Line Demote */
> +	RTE_CPUFLAG_MOVDIRI,                /**< Direct Store Instructions */
> +	RTE_CPUFLAG_MOVDIR64B,              /**< Direct Store Instructions 64B */
> +	RTE_CPUFLAG_AVX512VP2INTERSECT,     /**< AVX512 Two Register Intersection */
> +
>  	/* The last item */
>  	RTE_CPUFLAG_NUMFLAGS,               /**< This should always be the last! */
>  };
> diff --git a/lib/librte_eal/x86/rte_cpuflags.c b/lib/librte_eal/x86/rte_cpuflags.c
> index 6492df556..30439e795 100644
> --- a/lib/librte_eal/x86/rte_cpuflags.c
> +++ b/lib/librte_eal/x86/rte_cpuflags.c
> @@ -120,6 +120,24 @@ const struct feature_entry rte_cpu_feature_table[] = {
>  	FEAT_DEF(EM64T, 0x80000001, 0, RTE_REG_EDX, 29)
>  
>  	FEAT_DEF(INVTSC, 0x80000007, 0, RTE_REG_EDX,  8)
> +
> +	FEAT_DEF(AVX512DQ, 0x00000007, 0, RTE_REG_EBX, 17)
> +	FEAT_DEF(AVX512IFMA, 0x00000007, 0, RTE_REG_EBX, 21)
> +	FEAT_DEF(AVX512CD, 0x00000007, 0, RTE_REG_EBX, 28)
> +	FEAT_DEF(AVX512BW, 0x00000007, 0, RTE_REG_EBX, 30)
> +	FEAT_DEF(AVX512VL, 0x00000007, 0, RTE_REG_EBX, 31)
> +	FEAT_DEF(AVX512VBMI, 0x00000007, 0, RTE_REG_ECX, 1)
> +	FEAT_DEF(AVX512VBMI2, 0x00000007, 0, RTE_REG_ECX, 6)
> +	FEAT_DEF(GFNI, 0x00000007, 0, RTE_REG_ECX, 8)
> +	FEAT_DEF(VAES, 0x00000007, 0, RTE_REG_ECX, 9)
> +	FEAT_DEF(VPCLMULQDQ, 0x00000007, 0, RTE_REG_ECX, 10)
> +	FEAT_DEF(AVX512VNNI, 0x00000007, 0, RTE_REG_ECX, 11)
> +	FEAT_DEF(AVX512BITALG, 0x00000007, 0, RTE_REG_ECX, 12)
> +	FEAT_DEF(AVX512VPOPCNTDQ, 0x00000007, 0, RTE_REG_ECX,  14)
> +	FEAT_DEF(CLDEMOTE, 0x00000007, 0, RTE_REG_ECX, 25)
> +	FEAT_DEF(MOVDIRI, 0x00000007, 0, RTE_REG_ECX, 27)
> +	FEAT_DEF(MOVDIR64B, 0x00000007, 0, RTE_REG_ECX, 28)
> +	FEAT_DEF(AVX512VP2INTERSECT, 0x00000007, 0, RTE_REG_EDX, 8)
>  };
>  
>  int
> 

Re: [dpdk-dev] [PATCH v5] eal/cpuflags: add x86 based cpu flags

[Laatz, Kevin]

<snip>

> > ---
> >  devtools/libabigail.abignore              |  5 +++++
> >  lib/librte_eal/x86/include/rte_cpuflags.h | 19 +++++++++++++++++++
> >  lib/librte_eal/x86/rte_cpuflags.c         | 18 ++++++++++++++++++
> >  3 files changed, 42 insertions(+)
> >
> > diff --git a/devtools/libabigail.abignore
> > b/devtools/libabigail.abignore index a59df8f13..045f436fb 100644
> > --- a/devtools/libabigail.abignore
> > +++ b/devtools/libabigail.abignore
> 
> Kevin - you still have the surpession.
> I am testing locally with 1.7.1, and it doesn't complain when I disable the
> supression.
> Are you seeing something different?
> 

Ray,
I have re-tested and with libabigail 1.6 and it reports the addition of the flags as an ABI break without the abignore suppression.
With the suppression, it will still report changes to existing flags (e.g. inserting a new flag somewhere in the middle) in the enum as an ABI break, as expected.

The Travis CI is also based on Ubuntu 18.04 LTS, which uses libabigail 1.2-1. Without the suppression the community Travis CI builds fail on this false positive.

-Kevin 
 

Re: [dpdk-dev] [PATCH v5] eal/cpuflags: add x86 based cpu flags

[Thomas Monjalon]

28/04/2020 20:11, Laatz, Kevin:
> > > --- a/devtools/libabigail.abignore
> > > +++ b/devtools/libabigail.abignore
> > 
> > Kevin - you still have the surpession.
> > I am testing locally with 1.7.1, and it doesn't complain when I disable the
> > supression.
> > Are you seeing something different?
> > 
> 
> Ray,
> I have re-tested and with libabigail 1.6 and it reports the addition of the flags as an ABI break without the abignore suppression.
> With the suppression, it will still report changes to existing flags (e.g. inserting a new flag somewhere in the middle) in the enum as an ABI break, as expected.
> 
> The Travis CI is also based on Ubuntu 18.04 LTS, which uses libabigail 1.2-1. Without the suppression the community Travis CI builds fail on this false positive.

I think Travis uses libabigail 1.6:
http://git.dpdk.org/dpdk/tree/.ci/linux-build.sh#n61

Re: [dpdk-dev] [PATCH v5] eal/cpuflags: add x86 based cpu flags

[Stephen Hemminger]

On Tue, 28 Apr 2020 17:39:24 +0100
Ray Kinsella <mdr@ashroe.eu> wrote:

> > +
> >  	/* The last item */
> >  	RTE_CPUFLAG_NUMFLAGS,               /**< This should always be the last! */
> >  };

These kind of enums break API's. We should remove them all in 20.11.

Re: [dpdk-dev] [PATCH v5] eal/cpuflags: add x86 based cpu flags

[David Marchand]

On Tue, Apr 28, 2020 at 6:39 PM Ray Kinsella <mdr@ashroe.eu> wrote:
> > diff --git a/devtools/libabigail.abignore b/devtools/libabigail.abignore
> > index a59df8f13..045f436fb 100644
> > --- a/devtools/libabigail.abignore
> > +++ b/devtools/libabigail.abignore
>
> Kevin - you still have the surpession.
> I am testing locally with 1.7.1, and it doesn't complain when I disable the supression.
> Are you seeing something different?

Using current master libabigail, without the rule Kevin included, I
get the warning:

1 function with some indirect sub-type change:

  [C] 'function int rte_cpu_get_flag_enabled(rte_cpu_flag_t)' at
rte_cpuflags.c:144:1 has some indirect sub-type changes:
    parameter 1 of type 'enum rte_cpu_flag_t' has sub-type changes:
      type size hasn't changed
      17 enumerator insertions:
        'rte_cpu_flag_t::RTE_CPUFLAG_AVX512DQ' value '87'
        'rte_cpu_flag_t::RTE_CPUFLAG_AVX512IFMA' value '88'
        'rte_cpu_flag_t::RTE_CPUFLAG_AVX512CD' value '89'
        'rte_cpu_flag_t::RTE_CPUFLAG_AVX512BW' value '90'
        'rte_cpu_flag_t::RTE_CPUFLAG_AVX512VL' value '91'
        'rte_cpu_flag_t::RTE_CPUFLAG_AVX512VBMI' value '92'
        'rte_cpu_flag_t::RTE_CPUFLAG_AVX512VBMI2' value '93'
        'rte_cpu_flag_t::RTE_CPUFLAG_GFNI' value '94'
        'rte_cpu_flag_t::RTE_CPUFLAG_VAES' value '95'
        'rte_cpu_flag_t::RTE_CPUFLAG_VPCLMULQDQ' value '96'
        'rte_cpu_flag_t::RTE_CPUFLAG_AVX512VNNI' value '97'
        'rte_cpu_flag_t::RTE_CPUFLAG_AVX512BITALG' value '98'
        'rte_cpu_flag_t::RTE_CPUFLAG_AVX512VPOPCNTDQ' value '99'
        'rte_cpu_flag_t::RTE_CPUFLAG_CLDEMOTE' value '100'
        'rte_cpu_flag_t::RTE_CPUFLAG_MOVDIRI' value '101'
        'rte_cpu_flag_t::RTE_CPUFLAG_MOVDIR64B' value '102'
        'rte_cpu_flag_t::RTE_CPUFLAG_AVX512VP2INTERSECT' value '103'
      1 enumerator change:
        'rte_cpu_flag_t::RTE_CPUFLAG_NUMFLAGS' from value '87' to
'104' at rte_cpuflags.h:12:1


Ray, could you check that the reference and new dumps in your env
contain this enum?

$ grep RTE_CPUFLAG_NUMFLAGS
$HOME/abi/v20.02/x86_64-native-linux-gcc+shared+debug+ASSERT+RTE_IBVERBS_LINK_DLOPEN/dump/librte_eal.dump
      <enumerator name='RTE_CPUFLAG_NUMFLAGS' value='87'/>
$ grep RTE_CPUFLAG_NUMFLAGS
$HOME/builds/x86_64-native-linux-gcc+shared+debug+ASSERT+RTE_IBVERBS_LINK_DLOPEN/install/dump/librte_eal.dump
      <enumerator name='RTE_CPUFLAG_NUMFLAGS' value='104'/>

If you are missing those, you might have built dpdk without debuginfo.

-- 
David Marchand

Re: [dpdk-dev] [PATCH v5] eal/cpuflags: add x86 based cpu flags

[Ray Kinsella]

So that isn't the issue either. 

$ grep RTE_CPUFLAG_NUMFLAGS build-gcc-shared/install/dump/librte_eal.dump
4646:      <enumerator name='RTE_CPUFLAG_NUMFLAGS' value='104'/>
$ grep RTE_CPUFLAG_NUMFLAGS /build/dpdk/reference/v20.02/build-gcc-shared/dump/librte_eal.dump
3296:      <enumerator name='RTE_CPUFLAG_NUMFLAGS' value='87'/>
                                     1.7-1.fc31                             @updates

I finally got libabigail complaining about rte_cpu_flag_t, after doing a complete clear down.
So the suppression _is_ required. 
 
I then spent the following hour trying to identify the gremlin in the system with no luck.
In anycase, added my ack below.


On 29/04/2020 12:39, David Marchand wrote:
> On Tue, Apr 28, 2020 at 6:39 PM Ray Kinsella <mdr@ashroe.eu> wrote:
>>> diff --git a/devtools/libabigail.abignore b/devtools/libabigail.abignore
>>> index a59df8f13..045f436fb 100644
>>> --- a/devtools/libabigail.abignore
>>> +++ b/devtools/libabigail.abignore
>>
>> Kevin - you still have the surpession.
>> I am testing locally with 1.7.1, and it doesn't complain when I disable the supression.
>> Are you seeing something different?
> 
> Using current master libabigail, without the rule Kevin included, I
> get the warning:
> 
> 1 function with some indirect sub-type change:
> 
>   [C] 'function int rte_cpu_get_flag_enabled(rte_cpu_flag_t)' at
> rte_cpuflags.c:144:1 has some indirect sub-type changes:
>     parameter 1 of type 'enum rte_cpu_flag_t' has sub-type changes:
>       type size hasn't changed
>       17 enumerator insertions:
>         'rte_cpu_flag_t::RTE_CPUFLAG_AVX512DQ' value '87'
>         'rte_cpu_flag_t::RTE_CPUFLAG_AVX512IFMA' value '88'
>         'rte_cpu_flag_t::RTE_CPUFLAG_AVX512CD' value '89'
>         'rte_cpu_flag_t::RTE_CPUFLAG_AVX512BW' value '90'
>         'rte_cpu_flag_t::RTE_CPUFLAG_AVX512VL' value '91'
>         'rte_cpu_flag_t::RTE_CPUFLAG_AVX512VBMI' value '92'
>         'rte_cpu_flag_t::RTE_CPUFLAG_AVX512VBMI2' value '93'
>         'rte_cpu_flag_t::RTE_CPUFLAG_GFNI' value '94'
>         'rte_cpu_flag_t::RTE_CPUFLAG_VAES' value '95'
>         'rte_cpu_flag_t::RTE_CPUFLAG_VPCLMULQDQ' value '96'
>         'rte_cpu_flag_t::RTE_CPUFLAG_AVX512VNNI' value '97'
>         'rte_cpu_flag_t::RTE_CPUFLAG_AVX512BITALG' value '98'
>         'rte_cpu_flag_t::RTE_CPUFLAG_AVX512VPOPCNTDQ' value '99'
>         'rte_cpu_flag_t::RTE_CPUFLAG_CLDEMOTE' value '100'
>         'rte_cpu_flag_t::RTE_CPUFLAG_MOVDIRI' value '101'
>         'rte_cpu_flag_t::RTE_CPUFLAG_MOVDIR64B' value '102'
>         'rte_cpu_flag_t::RTE_CPUFLAG_AVX512VP2INTERSECT' value '103'
>       1 enumerator change:
>         'rte_cpu_flag_t::RTE_CPUFLAG_NUMFLAGS' from value '87' to
> '104' at rte_cpuflags.h:12:1
> 
> 
> Ray, could you check that the reference and new dumps in your env
> contain this enum?
> 
> $ grep RTE_CPUFLAG_NUMFLAGS
> $HOME/abi/v20.02/x86_64-native-linux-gcc+shared+debug+ASSERT+RTE_IBVERBS_LINK_DLOPEN/dump/librte_eal.dump
>       <enumerator name='RTE_CPUFLAG_NUMFLAGS' value='87'/>
> $ grep RTE_CPUFLAG_NUMFLAGS
> $HOME/builds/x86_64-native-linux-gcc+shared+debug+ASSERT+RTE_IBVERBS_LINK_DLOPEN/install/dump/librte_eal.dump
>       <enumerator name='RTE_CPUFLAG_NUMFLAGS' value='104'/>
> 
> If you are missing those, you might have built dpdk without debuginfo.
> 

Acked-By: Ray Kinsella <mdr@ashroe.eu>

Re: [dpdk-dev] [PATCH v5] eal/cpuflags: add x86 based cpu flags

[Thomas Monjalon]

> Acked-By: Ray Kinsella <mdr@ashroe.eu>

Applied, thanks