From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 817CCA057C; Fri, 27 Mar 2020 09:56:09 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 28DDC1C07F; Fri, 27 Mar 2020 09:56:09 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 3A0A34C93 for ; Fri, 27 Mar 2020 09:56:08 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 02R8toBV006702; Fri, 27 Mar 2020 01:56:05 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=tqtCKTy3l1IOwvcjXt7uumHEZTw+ROpLoByDmubaLH8=; b=GZS1AVDJrj6aUogVt7ElNtPq4PTKOEMQewNI0jhZ8iOMzgj7luPqAeXsfA1DNnSxAmu6 twpVrknJjOnHS6WOabNIdkGVYHFy+oLmxiw2h/H0Tg+jan6J1U0zYIhvmGXTZhSK+C7v uVeQebjf3En3nQ06rfH4d/0/4ZzZS9gyv/8cqYdB1NjHcMA1Aychr+rLjpWLDNTg8CpT 4mqp1uU25NKkz7nlwFMHywGAh+8pc1sYrDAdBTu69lBhexEbFjW83FYUmz7zCwUKUn0k tbKI7Owk8tyR+E+8u2HMoAJjqoV3f1Yy3jbOyE5co8jZrSo+dRUp1mKz3WyEN++FVqyQ 9w== Received: from sc-exch01.marvell.com ([199.233.58.181]) by mx0b-0016f401.pphosted.com with ESMTP id 300bpd0bej-4 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Fri, 27 Mar 2020 01:56:05 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 27 Mar 2020 01:56:03 -0700 Received: from SC-EXCH03.marvell.com (10.93.176.83) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 27 Mar 2020 01:56:02 -0700 Received: from maili.marvell.com (10.93.176.43) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 27 Mar 2020 01:56:01 -0700 Received: from BG-LT7430.marvell.com (BG-LT7430.marvell.com [10.28.163.117]) by maili.marvell.com (Postfix) with ESMTP id 08D7E3F703F; Fri, 27 Mar 2020 01:55:59 -0700 (PDT) From: To: , , , Pavan Nikhilesh CC: Date: Fri, 27 Mar 2020 14:25:58 +0530 Message-ID: <20200327085558.1136-1-pbhagavatula@marvell.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.645 definitions=2020-03-27_02:2020-03-26, 2020-03-27 signatures=0 Subject: [dpdk-dev] [PATCH] event/octeontx2: use c11 atomics for statistics X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Use c11 atomics with RELAXED ordering instead of rte_atomic ops which enforce unnessary barries on arm64. Signed-off-by: Pavan Nikhilesh --- drivers/event/octeontx2/otx2_tim_evdev.c | 5 +++-- drivers/event/octeontx2/otx2_tim_evdev.h | 2 +- drivers/event/octeontx2/otx2_tim_worker.c | 5 +++-- 3 files changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/event/octeontx2/otx2_tim_evdev.c b/drivers/event/octeontx2/otx2_tim_evdev.c index cd0dcde24..4c24cc8a6 100644 --- a/drivers/event/octeontx2/otx2_tim_evdev.c +++ b/drivers/event/octeontx2/otx2_tim_evdev.c @@ -526,7 +526,8 @@ otx2_tim_stats_get(const struct rte_event_timer_adapter *adapter, uint64_t bkt_cyc = rte_rdtsc() - tim_ring->ring_start_cyc; - stats->evtim_exp_count = rte_atomic64_read(&tim_ring->arm_cnt); + stats->evtim_exp_count = __atomic_load_n(&tim_ring->arm_cnt, + __ATOMIC_RELAXED); stats->ev_enq_count = stats->evtim_exp_count; stats->adapter_tick_count = rte_reciprocal_divide_u64(bkt_cyc, &tim_ring->fast_div); @@ -538,7 +539,7 @@ otx2_tim_stats_reset(const struct rte_event_timer_adapter *adapter) { struct otx2_tim_ring *tim_ring = adapter->data->adapter_priv; - rte_atomic64_clear(&tim_ring->arm_cnt); + __atomic_store_n(&tim_ring->arm_cnt, 0, __ATOMIC_RELAXED); return 0; } diff --git a/drivers/event/octeontx2/otx2_tim_evdev.h b/drivers/event/octeontx2/otx2_tim_evdev.h index 56895dcbf..44e3c7b51 100644 --- a/drivers/event/octeontx2/otx2_tim_evdev.h +++ b/drivers/event/octeontx2/otx2_tim_evdev.h @@ -149,7 +149,7 @@ struct otx2_tim_ring { struct otx2_tim_bkt *bkt; struct rte_mempool *chunk_pool; struct rte_reciprocal_u64 fast_div; - rte_atomic64_t arm_cnt; + uint64_t arm_cnt; uint8_t prod_type_sp; uint8_t enable_stats; uint8_t disable_npa; diff --git a/drivers/event/octeontx2/otx2_tim_worker.c b/drivers/event/octeontx2/otx2_tim_worker.c index 104674c79..4b5cfdc72 100644 --- a/drivers/event/octeontx2/otx2_tim_worker.c +++ b/drivers/event/octeontx2/otx2_tim_worker.c @@ -88,7 +88,7 @@ tim_timer_arm_burst(const struct rte_event_timer_adapter *adptr, } if (flags & OTX2_TIM_ENA_STATS) - rte_atomic64_add(&tim_ring->arm_cnt, index); + __atomic_fetch_add(&tim_ring->arm_cnt, index, __ATOMIC_RELAXED); return index; } @@ -130,7 +130,8 @@ tim_timer_arm_tmo_brst(const struct rte_event_timer_adapter *adptr, break; } if (flags & OTX2_TIM_ENA_STATS) - rte_atomic64_add(&tim_ring->arm_cnt, set_timers); + __atomic_fetch_add(&tim_ring->arm_cnt, set_timers, + __ATOMIC_RELAXED); return set_timers; } -- 2.17.1