From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id C732CA0598; Fri, 10 Apr 2020 18:41:44 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 35AC61D5A9; Fri, 10 Apr 2020 18:41:44 +0200 (CEST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by dpdk.org (Postfix) with ESMTP id 3EB611D595 for ; Fri, 10 Apr 2020 18:41:42 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B0C9030E; Fri, 10 Apr 2020 09:41:41 -0700 (PDT) Received: from net-arm-thunderx2-01.shanghai.arm.com (net-arm-thunderx2-01.shanghai.arm.com [10.169.41.214]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 7E4683F52E; Fri, 10 Apr 2020 09:41:37 -0700 (PDT) From: Gavin Hu To: dev@dpdk.org Cc: nd@arm.com, david.marchand@redhat.com, thomas@monjalon.net, rasland@mellanox.com, drc@linux.vnet.ibm.com, bruce.richardson@intel.com, konstantin.ananyev@intel.com, matan@mellanox.com, shahafs@mellanox.com, viacheslavo@mellanox.com, jerinj@marvell.com, Honnappa.Nagarahalli@arm.com, ruifeng.wang@arm.com, phil.yang@arm.com, joyce.kong@arm.com, steve.capper@arm.com Date: Sat, 11 Apr 2020 00:41:20 +0800 Message-Id: <20200410164127.54229-1-gavin.hu@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200213123854.203566-1-gavin.hu@arm.com> References: <20200213123854.203566-1-gavin.hu@arm.com> Subject: [dpdk-dev] [PATCH RFC v2 0/7] introduce new barrier class and use it for mlx5 PMD X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" To order writes to various memory types, 'sfence' is required for x86, and 'dmb oshst' is required for aarch64. But within DPDK, there is no abstracted barriers covers this combination: sfence(x86)/dmb(aarch64). So introduce a new barrier class - rte_dma_*mb for this combination, Doorbell rings are typical use cases of this new barrier class, which requires something ready in the memory before letting HW aware. As a note, rte_io_wmb and rte_cio_wmb are compiler barriers for x86, while rte_wmb is 'dsb' for aarch64. In the joint preliminary testing between Arm and Ampere, 8%~13% performance boost was measured. As there is no functionality changes, it will not impact x86. Gavin Hu (6): eal: introduce new class of barriers for DMA use cases net/mlx5: dmb for immediate doorbell ring on aarch64 net/mlx5: relax barrier to order UAR writes on aarch64 net/mlx5: relax barrier for aarch64 net/mlx5: add descriptive comment for a barrier doc: clarify one configuration in mlx5 guide Phil Yang (1): net/mlx5: relax ordering for multi-packet RQ buffer refcnt doc/guides/nics/mlx5.rst | 6 ++-- drivers/net/mlx5/mlx5_rxq.c | 2 +- drivers/net/mlx5/mlx5_rxtx.c | 16 ++++++----- drivers/net/mlx5/mlx5_rxtx.h | 14 ++++++---- lib/librte_eal/arm/include/rte_atomic_32.h | 6 ++++ lib/librte_eal/arm/include/rte_atomic_64.h | 6 ++++ lib/librte_eal/include/generic/rte_atomic.h | 31 +++++++++++++++++++++ lib/librte_eal/ppc/include/rte_atomic.h | 6 ++++ lib/librte_eal/x86/include/rte_atomic.h | 6 ++++ 9 files changed, 78 insertions(+), 15 deletions(-) -- 2.17.1