From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id D92C3A058A; Fri, 17 Apr 2020 08:41:27 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id B3F171DE4F; Fri, 17 Apr 2020 08:41:27 +0200 (CEST) Received: from mail-pl1-f193.google.com (mail-pl1-f193.google.com [209.85.214.193]) by dpdk.org (Postfix) with ESMTP id C62541DB28 for ; Fri, 17 Apr 2020 08:41:25 +0200 (CEST) Received: by mail-pl1-f193.google.com with SMTP id f8so626360plt.2 for ; Thu, 16 Apr 2020 23:41:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=LjkqQLLXQjp0f4T8c+9ATlpbSgrKbDCpfkblBbY2y2g=; b=U7GjTeQuCeapuN5Am+3+BqfhktgZmZmgUT44f4BcdXbN8iivJQ/GBah3GHHpoVSGSO 8q+y+wbuW0qTFmn2dTcxAwJqRjxAj2FIyF9DHUmat021d+vpW4BpFYj26XTacvTHY2gG J/e817g+YRoxPCNY1G3ePrpUnEmtO5jZBrgwYqtsn/ZQbI5rWB0KR9m4tQpg4aogkJOh GCl8KltPnuiV/XHVM/luv3s5RiDhooewAuPFgC07/vppMfavKhKufArPb7ijLcyoMbVc 7JSD7YLpSThTpuCvrH4dXd732uh6EgO8GD1z/HuV87X3+fHKIR3NB8+T74QHNAFXyWao +gAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=LjkqQLLXQjp0f4T8c+9ATlpbSgrKbDCpfkblBbY2y2g=; b=PaE0tCRgWrFOW/VUWRLLdYcNDk7F4hOXu1MI77fFy5gVsqYpViYZiBud9RMlB5D/+c Ql6SzBVTcjoe8YmjDdfLSMrRleZNd+zb3sYipKT+ENbjR01z5Yir6Uxs/pLexW5VF7TO 0FWBwRsnNI2JISySboGh2Jjq0/xYheAZ+VarBs+7m0jIvKZ+GER7g+4RaegkfAh9w2gw t+6SQrrS1p/fiY8Ejc0i359bqpHQxMbL7CLO+NPzx3Y4TIbjeB1/QyMT4FGSq1W54Bz9 LXhT2Y3jS2ZByeLY/JOX6LP643+IOAE5d/lIfsZj/rtaU4GaL57EhOteDLkXVUDGU67B hMpQ== X-Gm-Message-State: AGi0PuYVrCeXy18ECn8ZhUtChhIes5s+/gs+OVNiwZkyfTCSqI+Dwp95 kyzH3dJlokID9s5DE4PNXoPVgikZ0r0= X-Google-Smtp-Source: APiQypJJPDplw8vTayUX/YsW87G2Vkh8os9j/fbyFaljCbfYnjDcHSo6Wve1tk+h1WDvjIi6E76PjQ== X-Received: by 2002:a17:90a:7784:: with SMTP id v4mr2687191pjk.30.1587105684893; Thu, 16 Apr 2020 23:41:24 -0700 (PDT) Received: from hyd1588t430.marvell.com ([115.113.156.2]) by smtp.gmail.com with ESMTPSA id 189sm18379625pfg.170.2020.04.16.23.41.22 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 16 Apr 2020 23:41:24 -0700 (PDT) From: Nithin Dabilpuram To: Jerin Jacob , Nithin Dabilpuram , Kiran Kumar K Cc: dev@dpdk.org, kkanas@marvell.com Date: Fri, 17 Apr 2020 12:11:13 +0530 Message-Id: <20200417064113.7459-1-nithind1988@gmail.com> X-Mailer: git-send-email 2.8.4 Subject: [dpdk-dev] [PATCH] net/octeontx2: update red algo for shaper dynamic update X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Nithin Dabilpuram Due to an errata red algo needs to be set to discard instead of stall for 96XX C0 silicon for two rate shaping. This workaround is being already handled for newly created hierarchy but not for dynamic shaper update cases. This patch hence applies the workaround even when for shaper dynamic update. Signed-off-by: Nithin Dabilpuram --- Depends-on:series-9313 drivers/net/octeontx2/otx2_tm.c | 39 +++++++++++++++++++++++++++------------ drivers/net/octeontx2/otx2_tm.h | 1 + 2 files changed, 28 insertions(+), 12 deletions(-) diff --git a/drivers/net/octeontx2/otx2_tm.c b/drivers/net/octeontx2/otx2_tm.c index fa7d21b..e94a276 100644 --- a/drivers/net/octeontx2/otx2_tm.c +++ b/drivers/net/octeontx2/otx2_tm.c @@ -237,6 +237,30 @@ shaper_config_to_nix(struct otx2_nix_tm_shaper_profile *profile, &pir->burst_mantissa); } +static void +shaper_default_red_algo(struct otx2_eth_dev *dev, + struct otx2_nix_tm_node *tm_node, + struct otx2_nix_tm_shaper_profile *profile) +{ + struct shaper_params cir, pir; + + /* C0 doesn't support STALL when both PIR & CIR are enabled */ + if (profile && otx2_dev_is_96xx_Cx(dev)) { + memset(&cir, 0, sizeof(cir)); + memset(&pir, 0, sizeof(pir)); + shaper_config_to_nix(profile, &cir, &pir); + + if (pir.rate && cir.rate) { + tm_node->red_algo = NIX_REDALG_DISCARD; + tm_node->flags |= NIX_TM_NODE_RED_DISCARD; + return; + } + } + + tm_node->red_algo = NIX_REDALG_STD; + tm_node->flags &= ~NIX_TM_NODE_RED_DISCARD; +} + static int populate_tm_tl1_default(struct otx2_eth_dev *dev, uint32_t schq) { @@ -765,7 +789,6 @@ nix_tm_node_add_to_list(struct otx2_eth_dev *dev, uint32_t node_id, { struct otx2_nix_tm_shaper_profile *profile; struct otx2_nix_tm_node *tm_node, *parent_node; - struct shaper_params cir, pir; uint32_t profile_id; profile_id = params->shaper_profile_id; @@ -808,19 +831,9 @@ nix_tm_node_add_to_list(struct otx2_eth_dev *dev, uint32_t node_id, if (profile) profile->reference_count++; - memset(&cir, 0, sizeof(cir)); - memset(&pir, 0, sizeof(pir)); - shaper_config_to_nix(profile, &cir, &pir); - tm_node->parent = parent_node; tm_node->parent_hw_id = UINT32_MAX; - /* C0 doesn't support STALL when both PIR & CIR are enabled */ - if (lvl < OTX2_TM_LVL_QUEUE && - otx2_dev_is_96xx_Cx(dev) && - pir.rate && cir.rate) - tm_node->red_algo = NIX_REDALG_DISCARD; - else - tm_node->red_algo = NIX_REDALG_STD; + shaper_default_red_algo(dev, tm_node, profile); TAILQ_INSERT_TAIL(&dev->node_list, tm_node, node); @@ -2594,6 +2607,8 @@ otx2_nix_tm_node_shaper_update(struct rte_eth_dev *eth_dev, if (rc) return rc; + shaper_default_red_algo(dev, tm_node, profile); + /* Update the PIR/CIR and clear SW XOFF */ req = otx2_mbox_alloc_msg_nix_txschq_cfg(mbox); req->lvl = tm_node->hw_lvl; diff --git a/drivers/net/octeontx2/otx2_tm.h b/drivers/net/octeontx2/otx2_tm.h index cdca987..db44d48 100644 --- a/drivers/net/octeontx2/otx2_tm.h +++ b/drivers/net/octeontx2/otx2_tm.h @@ -46,6 +46,7 @@ struct otx2_nix_tm_node { #define NIX_TM_NODE_HWRES BIT_ULL(0) #define NIX_TM_NODE_ENABLED BIT_ULL(1) #define NIX_TM_NODE_USER BIT_ULL(2) +#define NIX_TM_NODE_RED_DISCARD BIT_ULL(3) /* Shaper algorithm for RED state @NIX_REDALG_E */ uint32_t red_algo:2; uint32_t pkt_mode:1; -- 2.8.4