From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4B296A04AD; Fri, 1 May 2020 16:24:33 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 241EC1DA5C; Fri, 1 May 2020 16:24:33 +0200 (CEST) Received: from mail-pf1-f196.google.com (mail-pf1-f196.google.com [209.85.210.196]) by dpdk.org (Postfix) with ESMTP id CA97B1D9D9 for ; Fri, 1 May 2020 16:24:31 +0200 (CEST) Received: by mail-pf1-f196.google.com with SMTP id x15so1662327pfa.1 for ; Fri, 01 May 2020 07:24:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=pGbP8ZnpW6uJ6GkdwgX/3OwrngvOV8BUZqdGrWpGAto=; b=r4voKJCfq9LEtU7Op4P+DHkhGT32FmFQL6cjxhnGv2KhR2lmdTOoghBZordJYqHIiv HKMfyCpPDzobr9G1Vtyf/bs1bbdGX9zItWMhPKZL2jgh9G634nKMnfwoJFWQlBEh5cs0 xtu+F+F8D1Di5Nho1vV4tNnHowWZ132nYHHRHWxDdAVs7MlHOCG8E7B0WcLzKiiECo+c T9zGl/jRGpyYo4o3pjtlpEftaCgr/9PCgKlNAnS1IYI+6/sKgOKBqOIv8V8wzePYr2zn E5Ef+damjRsRm3eovA44n1znCDj5hl+yN/+QldZ1UxYQ/SBtQ/1/+WCnY/7Mr81uq98n NtzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=pGbP8ZnpW6uJ6GkdwgX/3OwrngvOV8BUZqdGrWpGAto=; b=t6yMNnDaBBD0DXiQmFb50fJdeQXkHLvdEbGzIV5hq/tL5GOp2GQnuLaRBD0tKAsc9C vEWNrkTvlP90hj6KaJ6rtpgF75xfEuO+cTildVXGdYI1m81ieAm+K/UazP3WpBQG4Pj2 xG/y7TYhLNHrcMLfJ0nROnkXLc5ofjIBlQYx68NIBERAf9Jqe3HUM7LgVGcaNO2RlbTp 4Hq7MGpcCjUcZc5uidvOyzJF492nPnTT20mnfLYx7ibI2Fh505Zj/k9SAD8GFl2nDaUG K4PW66l9Ap9XZxNMk9iqxOqLRnNIZbIajBdCGwtKb83Yi7KwmRc8s8hy/QN9FlMHrs9Q amsQ== X-Gm-Message-State: AGi0PuaTGzHT2a2svIIGwg+hOtmBRTattx1O/Z2iEIbnOTJ0p2GQdiCA I6zFtwEvJq83CC3BAktzGtsyDUCal88= X-Google-Smtp-Source: APiQypK5swnxQLtCNepzHvpK8AsGx2cqs3kiE8tElinH7JSPI3UZGtoPjIXdHTJKKgPie12i7Nt/GQ== X-Received: by 2002:aa7:979d:: with SMTP id o29mr4519481pfp.90.1588343070863; Fri, 01 May 2020 07:24:30 -0700 (PDT) Received: from hyd1588t430.marvell.com ([115.113.156.2]) by smtp.gmail.com with ESMTPSA id a129sm2491439pfb.102.2020.05.01.07.24.27 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 01 May 2020 07:24:28 -0700 (PDT) From: Nithin Dabilpuram To: Jerin Jacob , Nithin Dabilpuram , Kiran Kumar K Cc: dev@dpdk.org, kkanas@marvell.com Date: Fri, 1 May 2020 19:54:16 +0530 Message-Id: <20200501142417.28243-1-nithind1988@gmail.com> X-Mailer: git-send-email 2.8.4 In-Reply-To: <20200417064113.7459-1-nithind1988@gmail.com> References: <20200417064113.7459-1-nithind1988@gmail.com> Subject: [dpdk-dev] [PATCH v2] net/octeontx2: update red algo for shaper dynamic update X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Nithin Dabilpuram Due to an errata red algo needs to be set to discard instead of stall for 96XX C0 silicon for two rate shaping. This workaround is being already handled for newly created hierarchy but not for dynamic shaper update cases. This patch hence applies the workaround even when for shaper dynamic update. Signed-off-by: Nithin Dabilpuram --- v2: - Rebased patch to fix dependency issue drivers/net/octeontx2/otx2_tm.c | 39 +++++++++++++++++++++++++++------------ drivers/net/octeontx2/otx2_tm.h | 1 + 2 files changed, 28 insertions(+), 12 deletions(-) diff --git a/drivers/net/octeontx2/otx2_tm.c b/drivers/net/octeontx2/otx2_tm.c index f94618d..b57e10f 100644 --- a/drivers/net/octeontx2/otx2_tm.c +++ b/drivers/net/octeontx2/otx2_tm.c @@ -237,6 +237,30 @@ shaper_config_to_nix(struct otx2_nix_tm_shaper_profile *profile, &pir->burst_mantissa); } +static void +shaper_default_red_algo(struct otx2_eth_dev *dev, + struct otx2_nix_tm_node *tm_node, + struct otx2_nix_tm_shaper_profile *profile) +{ + struct shaper_params cir, pir; + + /* C0 doesn't support STALL when both PIR & CIR are enabled */ + if (profile && otx2_dev_is_96xx_Cx(dev)) { + memset(&cir, 0, sizeof(cir)); + memset(&pir, 0, sizeof(pir)); + shaper_config_to_nix(profile, &cir, &pir); + + if (pir.rate && cir.rate) { + tm_node->red_algo = NIX_REDALG_DISCARD; + tm_node->flags |= NIX_TM_NODE_RED_DISCARD; + return; + } + } + + tm_node->red_algo = NIX_REDALG_STD; + tm_node->flags &= ~NIX_TM_NODE_RED_DISCARD; +} + static int populate_tm_tl1_default(struct otx2_eth_dev *dev, uint32_t schq) { @@ -744,7 +768,6 @@ nix_tm_node_add_to_list(struct otx2_eth_dev *dev, uint32_t node_id, { struct otx2_nix_tm_shaper_profile *profile; struct otx2_nix_tm_node *tm_node, *parent_node; - struct shaper_params cir, pir; uint32_t profile_id; profile_id = params->shaper_profile_id; @@ -778,19 +801,9 @@ nix_tm_node_add_to_list(struct otx2_eth_dev *dev, uint32_t node_id, if (profile) profile->reference_count++; - memset(&cir, 0, sizeof(cir)); - memset(&pir, 0, sizeof(pir)); - shaper_config_to_nix(profile, &cir, &pir); - tm_node->parent = parent_node; tm_node->parent_hw_id = UINT32_MAX; - /* C0 doesn't support STALL when both PIR & CIR are enabled */ - if (lvl < OTX2_TM_LVL_QUEUE && - otx2_dev_is_96xx_Cx(dev) && - pir.rate && cir.rate) - tm_node->red_algo = NIX_REDALG_DISCARD; - else - tm_node->red_algo = NIX_REDALG_STD; + shaper_default_red_algo(dev, tm_node, profile); TAILQ_INSERT_TAIL(&dev->node_list, tm_node, node); @@ -2500,6 +2513,8 @@ otx2_nix_tm_node_shaper_update(struct rte_eth_dev *eth_dev, if (rc) return rc; + shaper_default_red_algo(dev, tm_node, profile); + /* Update the PIR/CIR and clear SW XOFF */ req = otx2_mbox_alloc_msg_nix_txschq_cfg(mbox); req->lvl = tm_node->hw_lvl; diff --git a/drivers/net/octeontx2/otx2_tm.h b/drivers/net/octeontx2/otx2_tm.h index 9675182..4a80c23 100644 --- a/drivers/net/octeontx2/otx2_tm.h +++ b/drivers/net/octeontx2/otx2_tm.h @@ -46,6 +46,7 @@ struct otx2_nix_tm_node { #define NIX_TM_NODE_HWRES BIT_ULL(0) #define NIX_TM_NODE_ENABLED BIT_ULL(1) #define NIX_TM_NODE_USER BIT_ULL(2) +#define NIX_TM_NODE_RED_DISCARD BIT_ULL(3) /* Shaper algorithm for RED state @NIX_REDALG_E */ uint32_t red_algo:2; -- 2.8.4