From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 105AEA04EF; Wed, 3 Jun 2020 04:43:44 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id CA2DF1D5B3; Wed, 3 Jun 2020 04:37:53 +0200 (CEST) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id 3C9BB1D597 for ; Wed, 3 Jun 2020 04:37:51 +0200 (CEST) IronPort-SDR: /vYWk7J74jznZ+oX469IFwTXeVoMw6pzu/Rn8rIWuEkbBzbz2od1p96G5tmMrYh6juNPRCLfB4 Z1k28Uv5CSWg== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Jun 2020 19:37:50 -0700 IronPort-SDR: U7uu0dGhrcmk1bhPJTktDg7SMFrYAZ5D9BKpefzfqUsueyp1MM8dUqFGtrfg1FBlNVQEMO/t0L nlfGK2W2a3Sg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,466,1583222400"; d="scan'208";a="347614308" Received: from dpdk51.sh.intel.com ([10.67.111.82]) by orsmga001.jf.intel.com with ESMTP; 02 Jun 2020 19:37:47 -0700 From: Qi Zhang To: qiming.yang@intel.com Cc: dev@dpdk.org, xiaolong.ye@intel.com, Qi Zhang , Tarun Singh , "Paul M . Stillwell Jr" Date: Wed, 3 Jun 2020 10:40:07 +0800 Message-Id: <20200603024016.30636-44-qi.z.zhang@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20200603024016.30636-1-qi.z.zhang@intel.com> References: <20200603024016.30636-1-qi.z.zhang@intel.com> Subject: [dpdk-dev] [PATCH 43/52] net/ice/base: adjust scheduler default BW weight X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" By default the queues are configured in legacy mode. The default BW settings for legacy/advanced modes are different. The existing code was using the advanced mode default value of 1 which was incorrect. This caused the unbalanced BW sharing among siblings. The recommneded default value is applied. Signed-off-by: Tarun Singh Signed-off-by: Paul M. Stillwell Jr Signed-off-by: Qi Zhang --- drivers/net/ice/base/ice_common.c | 13 ++++++++++++- drivers/net/ice/base/ice_type.h | 2 +- 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index d02a047f6..54112e8f2 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -4012,7 +4012,18 @@ ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 q_handle, * Without setting the generic section as valid in valid_sections, the * Admin queue command will fail with error code ICE_AQ_RC_EINVAL. */ - buf->txqs[0].info.valid_sections = ICE_AQC_ELEM_VALID_GENERIC; + buf->txqs[0].info.valid_sections = + ICE_AQC_ELEM_VALID_GENERIC | ICE_AQC_ELEM_VALID_CIR | + ICE_AQC_ELEM_VALID_EIR; + buf->txqs[0].info.generic = 0; + buf->txqs[0].info.cir_bw.bw_profile_idx = + CPU_TO_LE16(ICE_SCHED_DFLT_RL_PROF_ID); + buf->txqs[0].info.cir_bw.bw_alloc = + CPU_TO_LE16(ICE_SCHED_DFLT_BW_WT); + buf->txqs[0].info.eir_bw.bw_profile_idx = + CPU_TO_LE16(ICE_SCHED_DFLT_RL_PROF_ID); + buf->txqs[0].info.eir_bw.bw_alloc = + CPU_TO_LE16(ICE_SCHED_DFLT_BW_WT); /* add the LAN queue */ status = ice_aq_add_lan_txq(hw, num_qgrps, buf, buf_size, cd); diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h index a6dece9c1..41a1912bf 100644 --- a/drivers/net/ice/base/ice_type.h +++ b/drivers/net/ice/base/ice_type.h @@ -610,7 +610,7 @@ enum ice_rl_type { #define ICE_SCHED_NO_BW_WT 0 #define ICE_SCHED_DFLT_RL_PROF_ID 0 #define ICE_SCHED_NO_SHARED_RL_PROF_ID 0xFFFF -#define ICE_SCHED_DFLT_BW_WT 1 +#define ICE_SCHED_DFLT_BW_WT 4 #define ICE_SCHED_INVAL_PROF_ID 0xFFFF #define ICE_SCHED_DFLT_BURST_SIZE (15 * 1024) /* in bytes (15k) */ -- 2.13.6