From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 1F33BA04F2; Sun, 7 Jun 2020 12:19:41 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id C708F1BFB2; Sun, 7 Jun 2020 12:19:39 +0200 (CEST) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by dpdk.org (Postfix) with ESMTP id A87821BF58 for ; Sun, 7 Jun 2020 12:19:37 +0200 (CEST) IronPort-SDR: JqnA2ME+LQ9u1NTCklfHwWg3eiH6qWXHGcF00BmzupBHr3HwDHXjBcoCsZPBYjN3dSbM6Xjo3F iI8/2VZoAWLQ== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Jun 2020 03:19:36 -0700 IronPort-SDR: guEVy8dcQ+VdEgOGCySLQeuuv3AFnpS09hVq7OBRZYeEzRs2CfYwbXODyh7AALHzHqWxybhHwY BPdGib2iIO8w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,483,1583222400"; d="scan'208";a="472389758" Received: from yexl-server.sh.intel.com (HELO localhost) ([10.67.116.183]) by fmsmga005.fm.intel.com with ESMTP; 07 Jun 2020 03:19:34 -0700 Date: Sun, 7 Jun 2020 18:11:22 +0800 From: Ye Xiaolong To: Ting Xu Cc: dev@dpdk.org, qi.z.zhang@intel.com, qiming.yang@intel.com, john.mcnamara@intel.com, marko.kovacevic@intel.com Message-ID: <20200607101122.GA7883@intel.com> References: <20200605201737.33766-1-ting.xu@intel.com> <20200605201737.33766-9-ting.xu@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200605201737.33766-9-ting.xu@intel.com> User-Agent: Mutt/1.9.4 (2018-02-28) Subject: Re: [dpdk-dev] [PATCH v1 08/12] net/ice: add queue config in DCF X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On 06/05, Ting Xu wrote: >From: Qi Zhang > >Add queues and Rx queue irqs configuration during device start >in DCF. The setup is sent to PF via virtchnl. > >Signed-off-by: Qi Zhang >--- > drivers/net/ice/ice_dcf.c | 109 +++++++++++++++++++++++++++ > drivers/net/ice/ice_dcf.h | 6 ++ > drivers/net/ice/ice_dcf_ethdev.c | 125 +++++++++++++++++++++++++++++++ > 3 files changed, 240 insertions(+) > >diff --git a/drivers/net/ice/ice_dcf.c b/drivers/net/ice/ice_dcf.c >index 8d078163e..d864ae894 100644 >--- a/drivers/net/ice/ice_dcf.c >+++ b/drivers/net/ice/ice_dcf.c >@@ -24,6 +24,7 @@ > #include > > #include "ice_dcf.h" >+#include "ice_rxtx.h" > > #define ICE_DCF_AQ_LEN 32 > #define ICE_DCF_AQ_BUF_SZ 4096 >@@ -831,3 +832,111 @@ ice_dcf_init_rss(struct ice_dcf_hw *hw) > > return 0; > } >+ >+#define IAVF_RXDID_LEGACY_1 1 >+#define IAVF_RXDID_COMMS_GENERIC 16 >+ >+int >+ice_dcf_configure_queues(struct ice_dcf_hw *hw) >+{ >+ struct ice_rx_queue **rxq = >+ (struct ice_rx_queue **)hw->eth_dev->data->rx_queues; >+ struct ice_tx_queue **txq = >+ (struct ice_tx_queue **)hw->eth_dev->data->tx_queues; >+ struct virtchnl_vsi_queue_config_info *vc_config; >+ struct virtchnl_queue_pair_info *vc_qp; >+ struct dcf_virtchnl_cmd args; >+ uint16_t i, size; >+ int err; >+ >+ size = sizeof(*vc_config) + >+ sizeof(vc_config->qpair[0]) * hw->num_queue_pairs; >+ vc_config = rte_zmalloc("cfg_queue", size, 0); >+ if (!vc_config) >+ return -ENOMEM; >+ >+ vc_config->vsi_id = hw->vsi_res->vsi_id; >+ vc_config->num_queue_pairs = hw->num_queue_pairs; >+ >+ for (i = 0, vc_qp = vc_config->qpair; >+ i < hw->num_queue_pairs; >+ i++, vc_qp++) { >+ vc_qp->txq.vsi_id = hw->vsi_res->vsi_id; >+ vc_qp->txq.queue_id = i; >+ if (i < hw->eth_dev->data->nb_tx_queues) { >+ vc_qp->txq.ring_len = txq[i]->nb_tx_desc; >+ vc_qp->txq.dma_ring_addr = txq[i]->tx_ring_dma; >+ } >+ vc_qp->rxq.vsi_id = hw->vsi_res->vsi_id; >+ vc_qp->rxq.queue_id = i; >+ vc_qp->rxq.max_pkt_size = rxq[i]->max_pkt_len; >+ if (i < hw->eth_dev->data->nb_rx_queues) { What about changing as below to reduce the nested level of if blocks. if (i >= hw->eth_dev->data->nb_rx_queues) break; vc_qp->rxq.ring_len = rxq[i]->nb_rx_desc; vc_qp->rxq.dma_ring_addr = rxq[i]->rx_ring_dma; vc_qp->rxq.databuffer_size = rxq[i]->rx_buf_len; ... } >+ vc_qp->rxq.ring_len = rxq[i]->nb_rx_desc; >+ vc_qp->rxq.dma_ring_addr = rxq[i]->rx_ring_dma; >+ vc_qp->rxq.databuffer_size = rxq[i]->rx_buf_len; >+ >+ if (hw->vf_res->vf_cap_flags & >+ VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC && >+ hw->supported_rxdid & >+ BIT(IAVF_RXDID_COMMS_GENERIC)) { >+ vc_qp->rxq.rxdid = IAVF_RXDID_COMMS_GENERIC; >+ PMD_DRV_LOG(NOTICE, "request RXDID == %d in " [snip] >+static inline uint16_t >+iavf_calc_itr_interval(int16_t interval) >+{ >+ if (interval < 0 || interval > IAVF_QUEUE_ITR_INTERVAL_MAX) >+ interval = IAVF_QUEUE_ITR_INTERVAL_DEFAULT; >+ >+ /* Convert to hardware count, as writing each 1 represents 2 us */ >+ return interval / 2; >+} >+ >+static int ice_dcf_config_rx_queues_irqs(struct rte_eth_dev *dev, >+ struct rte_intr_handle *intr_handle) put the return type in a separate line. >+{ >+ struct ice_dcf_adapter *adapter = dev->data->dev_private; >+ struct ice_dcf_hw *hw = &adapter->real_hw; >+ uint16_t interval, i; >+ int vec; >+ >+ if (rte_intr_cap_multiple(intr_handle) && >+ dev->data->dev_conf.intr_conf.rxq) { >+ if (rte_intr_efd_enable(intr_handle, dev->data->nb_rx_queues)) >+ return -1; >+ } >+ >+ if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) { >+ intr_handle->intr_vec = >+ rte_zmalloc("intr_vec", >+ dev->data->nb_rx_queues * sizeof(int), 0); >+ if (!intr_handle->intr_vec) { >+ PMD_DRV_LOG(ERR, "Failed to allocate %d rx intr_vec", >+ dev->data->nb_rx_queues); >+ return -1; >+ } >+ } >+ >+ if (!dev->data->dev_conf.intr_conf.rxq || >+ !rte_intr_dp_is_en(intr_handle)) { >+ /* Rx interrupt disabled, Map interrupt only for writeback */ >+ hw->nb_msix = 1; >+ if (hw->vf_res->vf_cap_flags & >+ VIRTCHNL_VF_OFFLOAD_WB_ON_ITR) { >+ /* If WB_ON_ITR supports, enable it */ >+ hw->msix_base = IAVF_RX_VEC_START; >+ IAVF_WRITE_REG(&hw->avf, >+ IAVF_VFINT_DYN_CTLN1(hw->msix_base - 1), >+ IAVF_VFINT_DYN_CTLN1_ITR_INDX_MASK | >+ IAVF_VFINT_DYN_CTLN1_WB_ON_ITR_MASK); >+ } else { >+ /* If no WB_ON_ITR offload flags, need to set >+ * interrupt for descriptor write back. >+ */ >+ hw->msix_base = IAVF_MISC_VEC_ID; >+ >+ /* set ITR to max */ >+ interval = >+ iavf_calc_itr_interval(IAVF_QUEUE_ITR_INTERVAL_MAX); >+ IAVF_WRITE_REG(&hw->avf, IAVF_VFINT_DYN_CTL01, >+ IAVF_VFINT_DYN_CTL01_INTENA_MASK | >+ (IAVF_ITR_INDEX_DEFAULT << >+ IAVF_VFINT_DYN_CTL01_ITR_INDX_SHIFT) | >+ (interval << >+ IAVF_VFINT_DYN_CTL01_INTERVAL_SHIFT)); >+ } >+ IAVF_WRITE_FLUSH(&hw->avf); >+ /* map all queues to the same interrupt */ >+ for (i = 0; i < dev->data->nb_rx_queues; i++) >+ hw->rxq_map[hw->msix_base] |= 1 << i; >+ } else { >+ if (!rte_intr_allow_others(intr_handle)) { >+ hw->nb_msix = 1; >+ hw->msix_base = IAVF_MISC_VEC_ID; >+ for (i = 0; i < dev->data->nb_rx_queues; i++) { >+ hw->rxq_map[hw->msix_base] |= 1 << i; >+ intr_handle->intr_vec[i] = IAVF_MISC_VEC_ID; >+ } >+ PMD_DRV_LOG(DEBUG, >+ "vector %u are mapping to all Rx queues", >+ hw->msix_base); >+ } else { >+ /* If Rx interrupt is reuquired, and we can use >+ * multi interrupts, then the vec is from 1 >+ */ >+ hw->nb_msix = RTE_MIN(hw->vf_res->max_vectors, >+ intr_handle->nb_efd); >+ hw->msix_base = IAVF_MISC_VEC_ID; >+ vec = IAVF_MISC_VEC_ID; >+ for (i = 0; i < dev->data->nb_rx_queues; i++) { >+ hw->rxq_map[vec] |= 1 << i; >+ intr_handle->intr_vec[i] = vec++; >+ if (vec >= hw->nb_msix) >+ vec = IAVF_RX_VEC_START; >+ } >+ PMD_DRV_LOG(DEBUG, >+ "%u vectors are mapping to %u Rx queues", >+ hw->nb_msix, dev->data->nb_rx_queues); >+ } >+ } >+ >+ if (ice_dcf_config_irq_map(hw)) { >+ PMD_DRV_LOG(ERR, "config interrupt mapping failed"); >+ return -1; Do we need to free intr_handle->intr_vec here? >+ } >+ return 0; >+} >+ > static int > ice_dcf_dev_start(struct rte_eth_dev *dev) > { > struct ice_dcf_adapter *dcf_ad = dev->data->dev_private; >+ struct rte_intr_handle *intr_handle = dev->intr_handle; > struct ice_adapter *ad = &dcf_ad->parent; > struct ice_dcf_hw *hw = &dcf_ad->real_hw; > int ret; >@@ -141,6 +254,18 @@ ice_dcf_dev_start(struct rte_eth_dev *dev) > } > } > >+ ret = ice_dcf_configure_queues(hw); >+ if (ret) { >+ PMD_DRV_LOG(ERR, "Fail to config queues"); >+ return ret; >+ } >+ >+ ret = ice_dcf_config_rx_queues_irqs(dev, intr_handle); >+ if (ret) { >+ PMD_DRV_LOG(ERR, "Fail to config rx queues' irqs"); >+ return ret; >+ } >+ > dev->data->dev_link.link_status = ETH_LINK_UP; > > return 0; >-- >2.17.1 >