From: Somnath Kotur <somnath.kotur@broadcom.com>
To: dev@dpdk.org
Cc: ferruh.yigit@intel.com
Subject: [dpdk-dev] [PATCH 45/50] net/bnxt: add support for vf rep and stat templates
Date: Fri, 12 Jun 2020 18:59:29 +0530 [thread overview]
Message-ID: <20200612132934.16488-46-somnath.kotur@broadcom.com> (raw)
In-Reply-To: <20200612132934.16488-1-somnath.kotur@broadcom.com>
From: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
The support for VF representor and counters is added to the
ulp templates.
Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
Reviewed-by: Somnath Kotur <somnath.kotur@broadcom.com>
Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com>
---
drivers/net/bnxt/tf_ulp/ulp_mapper.c | 21 +-
drivers/net/bnxt/tf_ulp/ulp_mapper.h | 2 +-
drivers/net/bnxt/tf_ulp/ulp_template_db_act.c | 424 +-
drivers/net/bnxt/tf_ulp/ulp_template_db_class.c | 5198 ++++++++++++++++++-----
drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h | 409 +-
drivers/net/bnxt/tf_ulp/ulp_template_db_field.h | 463 +-
drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c | 88 +-
7 files changed, 4948 insertions(+), 1657 deletions(-)
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.c b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
index b7b528b..9bf855f 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.c
@@ -22,7 +22,7 @@ ulp_mapper_glb_resource_info_list_get(uint32_t *num_entries)
{
if (!num_entries)
return NULL;
- *num_entries = BNXT_ULP_GLB_RESOURCE_INFO_TBL_MAX_SZ;
+ *num_entries = BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ;
return ulp_glb_resource_tbl;
}
@@ -119,11 +119,6 @@ ulp_mapper_resource_ident_allocate(struct bnxt_ulp_context *ulp_ctx,
tf_free_identifier(tfp, &fparms);
return rc;
}
-#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
- BNXT_TF_DBG(DEBUG, "Allocated Glb Res Ident [%s][%d][%d] = 0x%04x\n",
- (iparms.dir == TF_DIR_RX) ? "RX" : "TX",
- glb_res->glb_regfile_index, iparms.ident_type, iparms.id);
-#endif
return rc;
}
@@ -182,11 +177,6 @@ ulp_mapper_resource_index_tbl_alloc(struct bnxt_ulp_context *ulp_ctx,
tf_free_tbl_entry(tfp, &free_parms);
return rc;
}
-#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
- BNXT_TF_DBG(DEBUG, "Allocated Glb Res Index [%s][%d][%d] = 0x%04x\n",
- (aparms.dir == TF_DIR_RX) ? "RX" : "TX",
- glb_res->glb_regfile_index, aparms.type, aparms.idx);
-#endif
return rc;
}
@@ -1442,9 +1432,6 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms,
return rc;
}
}
-#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
- ulp_mapper_result_dump("EEM Result", tbl, &data);
-#endif
/* do the transpose for the internal EM keys */
if (tbl->resource_func == BNXT_ULP_RESOURCE_FUNC_INT_EM_TABLE)
@@ -1595,10 +1582,6 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
/* if encap bit swap is enabled perform the bit swap */
if (parms->device_params->encap_byte_swap && encap_flds) {
ulp_blob_perform_encap_swap(&data);
-#ifdef RTE_LIBRTE_BNXT_TRUFLOW_DEBUG
- BNXT_TF_DBG(INFO, "Dump after encap swap\n");
- ulp_mapper_blob_dump(&data);
-#endif
}
/*
@@ -2256,7 +2239,7 @@ ulp_mapper_glb_resource_info_deinit(struct bnxt_ulp_context *ulp_ctx,
/* Iterate the global resources and process each one */
for (dir = TF_DIR_RX; dir < TF_DIR_MAX; dir++) {
- for (idx = 0; idx < BNXT_ULP_GLB_RESOURCE_INFO_TBL_MAX_SZ;
+ for (idx = 0; idx < BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ;
idx++) {
ent = &mapper_data->glb_res_tbl[dir][idx];
if (ent->resource_func ==
diff --git a/drivers/net/bnxt/tf_ulp/ulp_mapper.h b/drivers/net/bnxt/tf_ulp/ulp_mapper.h
index f1399dc..54b9507 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_mapper.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_mapper.h
@@ -46,7 +46,7 @@ struct bnxt_ulp_mapper_glb_resource_entry {
struct bnxt_ulp_mapper_data {
struct bnxt_ulp_mapper_glb_resource_entry
- glb_res_tbl[TF_DIR_MAX][BNXT_ULP_GLB_RESOURCE_INFO_TBL_MAX_SZ];
+ glb_res_tbl[TF_DIR_MAX][BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ];
struct bnxt_ulp_mapper_cache_entry
*cache_tbl[BNXT_ULP_CACHE_TBL_MAX_SZ];
};
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c
index 9b14fa0..3d65073 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_act.c
@@ -9,70 +9,301 @@
#include "ulp_rte_parser.h"
uint16_t ulp_act_sig_tbl[BNXT_ULP_ACT_SIG_TBL_MAX_SZ] = {
- [BNXT_ULP_ACT_HID_00a1] = 1,
- [BNXT_ULP_ACT_HID_0029] = 2,
- [BNXT_ULP_ACT_HID_0040] = 3
+ [BNXT_ULP_ACT_HID_0002] = 1,
+ [BNXT_ULP_ACT_HID_0022] = 2,
+ [BNXT_ULP_ACT_HID_0026] = 3,
+ [BNXT_ULP_ACT_HID_0006] = 4,
+ [BNXT_ULP_ACT_HID_0009] = 5,
+ [BNXT_ULP_ACT_HID_0029] = 6,
+ [BNXT_ULP_ACT_HID_002d] = 7,
+ [BNXT_ULP_ACT_HID_004b] = 8,
+ [BNXT_ULP_ACT_HID_004a] = 9,
+ [BNXT_ULP_ACT_HID_004f] = 10,
+ [BNXT_ULP_ACT_HID_004e] = 11,
+ [BNXT_ULP_ACT_HID_006c] = 12,
+ [BNXT_ULP_ACT_HID_0070] = 13,
+ [BNXT_ULP_ACT_HID_0021] = 14,
+ [BNXT_ULP_ACT_HID_0025] = 15,
+ [BNXT_ULP_ACT_HID_0043] = 16,
+ [BNXT_ULP_ACT_HID_0042] = 17,
+ [BNXT_ULP_ACT_HID_0047] = 18,
+ [BNXT_ULP_ACT_HID_0046] = 19,
+ [BNXT_ULP_ACT_HID_0064] = 20,
+ [BNXT_ULP_ACT_HID_0068] = 21,
+ [BNXT_ULP_ACT_HID_00a1] = 22,
+ [BNXT_ULP_ACT_HID_00df] = 23
};
struct bnxt_ulp_act_match_info ulp_act_match_list[] = {
[1] = {
- .act_hid = BNXT_ULP_ACT_HID_00a1,
+ .act_hid = BNXT_ULP_ACT_HID_0002,
.act_sig = { .bits =
- BNXT_ULP_ACTION_BIT_VXLAN_DECAP |
- BNXT_ULP_ACTION_BIT_MARK |
- BNXT_ULP_ACTION_BIT_VNIC |
+ BNXT_ULP_ACTION_BIT_DROP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
- .act_tid = 0
+ .act_tid = 1
},
[2] = {
+ .act_hid = BNXT_ULP_ACT_HID_0022,
+ .act_sig = { .bits =
+ BNXT_ULP_ACTION_BIT_DROP |
+ BNXT_ULP_ACTION_BIT_VNIC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 1
+ },
+ [3] = {
+ .act_hid = BNXT_ULP_ACT_HID_0026,
+ .act_sig = { .bits =
+ BNXT_ULP_ACTION_BIT_DROP |
+ BNXT_ULP_ACTION_BIT_VNIC |
+ BNXT_ULP_ACTION_BIT_COUNT |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 1
+ },
+ [4] = {
+ .act_hid = BNXT_ULP_ACT_HID_0006,
+ .act_sig = { .bits =
+ BNXT_ULP_ACTION_BIT_DROP |
+ BNXT_ULP_ACTION_BIT_COUNT |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 1
+ },
+ [5] = {
+ .act_hid = BNXT_ULP_ACT_HID_0009,
+ .act_sig = { .bits =
+ BNXT_ULP_ACTION_BIT_MARK |
+ BNXT_ULP_ACTION_BIT_RSS |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 1
+ },
+ [6] = {
.act_hid = BNXT_ULP_ACT_HID_0029,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_MARK |
+ BNXT_ULP_ACTION_BIT_VNIC |
BNXT_ULP_ACTION_BIT_RSS |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 1
+ },
+ [7] = {
+ .act_hid = BNXT_ULP_ACT_HID_002d,
+ .act_sig = { .bits =
+ BNXT_ULP_ACTION_BIT_MARK |
BNXT_ULP_ACTION_BIT_VNIC |
+ BNXT_ULP_ACTION_BIT_RSS |
+ BNXT_ULP_ACTION_BIT_COUNT |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.act_tid = 1
},
- [3] = {
- .act_hid = BNXT_ULP_ACT_HID_0040,
+ [8] = {
+ .act_hid = BNXT_ULP_ACT_HID_004b,
+ .act_sig = { .bits =
+ BNXT_ULP_ACTION_BIT_MARK |
+ BNXT_ULP_ACTION_BIT_VNIC |
+ BNXT_ULP_ACTION_BIT_RSS |
+ BNXT_ULP_ACTION_BIT_POP_VLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 1
+ },
+ [9] = {
+ .act_hid = BNXT_ULP_ACT_HID_004a,
+ .act_sig = { .bits =
+ BNXT_ULP_ACTION_BIT_MARK |
+ BNXT_ULP_ACTION_BIT_VNIC |
+ BNXT_ULP_ACTION_BIT_RSS |
+ BNXT_ULP_ACTION_BIT_DEC_TTL |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 1
+ },
+ [10] = {
+ .act_hid = BNXT_ULP_ACT_HID_004f,
+ .act_sig = { .bits =
+ BNXT_ULP_ACTION_BIT_MARK |
+ BNXT_ULP_ACTION_BIT_VNIC |
+ BNXT_ULP_ACTION_BIT_RSS |
+ BNXT_ULP_ACTION_BIT_COUNT |
+ BNXT_ULP_ACTION_BIT_POP_VLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 1
+ },
+ [11] = {
+ .act_hid = BNXT_ULP_ACT_HID_004e,
+ .act_sig = { .bits =
+ BNXT_ULP_ACTION_BIT_MARK |
+ BNXT_ULP_ACTION_BIT_VNIC |
+ BNXT_ULP_ACTION_BIT_RSS |
+ BNXT_ULP_ACTION_BIT_COUNT |
+ BNXT_ULP_ACTION_BIT_DEC_TTL |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 1
+ },
+ [12] = {
+ .act_hid = BNXT_ULP_ACT_HID_006c,
+ .act_sig = { .bits =
+ BNXT_ULP_ACTION_BIT_MARK |
+ BNXT_ULP_ACTION_BIT_VNIC |
+ BNXT_ULP_ACTION_BIT_RSS |
+ BNXT_ULP_ACTION_BIT_POP_VLAN |
+ BNXT_ULP_ACTION_BIT_DEC_TTL |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 1
+ },
+ [13] = {
+ .act_hid = BNXT_ULP_ACT_HID_0070,
+ .act_sig = { .bits =
+ BNXT_ULP_ACTION_BIT_MARK |
+ BNXT_ULP_ACTION_BIT_VNIC |
+ BNXT_ULP_ACTION_BIT_RSS |
+ BNXT_ULP_ACTION_BIT_COUNT |
+ BNXT_ULP_ACTION_BIT_POP_VLAN |
+ BNXT_ULP_ACTION_BIT_DEC_TTL |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 1
+ },
+ [14] = {
+ .act_hid = BNXT_ULP_ACT_HID_0021,
+ .act_sig = { .bits =
+ BNXT_ULP_ACTION_BIT_MARK |
+ BNXT_ULP_ACTION_BIT_VNIC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 1
+ },
+ [15] = {
+ .act_hid = BNXT_ULP_ACT_HID_0025,
+ .act_sig = { .bits =
+ BNXT_ULP_ACTION_BIT_MARK |
+ BNXT_ULP_ACTION_BIT_VNIC |
+ BNXT_ULP_ACTION_BIT_COUNT |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 1
+ },
+ [16] = {
+ .act_hid = BNXT_ULP_ACT_HID_0043,
+ .act_sig = { .bits =
+ BNXT_ULP_ACTION_BIT_MARK |
+ BNXT_ULP_ACTION_BIT_VNIC |
+ BNXT_ULP_ACTION_BIT_POP_VLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 1
+ },
+ [17] = {
+ .act_hid = BNXT_ULP_ACT_HID_0042,
+ .act_sig = { .bits =
+ BNXT_ULP_ACTION_BIT_MARK |
+ BNXT_ULP_ACTION_BIT_VNIC |
+ BNXT_ULP_ACTION_BIT_DEC_TTL |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 1
+ },
+ [18] = {
+ .act_hid = BNXT_ULP_ACT_HID_0047,
+ .act_sig = { .bits =
+ BNXT_ULP_ACTION_BIT_MARK |
+ BNXT_ULP_ACTION_BIT_VNIC |
+ BNXT_ULP_ACTION_BIT_COUNT |
+ BNXT_ULP_ACTION_BIT_POP_VLAN |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 1
+ },
+ [19] = {
+ .act_hid = BNXT_ULP_ACT_HID_0046,
+ .act_sig = { .bits =
+ BNXT_ULP_ACTION_BIT_MARK |
+ BNXT_ULP_ACTION_BIT_VNIC |
+ BNXT_ULP_ACTION_BIT_COUNT |
+ BNXT_ULP_ACTION_BIT_DEC_TTL |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 1
+ },
+ [20] = {
+ .act_hid = BNXT_ULP_ACT_HID_0064,
+ .act_sig = { .bits =
+ BNXT_ULP_ACTION_BIT_MARK |
+ BNXT_ULP_ACTION_BIT_VNIC |
+ BNXT_ULP_ACTION_BIT_POP_VLAN |
+ BNXT_ULP_ACTION_BIT_DEC_TTL |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 1
+ },
+ [21] = {
+ .act_hid = BNXT_ULP_ACT_HID_0068,
+ .act_sig = { .bits =
+ BNXT_ULP_ACTION_BIT_MARK |
+ BNXT_ULP_ACTION_BIT_VNIC |
+ BNXT_ULP_ACTION_BIT_COUNT |
+ BNXT_ULP_ACTION_BIT_POP_VLAN |
+ BNXT_ULP_ACTION_BIT_DEC_TTL |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 1
+ },
+ [22] = {
+ .act_hid = BNXT_ULP_ACT_HID_00a1,
+ .act_sig = { .bits =
+ BNXT_ULP_ACTION_BIT_VXLAN_DECAP |
+ BNXT_ULP_ACTION_BIT_MARK |
+ BNXT_ULP_ACTION_BIT_VNIC |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ .act_tid = 2
+ },
+ [23] = {
+ .act_hid = BNXT_ULP_ACT_HID_00df,
.act_sig = { .bits =
BNXT_ULP_ACTION_BIT_VXLAN_ENCAP |
BNXT_ULP_ACTION_BIT_VPORT |
BNXT_ULP_FLOW_DIR_BITMASK_EGR },
- .act_tid = 2
+ .act_tid = 3
}
};
struct bnxt_ulp_mapper_tbl_list_info ulp_act_tmpl_list[] = {
- [((0 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
+ [((1 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .num_tbls = 1,
- .start_tbl_idx = 0
+ .num_tbls = 2,
+ .start_tbl_idx = 0,
+ .flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR
},
- [((1 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
+ [((2 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
.num_tbls = 1,
- .start_tbl_idx = 1
+ .start_tbl_idx = 2,
+ .flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR
},
- [((2 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
+ [((3 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
- .num_tbls = 1,
- .start_tbl_idx = 2
+ .num_tbls = 3,
+ .start_tbl_idx = 3,
+ .flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR
}
};
struct bnxt_ulp_mapper_tbl_info ulp_act_tbl_list[] = {
{
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_STATS_64,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT,
+ .cond_opcode = BNXT_ULP_COND_OPCODE_ACTION_BIT,
+ .cond_operand = BNXT_ULP_ACTION_BIT_COUNT,
+ .direction = TF_DIR_RX,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .result_start_idx = 0,
+ .result_bit_size = 64,
+ .result_num_fields = 1,
+ .encap_num_fields = 0,
+ .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
+ .index_operand = BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_EXT,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL,
.direction = TF_DIR_RX,
.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
- .result_start_idx = 0,
+ .result_start_idx = 1,
.result_bit_size = 128,
.result_num_fields = 26,
.encap_num_fields = 0,
@@ -87,7 +318,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_act_tbl_list[] = {
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL,
.direction = TF_DIR_RX,
.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
- .result_start_idx = 26,
+ .result_start_idx = 27,
.result_bit_size = 128,
.result_num_fields = 26,
.encap_num_fields = 0,
@@ -97,12 +328,46 @@ struct bnxt_ulp_mapper_tbl_info ulp_act_tbl_list[] = {
},
{
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL,
+ .cond_opcode = BNXT_ULP_COND_OPCODE_COMP_FIELD,
+ .cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV4_FLAG,
+ .direction = TF_DIR_TX,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .result_start_idx = 53,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 3,
+ .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
+ .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_SP_SMAC_IPV4,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL,
+ .cond_opcode = BNXT_ULP_COND_OPCODE_COMP_FIELD,
+ .cond_operand = BNXT_ULP_CF_IDX_ACT_ENCAP_IPV6_FLAG,
+ .direction = TF_DIR_TX,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .result_start_idx = 56,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 3,
+ .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
+ .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_EXT,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL,
.direction = TF_DIR_TX,
.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
- .result_start_idx = 52,
+ .result_start_idx = 59,
.result_bit_size = 128,
.result_num_fields = 26,
.encap_num_fields = 12,
@@ -114,10 +379,19 @@ struct bnxt_ulp_mapper_tbl_info ulp_act_tbl_list[] = {
struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = {
{
- .field_bit_size = 14,
+ .field_bit_size = 64,
.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
+ .field_bit_size = 14,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
.field_bit_size = 1,
.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
@@ -131,7 +405,17 @@ struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = {
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT,
+ .result_operand = {
+ ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACTION_BIT_COUNT >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACTION_BIT_COUNT & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
@@ -187,7 +471,17 @@ struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = {
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT,
+ .result_operand = {
+ ((uint64_t)BNXT_ULP_ACTION_BIT_DEC_TTL >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACTION_BIT_DEC_TTL >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACTION_BIT_DEC_TTL >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACTION_BIT_DEC_TTL >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACTION_BIT_DEC_TTL >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACTION_BIT_DEC_TTL >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACTION_BIT_DEC_TTL >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACTION_BIT_DEC_TTL & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
@@ -195,11 +489,7 @@ struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = {
},
{
.field_bit_size = 4,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .result_operand = {
- BNXT_ULP_SYM_DECAP_FUNC_THRU_TUN,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 12,
@@ -212,7 +502,17 @@ struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = {
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT,
+ .result_operand = {
+ ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACTION_BIT_POP_VLAN & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
@@ -224,7 +524,17 @@ struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = {
},
{
.field_bit_size = 1,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_BIT,
+ .result_operand = {
+ ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 56) & 0xff,
+ ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 48) & 0xff,
+ ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 40) & 0xff,
+ ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 32) & 0xff,
+ ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 24) & 0xff,
+ ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 16) & 0xff,
+ ((uint64_t)BNXT_ULP_ACTION_BIT_DROP >> 8) & 0xff,
+ (uint64_t)BNXT_ULP_ACTION_BIT_DROP & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 14,
@@ -308,7 +618,11 @@ struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = {
},
{
.field_bit_size = 4,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .result_operand = {
+ BNXT_ULP_SYM_DECAP_FUNC_THRU_TUN,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 12,
@@ -336,6 +650,50 @@ struct bnxt_ulp_mapper_result_field_info ulp_act_result_field_list[] = {
.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
+ .field_bit_size = 48,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP,
+ .result_operand = {
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 32,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP,
+ .result_operand = {
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 48,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 48,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP,
+ .result_operand = {
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_L2_SMAC & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 128,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ACT_PROP,
+ .result_operand = {
+ (BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC >> 8) & 0xff,
+ BNXT_ULP_ACT_PROP_IDX_ENCAP_IP_SRC & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
.field_bit_size = 14,
.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
index e51338d..fa7f793 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
@@ -10,8 +10,8 @@
uint16_t ulp_class_sig_tbl[BNXT_ULP_CLASS_SIG_TBL_MAX_SZ] = {
[BNXT_ULP_CLASS_HID_0080] = 1,
- [BNXT_ULP_CLASS_HID_0000] = 2,
- [BNXT_ULP_CLASS_HID_0087] = 3
+ [BNXT_ULP_CLASS_HID_0087] = 2,
+ [BNXT_ULP_CLASS_HID_0000] = 3
};
struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
@@ -23,1871 +23,4722 @@ struct bnxt_ulp_class_match_info ulp_class_match_list[] = {
BNXT_ULP_HDR_BIT_O_UDP |
BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF0_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF0_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF0_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF0_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF8_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF8_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF8_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF8_BITMASK_O_UDP_DST_PORT |
BNXT_ULP_MATCH_TYPE_BITMASK_EM },
- .class_tid = 0,
+ .class_tid = 8,
.act_vnic = 0,
.wc_pri = 0
},
[2] = {
- .class_hid = BNXT_ULP_CLASS_HID_0000,
+ .class_hid = BNXT_ULP_CLASS_HID_0087,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_HDR_BIT_O_UDP |
- BNXT_ULP_FLOW_DIR_BITMASK_EGR },
+ BNXT_ULP_HDR_BIT_T_VXLAN |
+ BNXT_ULP_HDR_BIT_I_ETH |
+ BNXT_ULP_HDR_BIT_I_IPV4 |
+ BNXT_ULP_HDR_BIT_I_UDP |
+ BNXT_ULP_FLOW_DIR_BITMASK_ING },
.field_sig = { .bits =
- BNXT_ULP_HF1_BITMASK_O_IPV4_SRC_ADDR |
- BNXT_ULP_HF1_BITMASK_O_IPV4_DST_ADDR |
- BNXT_ULP_HF1_BITMASK_O_UDP_SRC_PORT |
- BNXT_ULP_HF1_BITMASK_O_UDP_DST_PORT |
+ BNXT_ULP_HF9_BITMASK_I_IPV4_SRC_ADDR |
+ BNXT_ULP_HF9_BITMASK_I_IPV4_DST_ADDR |
+ BNXT_ULP_HF9_BITMASK_I_UDP_SRC_PORT |
+ BNXT_ULP_HF9_BITMASK_I_UDP_DST_PORT |
BNXT_ULP_MATCH_TYPE_BITMASK_EM },
- .class_tid = 1,
+ .class_tid = 9,
.act_vnic = 0,
.wc_pri = 0
},
[3] = {
- .class_hid = BNXT_ULP_CLASS_HID_0087,
+ .class_hid = BNXT_ULP_CLASS_HID_0000,
.hdr_sig = { .bits =
BNXT_ULP_HDR_BIT_O_ETH |
BNXT_ULP_HDR_BIT_O_IPV4 |
BNXT_ULP_HDR_BIT_O_UDP |
- BNXT_ULP_HDR_BIT_T_VXLAN |
- BNXT_ULP_HDR_BIT_I_ETH |
- BNXT_ULP_HDR_BIT_I_IPV4 |
- BNXT_ULP_HDR_BIT_I_UDP |
- BNXT_ULP_FLOW_DIR_BITMASK_ING },
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR },
.field_sig = { .bits =
- BNXT_ULP_HF2_BITMASK_I_IPV4_SRC_ADDR |
- BNXT_ULP_HF2_BITMASK_I_IPV4_DST_ADDR |
- BNXT_ULP_HF2_BITMASK_I_UDP_SRC_PORT |
- BNXT_ULP_HF2_BITMASK_I_UDP_DST_PORT |
+ BNXT_ULP_HF10_BITMASK_O_IPV4_SRC_ADDR |
+ BNXT_ULP_HF10_BITMASK_O_IPV4_DST_ADDR |
+ BNXT_ULP_HF10_BITMASK_O_UDP_SRC_PORT |
+ BNXT_ULP_HF10_BITMASK_O_UDP_DST_PORT |
BNXT_ULP_MATCH_TYPE_BITMASK_EM },
- .class_tid = 2,
+ .class_tid = 10,
.act_vnic = 0,
.wc_pri = 0
}
};
struct bnxt_ulp_mapper_tbl_list_info ulp_class_tmpl_list[] = {
- [((0 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
+ [((1 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
+ BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
+ .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .num_tbls = 4,
+ .start_tbl_idx = 0,
+ .flow_db_table_type = BNXT_ULP_FDB_TYPE_DEFAULT
+ },
+ [((2 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
+ BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
+ .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .num_tbls = 2,
+ .start_tbl_idx = 4,
+ .flow_db_table_type = BNXT_ULP_FDB_TYPE_DEFAULT
+ },
+ [((3 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
+ BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
+ .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .num_tbls = 6,
+ .start_tbl_idx = 6,
+ .flow_db_table_type = BNXT_ULP_FDB_TYPE_DEFAULT
+ },
+ [((4 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
.num_tbls = 5,
- .start_tbl_idx = 0
+ .start_tbl_idx = 12,
+ .flow_db_table_type = BNXT_ULP_FDB_TYPE_DEFAULT
},
- [((1 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
+ [((5 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
+ BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
+ .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .num_tbls = 3,
+ .start_tbl_idx = 17,
+ .flow_db_table_type = BNXT_ULP_FDB_TYPE_DEFAULT
+ },
+ [((6 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
+ BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
+ .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .num_tbls = 3,
+ .start_tbl_idx = 20,
+ .flow_db_table_type = BNXT_ULP_FDB_TYPE_DEFAULT
+ },
+ [((7 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
+ BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
+ .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .num_tbls = 1,
+ .start_tbl_idx = 23,
+ .flow_db_table_type = BNXT_ULP_FDB_TYPE_DEFAULT
+ },
+ [((8 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
.num_tbls = 5,
- .start_tbl_idx = 5
+ .start_tbl_idx = 24,
+ .flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR
},
- [((2 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
+ [((9 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
+ BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
+ .device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
+ .num_tbls = 5,
+ .start_tbl_idx = 29,
+ .flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR
+ },
+ [((10 << BNXT_ULP_LOG2_MAX_NUM_DEV) |
BNXT_ULP_DEVICE_ID_WH_PLUS)] = {
.device_name = BNXT_ULP_DEVICE_ID_WH_PLUS,
.num_tbls = 5,
- .start_tbl_idx = 10
+ .start_tbl_idx = 34,
+ .flow_db_table_type = BNXT_ULP_FDB_TYPE_REGULAR
}
};
struct bnxt_ulp_mapper_tbl_info ulp_class_tbl_list[] = {
{
- .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM,
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL,
.direction = TF_DIR_RX,
- .priority = BNXT_ULP_PRIORITY_NOT_USED,
- .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
- .key_start_idx = 0,
- .blob_key_bit_size = 12,
- .key_bit_size = 12,
- .key_num_fields = 2,
.result_start_idx = 0,
- .result_bit_size = 10,
- .result_num_fields = 1,
+ .result_bit_size = 128,
+ .result_num_fields = 26,
.encap_num_fields = 0,
- .ident_start_idx = 0,
- .ident_nums = 1,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
- .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
+ .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
+ .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
},
{
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED,
.direction = TF_DIR_RX,
.priority = BNXT_ULP_PRIORITY_LEVEL_0,
.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
- .key_start_idx = 2,
+ .key_start_idx = 0,
.blob_key_bit_size = 167,
.key_bit_size = 167,
.key_num_fields = 13,
- .result_start_idx = 1,
+ .result_start_idx = 26,
.result_bit_size = 64,
.result_num_fields = 13,
.encap_num_fields = 0,
- .ident_start_idx = 1,
+ .ident_start_idx = 0,
.ident_nums = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
},
{
- .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
.direction = TF_DIR_RX,
- .priority = BNXT_ULP_PRIORITY_NOT_USED,
- .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
- .key_start_idx = 15,
- .blob_key_bit_size = 16,
- .key_bit_size = 16,
- .key_num_fields = 3,
- .result_start_idx = 14,
- .result_bit_size = 10,
+ .result_start_idx = 39,
+ .result_bit_size = 32,
.result_num_fields = 1,
.encap_num_fields = 0,
- .ident_start_idx = 1,
- .ident_nums = 1,
+ .index_opcode = BNXT_ULP_INDEX_OPCODE_COMP_FIELD,
+ .index_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
+ .direction = TF_DIR_RX,
+ .result_start_idx = 40,
+ .result_bit_size = 32,
+ .result_num_fields = 1,
+ .encap_num_fields = 0,
+ .index_opcode = BNXT_ULP_INDEX_OPCODE_COMP_FIELD,
+ .index_operand = BNXT_ULP_CF_IDX_PHY_PORT_PARIF
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_VFR_CFA_ACTION,
+ .direction = TF_DIR_TX,
+ .result_start_idx = 41,
+ .result_bit_size = 128,
+ .result_num_fields = 26,
+ .encap_num_fields = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
- .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
+ .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
+ .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
},
{
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED,
- .direction = TF_DIR_RX,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM,
+ .direction = TF_DIR_TX,
.priority = BNXT_ULP_PRIORITY_LEVEL_0,
.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
- .key_start_idx = 18,
- .blob_key_bit_size = 81,
- .key_bit_size = 81,
- .key_num_fields = 42,
- .result_start_idx = 15,
- .result_bit_size = 38,
- .result_num_fields = 8,
+ .key_start_idx = 13,
+ .blob_key_bit_size = 167,
+ .key_bit_size = 167,
+ .key_num_fields = 13,
+ .result_start_idx = 67,
+ .result_bit_size = 64,
+ .result_num_fields = 13,
.encap_num_fields = 0,
- .ident_start_idx = 2,
+ .ident_start_idx = 0,
.ident_nums = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
},
{
- .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE,
- .resource_type = TF_MEM_EXTERNAL,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED,
- .direction = TF_DIR_RX,
- .priority = BNXT_ULP_PRIORITY_NOT_USED,
- .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
- .key_start_idx = 60,
- .blob_key_bit_size = 448,
- .key_bit_size = 448,
- .key_num_fields = 11,
- .result_start_idx = 23,
- .result_bit_size = 64,
- .result_num_fields = 9,
- .encap_num_fields = 0,
- .ident_start_idx = 2,
- .ident_nums = 0,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION,
- .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL,
+ .direction = TF_DIR_TX,
+ .result_start_idx = 80,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 12,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
+ .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
+ .index_operand = BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0
},
{
- .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM,
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_VFR_CFA_ACTION,
.direction = TF_DIR_TX,
- .priority = BNXT_ULP_PRIORITY_NOT_USED,
- .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
- .key_start_idx = 71,
- .blob_key_bit_size = 12,
- .key_bit_size = 12,
- .key_num_fields = 2,
- .result_start_idx = 32,
- .result_bit_size = 10,
- .result_num_fields = 1,
+ .result_start_idx = 92,
+ .result_bit_size = 128,
+ .result_num_fields = 26,
.encap_num_fields = 0,
- .ident_start_idx = 2,
- .ident_nums = 1,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
- .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
+ .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
+ .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
},
{
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED,
.direction = TF_DIR_TX,
.priority = BNXT_ULP_PRIORITY_LEVEL_0,
.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
- .key_start_idx = 73,
+ .key_start_idx = 26,
.blob_key_bit_size = 167,
.key_bit_size = 167,
.key_num_fields = 13,
- .result_start_idx = 33,
+ .result_start_idx = 118,
.result_bit_size = 64,
.result_num_fields = 13,
.encap_num_fields = 0,
- .ident_start_idx = 3,
+ .ident_start_idx = 0,
.ident_nums = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
},
{
- .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
- .direction = TF_DIR_TX,
- .priority = BNXT_ULP_PRIORITY_NOT_USED,
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL,
+ .direction = TF_DIR_RX,
+ .result_start_idx = 131,
+ .result_bit_size = 128,
+ .result_num_fields = 26,
+ .encap_num_fields = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
+ .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
+ .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM,
+ .direction = TF_DIR_RX,
+ .priority = BNXT_ULP_PRIORITY_LEVEL_0,
.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
- .key_start_idx = 86,
- .blob_key_bit_size = 16,
- .key_bit_size = 16,
- .key_num_fields = 3,
- .result_start_idx = 46,
- .result_bit_size = 10,
- .result_num_fields = 1,
+ .key_start_idx = 39,
+ .blob_key_bit_size = 167,
+ .key_bit_size = 167,
+ .key_num_fields = 13,
+ .result_start_idx = 157,
+ .result_bit_size = 64,
+ .result_num_fields = 13,
.encap_num_fields = 0,
- .ident_start_idx = 3,
- .ident_nums = 1,
+ .ident_start_idx = 0,
+ .ident_nums = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
},
{
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED,
- .direction = TF_DIR_TX,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM,
+ .direction = TF_DIR_RX,
.priority = BNXT_ULP_PRIORITY_LEVEL_0,
.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
- .key_start_idx = 89,
- .blob_key_bit_size = 81,
- .key_bit_size = 81,
- .key_num_fields = 42,
- .result_start_idx = 47,
- .result_bit_size = 38,
- .result_num_fields = 8,
+ .key_start_idx = 52,
+ .blob_key_bit_size = 167,
+ .key_bit_size = 167,
+ .key_num_fields = 13,
+ .result_start_idx = 170,
+ .result_bit_size = 64,
+ .result_num_fields = 13,
.encap_num_fields = 0,
- .ident_start_idx = 4,
+ .ident_start_idx = 0,
.ident_nums = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
},
{
- .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE,
- .resource_type = TF_MEM_EXTERNAL,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM,
.direction = TF_DIR_TX,
- .priority = BNXT_ULP_PRIORITY_NOT_USED,
+ .priority = BNXT_ULP_PRIORITY_LEVEL_0,
.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
- .key_start_idx = 131,
- .blob_key_bit_size = 448,
- .key_bit_size = 448,
- .key_num_fields = 11,
- .result_start_idx = 55,
+ .key_start_idx = 65,
+ .blob_key_bit_size = 167,
+ .key_bit_size = 167,
+ .key_num_fields = 13,
+ .result_start_idx = 183,
.result_bit_size = 64,
- .result_num_fields = 9,
+ .result_num_fields = 13,
.encap_num_fields = 0,
- .ident_start_idx = 4,
+ .ident_start_idx = 0,
.ident_nums = 0,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION,
- .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
},
{
- .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_DFLT_ACT_REC_PTR,
+ .direction = TF_DIR_TX,
+ .result_start_idx = 196,
+ .result_bit_size = 32,
+ .result_num_fields = 1,
+ .encap_num_fields = 0,
+ .index_opcode = BNXT_ULP_INDEX_OPCODE_COMP_FIELD,
+ .index_operand = BNXT_ULP_CF_IDX_VF_FUNC_PARIF
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IF_TABLE,
+ .resource_type = TF_IF_TBL_TYPE_PROF_PARIF_ERR_ACT_REC_PTR,
+ .direction = TF_DIR_TX,
+ .result_start_idx = 197,
+ .result_bit_size = 32,
+ .result_num_fields = 1,
+ .encap_num_fields = 0,
+ .index_opcode = BNXT_ULP_INDEX_OPCODE_COMP_FIELD,
+ .index_operand = BNXT_ULP_CF_IDX_VF_FUNC_PARIF
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM,
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL,
.direction = TF_DIR_RX,
- .priority = BNXT_ULP_PRIORITY_NOT_USED,
- .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
- .key_start_idx = 142,
- .blob_key_bit_size = 12,
- .key_bit_size = 12,
- .key_num_fields = 2,
- .result_start_idx = 64,
- .result_bit_size = 10,
- .result_num_fields = 1,
+ .result_start_idx = 198,
+ .result_bit_size = 128,
+ .result_num_fields = 26,
.encap_num_fields = 0,
- .ident_start_idx = 4,
- .ident_nums = 1,
- .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
- .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_VFR_FLAG,
+ .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
+ .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
},
{
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
.resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED,
.direction = TF_DIR_RX,
.priority = BNXT_ULP_PRIORITY_LEVEL_0,
.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
- .key_start_idx = 144,
+ .key_start_idx = 78,
.blob_key_bit_size = 167,
.key_bit_size = 167,
.key_num_fields = 13,
- .result_start_idx = 65,
+ .result_start_idx = 224,
.result_bit_size = 64,
.result_num_fields = 13,
.encap_num_fields = 0,
- .ident_start_idx = 5,
+ .ident_start_idx = 0,
.ident_nums = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
},
{
- .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
- .direction = TF_DIR_RX,
- .priority = BNXT_ULP_PRIORITY_NOT_USED,
- .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
- .key_start_idx = 157,
- .blob_key_bit_size = 16,
- .key_bit_size = 16,
- .key_num_fields = 3,
- .result_start_idx = 78,
- .result_bit_size = 10,
- .result_num_fields = 1,
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL,
+ .direction = TF_DIR_TX,
+ .result_start_idx = 237,
+ .result_bit_size = 0,
+ .result_num_fields = 0,
+ .encap_num_fields = 12,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
+ .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
+ .index_operand = BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL,
+ .direction = TF_DIR_TX,
+ .result_start_idx = 249,
+ .result_bit_size = 128,
+ .result_num_fields = 26,
.encap_num_fields = 0,
- .ident_start_idx = 5,
- .ident_nums = 1,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
- .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
+ .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
+ .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
},
{
.resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
- .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
- .resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED,
- .direction = TF_DIR_RX,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM,
+ .direction = TF_DIR_TX,
.priority = BNXT_ULP_PRIORITY_LEVEL_0,
.srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
- .key_start_idx = 160,
- .blob_key_bit_size = 81,
- .key_bit_size = 81,
- .key_num_fields = 42,
- .result_start_idx = 79,
- .result_bit_size = 38,
- .result_num_fields = 8,
+ .key_start_idx = 91,
+ .blob_key_bit_size = 167,
+ .key_bit_size = 167,
+ .key_num_fields = 13,
+ .result_start_idx = 275,
+ .result_bit_size = 64,
+ .result_num_fields = 13,
.encap_num_fields = 0,
- .ident_start_idx = 6,
+ .ident_start_idx = 0,
.ident_nums = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
},
{
- .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE,
- .resource_type = TF_MEM_EXTERNAL,
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.resource_sub_type =
- BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED,
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL,
.direction = TF_DIR_RX,
- .priority = BNXT_ULP_PRIORITY_NOT_USED,
- .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
- .key_start_idx = 202,
- .blob_key_bit_size = 448,
- .key_bit_size = 448,
- .key_num_fields = 11,
- .result_start_idx = 87,
- .result_bit_size = 64,
+ .result_start_idx = 288,
+ .result_bit_size = 128,
+ .result_num_fields = 26,
+ .encap_num_fields = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
+ .index_opcode = BNXT_ULP_INDEX_OPCODE_ALLOCATE,
+ .index_operand = BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM,
+ .direction = TF_DIR_RX,
+ .priority = BNXT_ULP_PRIORITY_LEVEL_0,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 104,
+ .blob_key_bit_size = 167,
+ .key_bit_size = 167,
+ .key_num_fields = 13,
+ .result_start_idx = 314,
+ .result_bit_size = 64,
+ .result_num_fields = 13,
+ .encap_num_fields = 0,
+ .ident_start_idx = 0,
+ .ident_nums = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM,
+ .direction = TF_DIR_RX,
+ .priority = BNXT_ULP_PRIORITY_LEVEL_0,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 117,
+ .blob_key_bit_size = 167,
+ .key_bit_size = 167,
+ .key_num_fields = 13,
+ .result_start_idx = 327,
+ .result_bit_size = 64,
+ .result_num_fields = 13,
+ .encap_num_fields = 0,
+ .ident_start_idx = 0,
+ .ident_nums = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_VFR_CFA_ACTION,
+ .direction = TF_DIR_TX,
+ .result_start_idx = 340,
+ .result_bit_size = 128,
+ .result_num_fields = 26,
+ .encap_num_fields = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
+ .index_opcode = BNXT_ULP_INDEX_OPCODE_GLOBAL,
+ .index_operand = BNXT_ULP_GLB_REGFILE_INDEX_GLB_LB_AREC_PTR
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_RX,
+ .key_start_idx = 130,
+ .blob_key_bit_size = 12,
+ .key_bit_size = 12,
+ .key_num_fields = 2,
+ .result_start_idx = 366,
+ .result_bit_size = 10,
+ .result_num_fields = 1,
+ .encap_num_fields = 0,
+ .ident_start_idx = 0,
+ .ident_nums = 1
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM,
+ .direction = TF_DIR_RX,
+ .priority = BNXT_ULP_PRIORITY_LEVEL_0,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 132,
+ .blob_key_bit_size = 167,
+ .key_bit_size = 167,
+ .key_num_fields = 13,
+ .result_start_idx = 367,
+ .result_bit_size = 64,
+ .result_num_fields = 13,
+ .encap_num_fields = 0,
+ .ident_start_idx = 1,
+ .ident_nums = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
+ .direction = TF_DIR_RX,
+ .key_start_idx = 145,
+ .blob_key_bit_size = 16,
+ .key_bit_size = 16,
+ .key_num_fields = 3,
+ .result_start_idx = 380,
+ .result_bit_size = 10,
+ .result_num_fields = 1,
+ .encap_num_fields = 0,
+ .ident_start_idx = 1,
+ .ident_nums = 1
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .direction = TF_DIR_RX,
+ .priority = BNXT_ULP_PRIORITY_LEVEL_0,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 148,
+ .blob_key_bit_size = 81,
+ .key_bit_size = 81,
+ .key_num_fields = 42,
+ .result_start_idx = 381,
+ .result_bit_size = 38,
+ .result_num_fields = 8,
+ .encap_num_fields = 0,
+ .ident_start_idx = 2,
+ .ident_nums = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE,
+ .resource_type = TF_MEM_EXTERNAL,
+ .direction = TF_DIR_RX,
+ .key_start_idx = 190,
+ .blob_key_bit_size = 448,
+ .key_bit_size = 448,
+ .key_num_fields = 11,
+ .result_start_idx = 389,
+ .result_bit_size = 64,
.result_num_fields = 9,
.encap_num_fields = 0,
- .ident_start_idx = 6,
+ .ident_start_idx = 2,
.ident_nums = 0,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION,
.critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
- }
-};
-
-struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_RX,
+ .key_start_idx = 201,
+ .blob_key_bit_size = 12,
+ .key_bit_size = 12,
+ .key_num_fields = 2,
+ .result_start_idx = 398,
+ .result_bit_size = 10,
+ .result_num_fields = 1,
+ .encap_num_fields = 0,
+ .ident_start_idx = 2,
+ .ident_nums = 1
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM,
+ .direction = TF_DIR_RX,
+ .priority = BNXT_ULP_PRIORITY_LEVEL_0,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 203,
+ .blob_key_bit_size = 167,
+ .key_bit_size = 167,
+ .key_num_fields = 13,
+ .result_start_idx = 399,
+ .result_bit_size = 64,
+ .result_num_fields = 13,
+ .encap_num_fields = 0,
+ .ident_start_idx = 3,
+ .ident_nums = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
+ .direction = TF_DIR_RX,
+ .key_start_idx = 216,
+ .blob_key_bit_size = 16,
+ .key_bit_size = 16,
+ .key_num_fields = 3,
+ .result_start_idx = 412,
+ .result_bit_size = 10,
+ .result_num_fields = 1,
+ .encap_num_fields = 0,
+ .ident_start_idx = 3,
+ .ident_nums = 1
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .direction = TF_DIR_RX,
+ .priority = BNXT_ULP_PRIORITY_LEVEL_0,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 219,
+ .blob_key_bit_size = 81,
+ .key_bit_size = 81,
+ .key_num_fields = 42,
+ .result_start_idx = 413,
+ .result_bit_size = 38,
+ .result_num_fields = 8,
+ .encap_num_fields = 0,
+ .ident_start_idx = 4,
+ .ident_nums = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE,
+ .resource_type = TF_MEM_EXTERNAL,
+ .direction = TF_DIR_RX,
+ .key_start_idx = 261,
+ .blob_key_bit_size = 448,
+ .key_bit_size = 448,
+ .key_num_fields = 11,
+ .result_start_idx = 421,
+ .result_bit_size = 64,
+ .result_num_fields = 9,
+ .encap_num_fields = 0,
+ .ident_start_idx = 4,
+ .ident_nums = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .key_start_idx = 272,
+ .blob_key_bit_size = 12,
+ .key_bit_size = 12,
+ .key_num_fields = 2,
+ .result_start_idx = 430,
+ .result_bit_size = 10,
+ .result_num_fields = 1,
+ .encap_num_fields = 0,
+ .ident_start_idx = 4,
+ .ident_nums = 1
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_L2_CTXT_TCAM,
+ .direction = TF_DIR_TX,
+ .priority = BNXT_ULP_PRIORITY_LEVEL_0,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 274,
+ .blob_key_bit_size = 167,
+ .key_bit_size = 167,
+ .key_num_fields = 13,
+ .result_start_idx = 431,
+ .result_bit_size = 64,
+ .result_num_fields = 13,
+ .encap_num_fields = 0,
+ .ident_start_idx = 5,
+ .ident_nums = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_CACHE_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .resource_sub_type =
+ BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM,
+ .direction = TF_DIR_TX,
+ .key_start_idx = 287,
+ .blob_key_bit_size = 16,
+ .key_bit_size = 16,
+ .key_num_fields = 3,
+ .result_start_idx = 444,
+ .result_bit_size = 10,
+ .result_num_fields = 1,
+ .encap_num_fields = 0,
+ .ident_start_idx = 5,
+ .ident_nums = 1
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_TCAM_TABLE,
+ .resource_type = TF_TCAM_TBL_TYPE_PROF_TCAM,
+ .direction = TF_DIR_TX,
+ .priority = BNXT_ULP_PRIORITY_LEVEL_0,
+ .srch_b4_alloc = BNXT_ULP_SEARCH_BEFORE_ALLOC_NO,
+ .key_start_idx = 290,
+ .blob_key_bit_size = 81,
+ .key_bit_size = 81,
+ .key_num_fields = 42,
+ .result_start_idx = 445,
+ .result_bit_size = 38,
+ .result_num_fields = 8,
+ .encap_num_fields = 0,
+ .ident_start_idx = 6,
+ .ident_nums = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_NOP,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_NO
+ },
+ {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_EXT_EM_TABLE,
+ .resource_type = TF_MEM_EXTERNAL,
+ .direction = TF_DIR_TX,
+ .key_start_idx = 332,
+ .blob_key_bit_size = 448,
+ .key_bit_size = 448,
+ .key_num_fields = 11,
+ .result_start_idx = 453,
+ .result_bit_size = 64,
+ .result_num_fields = 9,
+ .encap_num_fields = 0,
+ .ident_start_idx = 6,
+ .ident_nums = 0,
+ .mark_db_opcode = BNXT_ULP_MARK_DB_OPCODE_SET_IF_MARK_ACTION,
+ .critical_resource = BNXT_ULP_CRITICAL_RESOURCE_YES
+ }
+};
+
+struct bnxt_ulp_mapper_class_key_field_info ulp_class_key_field_list[] = {
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_SVIF & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_TYPE_NONE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_TYPE_NONE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_CF_IDX_VF_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_VF_FUNC_SVIF & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_TYPE_NONE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x01, 0x02}
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_TYPE_NONE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x01, 0x02}
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_SVIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_SVIF & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_TYPE_NONE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF8_IDX_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_HF8_IDX_SVIF_INDEX & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_TYPE_NONE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+ .mask_operand = {
+ (BNXT_ULP_HF8_IDX_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_HF8_IDX_SVIF_INDEX & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF8_IDX_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_HF8_IDX_SVIF_INDEX & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_TYPE_NONE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 7,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L4_HDR_TYPE_UDP,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L4_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 3,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 9,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 7,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 251,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 3,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 16,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF8_IDX_O_UDP_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_HF8_IDX_O_UDP_DST_PORT & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF8_IDX_O_UDP_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_HF8_IDX_O_UDP_SRC_PORT & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_IP_PROTO_UDP,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 32,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF8_IDX_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_HF8_IDX_O_IPV4_DST_ADDR & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 32,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF8_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_HF8_IDX_O_IPV4_SRC_ADDR & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 24,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 10,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF9_IDX_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_HF9_IDX_SVIF_INDEX & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_TYPE_NONE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+ .mask_operand = {
+ (BNXT_ULP_HF9_IDX_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_HF9_IDX_SVIF_INDEX & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF9_IDX_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_HF9_IDX_SVIF_INDEX & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 7,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L4_HDR_TYPE_UDP,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L4_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 3,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL4_HDR_TYPE_UDP,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL4_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL3_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TL2_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 9,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 7,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 251,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 3,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 16,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF9_IDX_I_UDP_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_HF9_IDX_I_UDP_DST_PORT & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF9_IDX_I_UDP_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_HF9_IDX_I_UDP_SRC_PORT & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_IP_PROTO_UDP,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 32,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF9_IDX_I_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_HF9_IDX_I_IPV4_DST_ADDR & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 32,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF9_IDX_I_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_HF9_IDX_I_IPV4_SRC_ADDR & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 24,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 10,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF10_IDX_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_HF10_IDX_SVIF_INDEX & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_TYPE_NONE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+ .mask_operand = {
+ (BNXT_ULP_HF10_IDX_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_HF10_IDX_SVIF_INDEX & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF10_IDX_SVIF_INDEX >> 8) & 0xff,
+ BNXT_ULP_HF10_IDX_SVIF_INDEX & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 12,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_TUN_HDR_TYPE_NONE,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 7,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L4_HDR_TYPE_UDP,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L4_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L3_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_L2_HDR_VALID_YES,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 3,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 9,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 7,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 2,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 4,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 251,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 3,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 16,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF10_IDX_O_UDP_DST_PORT >> 8) & 0xff,
+ BNXT_ULP_HF10_IDX_O_UDP_DST_PORT & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF10_IDX_O_UDP_SRC_PORT >> 8) & 0xff,
+ BNXT_ULP_HF10_IDX_O_UDP_SRC_PORT & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .spec_operand = {
+ BNXT_ULP_SYM_IP_PROTO_UDP,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 32,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF10_IDX_O_IPV4_DST_ADDR >> 8) & 0xff,
+ BNXT_ULP_HF10_IDX_O_IPV4_DST_ADDR & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 32,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
+ .spec_operand = {
+ (BNXT_ULP_HF10_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff,
+ BNXT_ULP_HF10_IDX_O_IPV4_SRC_ADDR & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 48,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 24,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 10,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
+ .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+ .spec_operand = {
+ (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ }
+};
+
+struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
+ {
+ .field_bit_size = 14,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 8,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 11,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 4,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 12,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD,
+ .result_operand = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_GLB_REGFILE_INDEX_GLB_L2_CNTXT_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_REGFILE_INDEX_GLB_L2_CNTXT_ID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 7,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 4,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD,
+ .result_operand = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_PARIF >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_PARIF & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 8,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 6,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 32,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 32,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 14,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 8,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 11,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 4,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 12,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD,
+ .result_operand = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_VPORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_VPORT & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 8,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 6,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 4,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .result_operand = {
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x81, 0x00}
+ },
+ {
+ .field_bit_size = 12,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD,
+ .result_operand = {
+ (BNXT_ULP_CF_IDX_DEV_PORT_ID >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DEV_PORT_ID & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 80,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 14,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 8,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 11,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
{
- .field_bit_size = 8,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
- .spec_operand = {
- (BNXT_ULP_HF0_IDX_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_HF0_IDX_SVIF_INDEX & 0xff,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TUN_HDR_TYPE_NONE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 12,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 12,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 48,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 8,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
- .mask_operand = {
- (BNXT_ULP_HF0_IDX_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_HF0_IDX_SVIF_INDEX & 0xff,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
- .spec_operand = {
- (BNXT_ULP_HF0_IDX_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_HF0_IDX_SVIF_INDEX & 0xff,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 12,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .result_operand = {
+ (BNXT_ULP_SYM_WH_PLUS_LOOPBACK_PORT >> 8) & 0xff,
+ BNXT_ULP_SYM_WH_PLUS_LOOPBACK_PORT & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
- .field_bit_size = 12,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 48,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TUN_HDR_TYPE_NONE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
- .field_bit_size = 7,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
- .spec_operand = {
- (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .field_bit_size = 4,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 8,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
- .spec_operand = {
- (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff,
- BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 6,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
- .field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_L4_HDR_TYPE_UDP,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 14,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_L4_HDR_VALID_YES,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 8,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_L3_HDR_VALID_YES,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 11,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_L2_HDR_VALID_YES,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 3,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 12,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD,
+ .result_operand = {
+ (BNXT_ULP_CF_IDX_VF_FUNC_VNIC >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_VF_FUNC_VNIC & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 8,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 6,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
- .field_bit_size = 9,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 4,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 7,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
- .spec_operand = {
- (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .field_bit_size = 8,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 6,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
- .field_bit_size = 251,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 3,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 16,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
- .spec_operand = {
- (BNXT_ULP_HF0_IDX_O_UDP_DST_PORT >> 8) & 0xff,
- BNXT_ULP_HF0_IDX_O_UDP_DST_PORT & 0xff,
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_GLB_REGFILE_INDEX_GLB_L2_CNTXT_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_REGFILE_INDEX_GLB_L2_CNTXT_ID & 0xff,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
- .field_bit_size = 16,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
- .spec_operand = {
- (BNXT_ULP_HF0_IDX_O_UDP_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_HF0_IDX_O_UDP_SRC_PORT & 0xff,
+ .field_bit_size = 7,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
+ BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 4,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
.field_bit_size = 8,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_IP_PROTO_UDP,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 32,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
- .spec_operand = {
- (BNXT_ULP_HF0_IDX_O_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_HF0_IDX_O_IPV4_DST_ADDR & 0xff,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 32,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
- .spec_operand = {
- (BNXT_ULP_HF0_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_HF0_IDX_O_IPV4_SRC_ADDR & 0xff,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .field_bit_size = 6,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 48,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 24,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 10,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
- .spec_operand = {
- (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 8,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
- .spec_operand = {
- (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
+ .field_bit_size = 32,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_GLB_REGFILE_INDEX_GLB_LB_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_GLB_REGFILE_INDEX_GLB_LB_AREC_PTR & 0xff,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
- .field_bit_size = 8,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
- .spec_operand = {
- (BNXT_ULP_HF1_IDX_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_HF1_IDX_SVIF_INDEX & 0xff,
+ .field_bit_size = 32,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_GLB_REGFILE_INDEX_GLB_LB_AREC_PTR >> 8) & 0xff,
+ BNXT_ULP_GLB_REGFILE_INDEX_GLB_LB_AREC_PTR & 0xff,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
- .field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TUN_HDR_TYPE_NONE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .field_bit_size = 14,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 12,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 12,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 48,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 8,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
- .mask_operand = {
- (BNXT_ULP_HF1_IDX_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_HF1_IDX_SVIF_INDEX & 0xff,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
- .spec_operand = {
- (BNXT_ULP_HF1_IDX_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_HF1_IDX_SVIF_INDEX & 0xff,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 12,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 12,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 11,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 48,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TUN_HDR_TYPE_NONE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 7,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
- .spec_operand = {
- (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 8,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
- .spec_operand = {
- (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff,
- BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff,
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 4,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 12,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD,
+ .result_operand = {
+ (BNXT_ULP_CF_IDX_DRV_FUNC_VNIC >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_DRV_FUNC_VNIC & 0xff,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_L4_HDR_TYPE_UDP,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_L4_HDR_VALID_YES,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 8,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 6,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_L3_HDR_VALID_YES,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 4,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .result_operand = {
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
- .field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x81, 0x00}
},
{
- .field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 12,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x02}
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_L2_HDR_VALID_YES,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 3,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 80,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 14,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 8,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 11,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_0 & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
- .field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 9,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 4,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 7,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
- .spec_operand = {
- (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
+ .field_bit_size = 12,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD,
+ .result_operand = {
+ (BNXT_ULP_CF_IDX_PHY_PORT_VPORT >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_PHY_PORT_VPORT & 0xff,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 251,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 3,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 16,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
- .spec_operand = {
- (BNXT_ULP_HF1_IDX_O_UDP_DST_PORT >> 8) & 0xff,
- BNXT_ULP_HF1_IDX_O_UDP_DST_PORT & 0xff,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
- .field_bit_size = 16,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
- .spec_operand = {
- (BNXT_ULP_HF1_IDX_O_UDP_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_HF1_IDX_O_UDP_SRC_PORT & 0xff,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 4,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 8,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_IP_PROTO_UDP,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 32,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
- .spec_operand = {
- (BNXT_ULP_HF1_IDX_O_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_HF1_IDX_O_IPV4_DST_ADDR & 0xff,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 32,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
- .spec_operand = {
- (BNXT_ULP_HF1_IDX_O_IPV4_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_HF1_IDX_O_IPV4_SRC_ADDR & 0xff,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .field_bit_size = 6,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 48,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 24,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 10,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
- .spec_operand = {
- (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 8,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
- .spec_operand = {
- (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 8,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
- .spec_operand = {
- (BNXT_ULP_HF2_IDX_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_HF2_IDX_SVIF_INDEX & 0xff,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .field_bit_size = 14,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TUN_HDR_TYPE_NONE,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 12,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 12,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 48,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 8,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
- .mask_operand = {
- (BNXT_ULP_HF2_IDX_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_HF2_IDX_SVIF_INDEX & 0xff,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
- .spec_operand = {
- (BNXT_ULP_HF2_IDX_SVIF_INDEX >> 8) & 0xff,
- BNXT_ULP_HF2_IDX_SVIF_INDEX & 0xff,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 12,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 12,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 11,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 48,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 7,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
- .spec_operand = {
- (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 8,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
- .spec_operand = {
- (BNXT_ULP_REGFILE_INDEX_CLASS_TID >> 8) & 0xff,
- BNXT_ULP_REGFILE_INDEX_CLASS_TID & 0xff,
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 4,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 12,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_COMP_FIELD,
+ .result_operand = {
+ (BNXT_ULP_CF_IDX_VF_FUNC_VNIC >> 8) & 0xff,
+ BNXT_ULP_CF_IDX_VF_FUNC_VNIC & 0xff,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
- .field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_L4_HDR_TYPE_UDP,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_L4_HDR_VALID_YES,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 8,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_L3_HDR_VALID_YES,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 6,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
+ {
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_MAIN_ACTION_PTR & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_L2_HDR_VALID_YES,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 3,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
- .field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 4,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 8,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TUN_HDR_VALID_YES,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 6,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TL4_HDR_TYPE_UDP,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .field_bit_size = 3,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TL4_HDR_VALID_YES,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .result_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
- .field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 14,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TL3_HDR_VALID_YES,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 8,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_TL2_HDR_VALID_YES,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 11,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 9,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 7,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_GLB_REGFILE,
- .spec_operand = {
- (BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID >> 8) & 0xff,
- BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID & 0xff,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 2,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 16,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 4,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 10,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
.field_bit_size = 1,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .mask_operand = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
- 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff},
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 251,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 3,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 16,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
- .spec_operand = {
- (BNXT_ULP_HF2_IDX_I_UDP_DST_PORT >> 8) & 0xff,
- BNXT_ULP_HF2_IDX_I_UDP_DST_PORT & 0xff,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 16,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
- .spec_operand = {
- (BNXT_ULP_HF2_IDX_I_UDP_SRC_PORT >> 8) & 0xff,
- BNXT_ULP_HF2_IDX_I_UDP_SRC_PORT & 0xff,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .field_bit_size = 4,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 8,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
- .spec_operand = {
- BNXT_ULP_SYM_IP_PROTO_UDP,
+ .field_bit_size = 12,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_CONSTANT,
+ .result_operand = {
+ (BNXT_ULP_SYM_WH_PLUS_LOOPBACK_PORT >> 8) & 0xff,
+ BNXT_ULP_SYM_WH_PLUS_LOOPBACK_PORT & 0xff,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
- .field_bit_size = 32,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
- .spec_operand = {
- (BNXT_ULP_HF2_IDX_I_IPV4_DST_ADDR >> 8) & 0xff,
- BNXT_ULP_HF2_IDX_I_IPV4_DST_ADDR & 0xff,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 32,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_HDR_FIELD,
- .spec_operand = {
- (BNXT_ULP_HF2_IDX_I_IPV4_SRC_ADDR >> 8) & 0xff,
- BNXT_ULP_HF2_IDX_I_IPV4_SRC_ADDR & 0xff,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 48,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 2,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 24,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 10,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
- .spec_operand = {
- (BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 >> 8) & 0xff,
- BNXT_ULP_REGFILE_INDEX_L2_CNTXT_ID_0 & 0xff,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
},
{
- .field_bit_size = 8,
- .mask_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO,
- .spec_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
- .spec_operand = {
- (BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 >> 8) & 0xff,
- BNXT_ULP_REGFILE_INDEX_EM_PROFILE_ID_0 & 0xff,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
- }
-};
-
-struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
+ .field_bit_size = 1,
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ },
{
.field_bit_size = 10,
.result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
@@ -2309,7 +5160,12 @@ struct bnxt_ulp_mapper_result_field_info ulp_class_result_field_list[] = {
},
{
.field_bit_size = 16,
- .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_ZERO
+ .result_opcode = BNXT_ULP_MAPPER_OPC_SET_TO_REGFILE,
+ .result_operand = {
+ (BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR >> 8) & 0xff,
+ BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR & 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
},
{
.field_bit_size = 1,
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
index 2346797..6955464 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
@@ -6,7 +6,7 @@
#ifndef ULP_TEMPLATE_DB_H_
#define ULP_TEMPLATE_DB_H_
-#define BNXT_ULP_REGFILE_MAX_SZ 16
+#define BNXT_ULP_REGFILE_MAX_SZ 17
#define BNXT_ULP_MAX_NUM_DEVICES 4
#define BNXT_ULP_LOG2_MAX_NUM_DEV 2
#define BNXT_ULP_CACHE_TBL_MAX_SZ 4
@@ -18,15 +18,15 @@
#define BNXT_ULP_CLASS_HID_SHFTL 23
#define BNXT_ULP_CLASS_HID_MASK 255
#define BNXT_ULP_ACT_SIG_TBL_MAX_SZ 256
-#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 4
+#define BNXT_ULP_ACT_MATCH_LIST_MAX_SZ 24
#define BNXT_ULP_ACT_HID_LOW_PRIME 7919
#define BNXT_ULP_ACT_HID_HIGH_PRIME 7919
-#define BNXT_ULP_ACT_HID_SHFTR 0
+#define BNXT_ULP_ACT_HID_SHFTR 23
#define BNXT_ULP_ACT_HID_SHFTL 23
#define BNXT_ULP_ACT_HID_MASK 255
#define BNXT_ULP_CACHE_TBL_IDENT_MAX_NUM 2
-#define BNXT_ULP_GLB_RESOURCE_INFO_TBL_MAX_SZ 3
-#define BNXT_ULP_GLB_TEMPLATE_TBL_MAX_SZ 0
+#define BNXT_ULP_GLB_RESOURCE_TBL_MAX_SZ 5
+#define BNXT_ULP_GLB_TEMPLATE_TBL_MAX_SZ 1
enum bnxt_ulp_action_bit {
BNXT_ULP_ACTION_BIT_MARK = 0x0000000000000001,
@@ -242,7 +242,8 @@ enum bnxt_ulp_regfile_index {
BNXT_ULP_REGFILE_INDEX_ENCAP_PTR_1 = 13,
BNXT_ULP_REGFILE_INDEX_CRITICAL_RESOURCE = 14,
BNXT_ULP_REGFILE_INDEX_FLOW_CNTR_PTR_0 = 15,
- BNXT_ULP_REGFILE_INDEX_LAST = 16
+ BNXT_ULP_REGFILE_INDEX_MAIN_SP_PTR = 16,
+ BNXT_ULP_REGFILE_INDEX_LAST = 17
};
enum bnxt_ulp_search_before_alloc {
@@ -252,18 +253,18 @@ enum bnxt_ulp_search_before_alloc {
};
enum bnxt_ulp_fdb_resource_flags {
- BNXT_ULP_FDB_RESOURCE_FLAGS_DIR_EGR = 0x01,
- BNXT_ULP_FDB_RESOURCE_FLAGS_DIR_INGR = 0x00
+ BNXT_ULP_FDB_RESOURCE_FLAGS_DIR_INGR = 0x00,
+ BNXT_ULP_FDB_RESOURCE_FLAGS_DIR_EGR = 0x01
};
enum bnxt_ulp_fdb_type {
- BNXT_ULP_FDB_TYPE_DEFAULT = 1,
- BNXT_ULP_FDB_TYPE_REGULAR = 0
+ BNXT_ULP_FDB_TYPE_REGULAR = 0,
+ BNXT_ULP_FDB_TYPE_DEFAULT = 1
};
enum bnxt_ulp_flow_dir_bitmask {
- BNXT_ULP_FLOW_DIR_BITMASK_EGR = 0x8000000000000000,
- BNXT_ULP_FLOW_DIR_BITMASK_ING = 0x0000000000000000
+ BNXT_ULP_FLOW_DIR_BITMASK_ING = 0x0000000000000000,
+ BNXT_ULP_FLOW_DIR_BITMASK_EGR = 0x8000000000000000
};
enum bnxt_ulp_match_type_bitmask {
@@ -285,190 +286,66 @@ enum bnxt_ulp_resource_func {
};
enum bnxt_ulp_resource_sub_type {
- BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM = 0,
- BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM = 1,
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_EXT_COUNT = 3,
- BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT = 2,
+ BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED = 0,
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_NORMAL = 0,
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_VFR_CFA_ACTION = 1,
- BNXT_ULP_RESOURCE_SUB_TYPE_NOT_USED = 0
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_INT_COUNT = 2,
+ BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TYPE_EXT_COUNT = 3,
+ BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM = 0,
+ BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM = 1
};
enum bnxt_ulp_sym {
- BNXT_ULP_SYM_ACT_REC_DROP_NO = 0,
- BNXT_ULP_SYM_ACT_REC_DROP_YES = 1,
- BNXT_ULP_SYM_ACT_REC_METER_EN_NO = 0,
- BNXT_ULP_SYM_ACT_REC_METER_EN_YES = 1,
- BNXT_ULP_SYM_ACT_REC_POP_VLAN_NO = 0,
- BNXT_ULP_SYM_ACT_REC_POP_VLAN_YES = 1,
- BNXT_ULP_SYM_AGG_ERROR_IGNORE = 0,
- BNXT_ULP_SYM_AGG_ERROR_NO = 0,
- BNXT_ULP_SYM_AGG_ERROR_YES = 1,
- BNXT_ULP_SYM_DECAP_FUNC_NONE = 0,
- BNXT_ULP_SYM_DECAP_FUNC_THRU_L2 = 11,
- BNXT_ULP_SYM_DECAP_FUNC_THRU_L3 = 12,
- BNXT_ULP_SYM_DECAP_FUNC_THRU_L4 = 13,
- BNXT_ULP_SYM_DECAP_FUNC_THRU_TL2 = 3,
- BNXT_ULP_SYM_DECAP_FUNC_THRU_TL3 = 8,
- BNXT_ULP_SYM_DECAP_FUNC_THRU_TL4 = 9,
- BNXT_ULP_SYM_DECAP_FUNC_THRU_TUN = 10,
- BNXT_ULP_SYM_ECV_CUSTOM_EN_NO = 0,
- BNXT_ULP_SYM_ECV_CUSTOM_EN_YES = 1,
- BNXT_ULP_SYM_ECV_L2_EN_NO = 0,
- BNXT_ULP_SYM_ECV_L2_EN_YES = 1,
- BNXT_ULP_SYM_ECV_L3_TYPE_IPV4 = 4,
- BNXT_ULP_SYM_ECV_L3_TYPE_IPV6 = 5,
- BNXT_ULP_SYM_ECV_L3_TYPE_MPLS_8847 = 6,
- BNXT_ULP_SYM_ECV_L3_TYPE_MPLS_8848 = 7,
- BNXT_ULP_SYM_ECV_L3_TYPE_NONE = 0,
- BNXT_ULP_SYM_ECV_L4_TYPE_NONE = 0,
- BNXT_ULP_SYM_ECV_L4_TYPE_UDP = 4,
- BNXT_ULP_SYM_ECV_L4_TYPE_UDP_CSUM = 5,
- BNXT_ULP_SYM_ECV_L4_TYPE_UDP_ENTROPY = 6,
- BNXT_ULP_SYM_ECV_L4_TYPE_UDP_ENTROPY_CSUM = 7,
- BNXT_ULP_SYM_ECV_TUN_TYPE_GENERIC = 1,
- BNXT_ULP_SYM_ECV_TUN_TYPE_GRE = 5,
- BNXT_ULP_SYM_ECV_TUN_TYPE_NGE = 3,
- BNXT_ULP_SYM_ECV_TUN_TYPE_NONE = 0,
- BNXT_ULP_SYM_ECV_TUN_TYPE_NVGRE = 4,
- BNXT_ULP_SYM_ECV_TUN_TYPE_VXLAN = 2,
- BNXT_ULP_SYM_ECV_VALID_NO = 0,
- BNXT_ULP_SYM_ECV_VALID_YES = 1,
- BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_ENCAP_PRI = 6,
- BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_0 = 8,
- BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_1 = 8,
- BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_2 = 8,
- BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_3 = 8,
- BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_4 = 8,
- BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_5 = 8,
- BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_6 = 8,
- BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_7 = 8,
- BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_REMAP_DIFFSERV = 7,
- BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI = 1,
- BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_IVLAN_PRI = 2,
- BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_REMAP_DIFFSERV = 3,
- BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_2_ENCAP_PRI = 4,
- BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_2_REMAP_DIFFSERV = 5,
- BNXT_ULP_SYM_ECV_VTAG_TYPE_NOP = 0,
- BNXT_ULP_SYM_HREC_NEXT_IGNORE = 0,
- BNXT_ULP_SYM_HREC_NEXT_NO = 0,
- BNXT_ULP_SYM_HREC_NEXT_YES = 1,
- BNXT_ULP_SYM_IP_PROTO_ICMP = 1,
- BNXT_ULP_SYM_IP_PROTO_IGMP = 2,
- BNXT_ULP_SYM_IP_PROTO_IP_IN_IP = 4,
- BNXT_ULP_SYM_IP_PROTO_TCP = 6,
- BNXT_ULP_SYM_IP_PROTO_UDP = 17,
- BNXT_ULP_SYM_L2_HDR_ERROR_IGNORE = 0,
- BNXT_ULP_SYM_L2_HDR_ERROR_NO = 0,
- BNXT_ULP_SYM_L2_HDR_ERROR_YES = 1,
- BNXT_ULP_SYM_L2_HDR_TYPE_DIX = 0,
- BNXT_ULP_SYM_L2_HDR_TYPE_IGNORE = 0,
- BNXT_ULP_SYM_L2_HDR_TYPE_LLC = 2,
- BNXT_ULP_SYM_L2_HDR_TYPE_LLC_SNAP = 1,
- BNXT_ULP_SYM_L2_HDR_VALID_IGNORE = 0,
- BNXT_ULP_SYM_L2_HDR_VALID_NO = 0,
- BNXT_ULP_SYM_L2_HDR_VALID_YES = 1,
- BNXT_ULP_SYM_L2_TWO_VTAGS_IGNORE = 0,
- BNXT_ULP_SYM_L2_TWO_VTAGS_NO = 0,
- BNXT_ULP_SYM_L2_TWO_VTAGS_YES = 1,
- BNXT_ULP_SYM_L2_UC_MC_BC_BC = 3,
- BNXT_ULP_SYM_L2_UC_MC_BC_IGNORE = 0,
- BNXT_ULP_SYM_L2_UC_MC_BC_MC = 2,
- BNXT_ULP_SYM_L2_UC_MC_BC_UC = 0,
- BNXT_ULP_SYM_L2_VTAG_PRESENT_IGNORE = 0,
- BNXT_ULP_SYM_L2_VTAG_PRESENT_NO = 0,
- BNXT_ULP_SYM_L2_VTAG_PRESENT_YES = 1,
- BNXT_ULP_SYM_L3_HDR_ERROR_IGNORE = 0,
- BNXT_ULP_SYM_L3_HDR_ERROR_NO = 0,
- BNXT_ULP_SYM_L3_HDR_ERROR_YES = 1,
- BNXT_ULP_SYM_L3_HDR_ISIP_IGNORE = 0,
- BNXT_ULP_SYM_L3_HDR_ISIP_NO = 0,
- BNXT_ULP_SYM_L3_HDR_ISIP_YES = 1,
- BNXT_ULP_SYM_L3_HDR_TYPE_ARP = 2,
- BNXT_ULP_SYM_L3_HDR_TYPE_EAPOL = 4,
- BNXT_ULP_SYM_L3_HDR_TYPE_FCOE = 6,
- BNXT_ULP_SYM_L3_HDR_TYPE_IGNORE = 0,
- BNXT_ULP_SYM_L3_HDR_TYPE_IPV4 = 0,
- BNXT_ULP_SYM_L3_HDR_TYPE_IPV6 = 1,
- BNXT_ULP_SYM_L3_HDR_TYPE_PTP = 3,
- BNXT_ULP_SYM_L3_HDR_TYPE_ROCE = 5,
- BNXT_ULP_SYM_L3_HDR_TYPE_UPAR1 = 7,
- BNXT_ULP_SYM_L3_HDR_TYPE_UPAR2 = 8,
- BNXT_ULP_SYM_L3_HDR_VALID_IGNORE = 0,
- BNXT_ULP_SYM_L3_HDR_VALID_NO = 0,
- BNXT_ULP_SYM_L3_HDR_VALID_YES = 1,
- BNXT_ULP_SYM_L3_IPV6_CMP_DST_IGNORE = 0,
- BNXT_ULP_SYM_L3_IPV6_CMP_DST_NO = 0,
- BNXT_ULP_SYM_L3_IPV6_CMP_DST_YES = 1,
- BNXT_ULP_SYM_L3_IPV6_CMP_SRC_IGNORE = 0,
- BNXT_ULP_SYM_L3_IPV6_CMP_SRC_NO = 0,
- BNXT_ULP_SYM_L3_IPV6_CMP_SRC_YES = 1,
- BNXT_ULP_SYM_L4_HDR_ERROR_IGNORE = 0,
- BNXT_ULP_SYM_L4_HDR_ERROR_NO = 0,
- BNXT_ULP_SYM_L4_HDR_ERROR_YES = 1,
- BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_IGNORE = 0,
- BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_NO = 0,
- BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_YES = 1,
- BNXT_ULP_SYM_L4_HDR_TYPE_BTH_V1 = 5,
- BNXT_ULP_SYM_L4_HDR_TYPE_ICMP = 2,
- BNXT_ULP_SYM_L4_HDR_TYPE_IGNORE = 0,
- BNXT_ULP_SYM_L4_HDR_TYPE_TCP = 0,
- BNXT_ULP_SYM_L4_HDR_TYPE_UDP = 1,
- BNXT_ULP_SYM_L4_HDR_TYPE_UPAR1 = 3,
- BNXT_ULP_SYM_L4_HDR_TYPE_UPAR2 = 4,
- BNXT_ULP_SYM_L4_HDR_VALID_IGNORE = 0,
- BNXT_ULP_SYM_L4_HDR_VALID_NO = 0,
- BNXT_ULP_SYM_L4_HDR_VALID_YES = 1,
- BNXT_ULP_SYM_MATCH_TYPE_EM = 0,
- BNXT_ULP_SYM_MATCH_TYPE_WM = 1,
- BNXT_ULP_SYM_NO = 0,
BNXT_ULP_SYM_PKT_TYPE_IGNORE = 0,
BNXT_ULP_SYM_PKT_TYPE_L2 = 0,
- BNXT_ULP_SYM_POP_VLAN_NO = 0,
- BNXT_ULP_SYM_POP_VLAN_YES = 1,
BNXT_ULP_SYM_RECYCLE_CNT_IGNORE = 0,
+ BNXT_ULP_SYM_RECYCLE_CNT_ZERO = 0,
BNXT_ULP_SYM_RECYCLE_CNT_ONE = 1,
- BNXT_ULP_SYM_RECYCLE_CNT_THREE = 3,
BNXT_ULP_SYM_RECYCLE_CNT_TWO = 2,
- BNXT_ULP_SYM_RECYCLE_CNT_ZERO = 0,
+ BNXT_ULP_SYM_RECYCLE_CNT_THREE = 3,
+ BNXT_ULP_SYM_AGG_ERROR_IGNORE = 0,
+ BNXT_ULP_SYM_AGG_ERROR_NO = 0,
+ BNXT_ULP_SYM_AGG_ERROR_YES = 1,
BNXT_ULP_SYM_RESERVED_IGNORE = 0,
- BNXT_ULP_SYM_STINGRAY_EXT_EM_MAX_KEY_SIZE = 448,
- BNXT_ULP_SYM_STINGRAY_LOOPBACK_PORT = 16,
- BNXT_ULP_SYM_STINGRAY2_LOOPBACK_PORT = 3,
- BNXT_ULP_SYM_THOR_LOOPBACK_PORT = 3,
- BNXT_ULP_SYM_TL2_HDR_TYPE_DIX = 0,
- BNXT_ULP_SYM_TL2_HDR_TYPE_IGNORE = 0,
+ BNXT_ULP_SYM_HREC_NEXT_IGNORE = 0,
+ BNXT_ULP_SYM_HREC_NEXT_NO = 0,
+ BNXT_ULP_SYM_HREC_NEXT_YES = 1,
BNXT_ULP_SYM_TL2_HDR_VALID_IGNORE = 0,
BNXT_ULP_SYM_TL2_HDR_VALID_NO = 0,
BNXT_ULP_SYM_TL2_HDR_VALID_YES = 1,
- BNXT_ULP_SYM_TL2_TWO_VTAGS_IGNORE = 0,
- BNXT_ULP_SYM_TL2_TWO_VTAGS_NO = 0,
- BNXT_ULP_SYM_TL2_TWO_VTAGS_YES = 1,
- BNXT_ULP_SYM_TL2_UC_MC_BC_BC = 3,
+ BNXT_ULP_SYM_TL2_HDR_TYPE_IGNORE = 0,
+ BNXT_ULP_SYM_TL2_HDR_TYPE_DIX = 0,
BNXT_ULP_SYM_TL2_UC_MC_BC_IGNORE = 0,
- BNXT_ULP_SYM_TL2_UC_MC_BC_MC = 2,
BNXT_ULP_SYM_TL2_UC_MC_BC_UC = 0,
+ BNXT_ULP_SYM_TL2_UC_MC_BC_MC = 2,
+ BNXT_ULP_SYM_TL2_UC_MC_BC_BC = 3,
BNXT_ULP_SYM_TL2_VTAG_PRESENT_IGNORE = 0,
BNXT_ULP_SYM_TL2_VTAG_PRESENT_NO = 0,
BNXT_ULP_SYM_TL2_VTAG_PRESENT_YES = 1,
+ BNXT_ULP_SYM_TL2_TWO_VTAGS_IGNORE = 0,
+ BNXT_ULP_SYM_TL2_TWO_VTAGS_NO = 0,
+ BNXT_ULP_SYM_TL2_TWO_VTAGS_YES = 1,
+ BNXT_ULP_SYM_TL3_HDR_VALID_IGNORE = 0,
+ BNXT_ULP_SYM_TL3_HDR_VALID_NO = 0,
+ BNXT_ULP_SYM_TL3_HDR_VALID_YES = 1,
BNXT_ULP_SYM_TL3_HDR_ERROR_IGNORE = 0,
BNXT_ULP_SYM_TL3_HDR_ERROR_NO = 0,
BNXT_ULP_SYM_TL3_HDR_ERROR_YES = 1,
- BNXT_ULP_SYM_TL3_HDR_ISIP_IGNORE = 0,
- BNXT_ULP_SYM_TL3_HDR_ISIP_NO = 0,
- BNXT_ULP_SYM_TL3_HDR_ISIP_YES = 1,
BNXT_ULP_SYM_TL3_HDR_TYPE_IGNORE = 0,
BNXT_ULP_SYM_TL3_HDR_TYPE_IPV4 = 0,
BNXT_ULP_SYM_TL3_HDR_TYPE_IPV6 = 1,
- BNXT_ULP_SYM_TL3_HDR_VALID_IGNORE = 0,
- BNXT_ULP_SYM_TL3_HDR_VALID_NO = 0,
- BNXT_ULP_SYM_TL3_HDR_VALID_YES = 1,
- BNXT_ULP_SYM_TL3_IPV6_CMP_DST_IGNORE = 0,
- BNXT_ULP_SYM_TL3_IPV6_CMP_DST_NO = 0,
- BNXT_ULP_SYM_TL3_IPV6_CMP_DST_YES = 1,
+ BNXT_ULP_SYM_TL3_HDR_ISIP_IGNORE = 0,
+ BNXT_ULP_SYM_TL3_HDR_ISIP_NO = 0,
+ BNXT_ULP_SYM_TL3_HDR_ISIP_YES = 1,
BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_IGNORE = 0,
BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_NO = 0,
BNXT_ULP_SYM_TL3_IPV6_CMP_SRC_YES = 1,
+ BNXT_ULP_SYM_TL3_IPV6_CMP_DST_IGNORE = 0,
+ BNXT_ULP_SYM_TL3_IPV6_CMP_DST_NO = 0,
+ BNXT_ULP_SYM_TL3_IPV6_CMP_DST_YES = 1,
+ BNXT_ULP_SYM_TL4_HDR_VALID_IGNORE = 0,
+ BNXT_ULP_SYM_TL4_HDR_VALID_NO = 0,
+ BNXT_ULP_SYM_TL4_HDR_VALID_YES = 1,
BNXT_ULP_SYM_TL4_HDR_ERROR_IGNORE = 0,
BNXT_ULP_SYM_TL4_HDR_ERROR_NO = 0,
BNXT_ULP_SYM_TL4_HDR_ERROR_YES = 1,
@@ -478,40 +355,164 @@ enum bnxt_ulp_sym {
BNXT_ULP_SYM_TL4_HDR_TYPE_IGNORE = 0,
BNXT_ULP_SYM_TL4_HDR_TYPE_TCP = 0,
BNXT_ULP_SYM_TL4_HDR_TYPE_UDP = 1,
- BNXT_ULP_SYM_TL4_HDR_VALID_IGNORE = 0,
- BNXT_ULP_SYM_TL4_HDR_VALID_NO = 0,
- BNXT_ULP_SYM_TL4_HDR_VALID_YES = 1,
+ BNXT_ULP_SYM_TUN_HDR_VALID_IGNORE = 0,
+ BNXT_ULP_SYM_TUN_HDR_VALID_NO = 0,
+ BNXT_ULP_SYM_TUN_HDR_VALID_YES = 1,
BNXT_ULP_SYM_TUN_HDR_ERROR_IGNORE = 0,
BNXT_ULP_SYM_TUN_HDR_ERROR_NO = 0,
BNXT_ULP_SYM_TUN_HDR_ERROR_YES = 1,
- BNXT_ULP_SYM_TUN_HDR_FLAGS_IGNORE = 0,
+ BNXT_ULP_SYM_TUN_HDR_TYPE_IGNORE = 0,
+ BNXT_ULP_SYM_TUN_HDR_TYPE_VXLAN = 0,
BNXT_ULP_SYM_TUN_HDR_TYPE_GENEVE = 1,
+ BNXT_ULP_SYM_TUN_HDR_TYPE_NVGRE = 2,
BNXT_ULP_SYM_TUN_HDR_TYPE_GRE = 3,
- BNXT_ULP_SYM_TUN_HDR_TYPE_IGNORE = 0,
BNXT_ULP_SYM_TUN_HDR_TYPE_IPV4 = 4,
BNXT_ULP_SYM_TUN_HDR_TYPE_IPV6 = 5,
- BNXT_ULP_SYM_TUN_HDR_TYPE_MPLS = 7,
- BNXT_ULP_SYM_TUN_HDR_TYPE_NONE = 15,
- BNXT_ULP_SYM_TUN_HDR_TYPE_NVGRE = 2,
BNXT_ULP_SYM_TUN_HDR_TYPE_PPPOE = 6,
+ BNXT_ULP_SYM_TUN_HDR_TYPE_MPLS = 7,
BNXT_ULP_SYM_TUN_HDR_TYPE_UPAR1 = 8,
BNXT_ULP_SYM_TUN_HDR_TYPE_UPAR2 = 9,
- BNXT_ULP_SYM_TUN_HDR_TYPE_VXLAN = 0,
- BNXT_ULP_SYM_TUN_HDR_VALID_IGNORE = 0,
- BNXT_ULP_SYM_TUN_HDR_VALID_NO = 0,
- BNXT_ULP_SYM_TUN_HDR_VALID_YES = 1,
- BNXT_ULP_SYM_WH_PLUS_EXT_ACT_REC = 0,
- BNXT_ULP_SYM_WH_PLUS_EXT_EM_MAX_KEY_SIZE = 448,
+ BNXT_ULP_SYM_TUN_HDR_TYPE_NONE = 15,
+ BNXT_ULP_SYM_TUN_HDR_FLAGS_IGNORE = 0,
+ BNXT_ULP_SYM_L2_HDR_VALID_IGNORE = 0,
+ BNXT_ULP_SYM_L2_HDR_VALID_NO = 0,
+ BNXT_ULP_SYM_L2_HDR_VALID_YES = 1,
+ BNXT_ULP_SYM_L2_HDR_ERROR_IGNORE = 0,
+ BNXT_ULP_SYM_L2_HDR_ERROR_NO = 0,
+ BNXT_ULP_SYM_L2_HDR_ERROR_YES = 1,
+ BNXT_ULP_SYM_L2_HDR_TYPE_IGNORE = 0,
+ BNXT_ULP_SYM_L2_HDR_TYPE_DIX = 0,
+ BNXT_ULP_SYM_L2_HDR_TYPE_LLC_SNAP = 1,
+ BNXT_ULP_SYM_L2_HDR_TYPE_LLC = 2,
+ BNXT_ULP_SYM_L2_UC_MC_BC_IGNORE = 0,
+ BNXT_ULP_SYM_L2_UC_MC_BC_UC = 0,
+ BNXT_ULP_SYM_L2_UC_MC_BC_MC = 2,
+ BNXT_ULP_SYM_L2_UC_MC_BC_BC = 3,
+ BNXT_ULP_SYM_L2_VTAG_PRESENT_IGNORE = 0,
+ BNXT_ULP_SYM_L2_VTAG_PRESENT_NO = 0,
+ BNXT_ULP_SYM_L2_VTAG_PRESENT_YES = 1,
+ BNXT_ULP_SYM_L2_TWO_VTAGS_IGNORE = 0,
+ BNXT_ULP_SYM_L2_TWO_VTAGS_NO = 0,
+ BNXT_ULP_SYM_L2_TWO_VTAGS_YES = 1,
+ BNXT_ULP_SYM_L3_HDR_VALID_IGNORE = 0,
+ BNXT_ULP_SYM_L3_HDR_VALID_NO = 0,
+ BNXT_ULP_SYM_L3_HDR_VALID_YES = 1,
+ BNXT_ULP_SYM_L3_HDR_ERROR_IGNORE = 0,
+ BNXT_ULP_SYM_L3_HDR_ERROR_NO = 0,
+ BNXT_ULP_SYM_L3_HDR_ERROR_YES = 1,
+ BNXT_ULP_SYM_L3_HDR_TYPE_IGNORE = 0,
+ BNXT_ULP_SYM_L3_HDR_TYPE_IPV4 = 0,
+ BNXT_ULP_SYM_L3_HDR_TYPE_IPV6 = 1,
+ BNXT_ULP_SYM_L3_HDR_TYPE_ARP = 2,
+ BNXT_ULP_SYM_L3_HDR_TYPE_PTP = 3,
+ BNXT_ULP_SYM_L3_HDR_TYPE_EAPOL = 4,
+ BNXT_ULP_SYM_L3_HDR_TYPE_ROCE = 5,
+ BNXT_ULP_SYM_L3_HDR_TYPE_FCOE = 6,
+ BNXT_ULP_SYM_L3_HDR_TYPE_UPAR1 = 7,
+ BNXT_ULP_SYM_L3_HDR_TYPE_UPAR2 = 8,
+ BNXT_ULP_SYM_L3_HDR_ISIP_IGNORE = 0,
+ BNXT_ULP_SYM_L3_HDR_ISIP_NO = 0,
+ BNXT_ULP_SYM_L3_HDR_ISIP_YES = 1,
+ BNXT_ULP_SYM_L3_IPV6_CMP_SRC_IGNORE = 0,
+ BNXT_ULP_SYM_L3_IPV6_CMP_SRC_NO = 0,
+ BNXT_ULP_SYM_L3_IPV6_CMP_SRC_YES = 1,
+ BNXT_ULP_SYM_L3_IPV6_CMP_DST_IGNORE = 0,
+ BNXT_ULP_SYM_L3_IPV6_CMP_DST_NO = 0,
+ BNXT_ULP_SYM_L3_IPV6_CMP_DST_YES = 1,
+ BNXT_ULP_SYM_L4_HDR_VALID_IGNORE = 0,
+ BNXT_ULP_SYM_L4_HDR_VALID_NO = 0,
+ BNXT_ULP_SYM_L4_HDR_VALID_YES = 1,
+ BNXT_ULP_SYM_L4_HDR_ERROR_IGNORE = 0,
+ BNXT_ULP_SYM_L4_HDR_ERROR_NO = 0,
+ BNXT_ULP_SYM_L4_HDR_ERROR_YES = 1,
+ BNXT_ULP_SYM_L4_HDR_TYPE_IGNORE = 0,
+ BNXT_ULP_SYM_L4_HDR_TYPE_TCP = 0,
+ BNXT_ULP_SYM_L4_HDR_TYPE_UDP = 1,
+ BNXT_ULP_SYM_L4_HDR_TYPE_ICMP = 2,
+ BNXT_ULP_SYM_L4_HDR_TYPE_UPAR1 = 3,
+ BNXT_ULP_SYM_L4_HDR_TYPE_UPAR2 = 4,
+ BNXT_ULP_SYM_L4_HDR_TYPE_BTH_V1 = 5,
+ BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_IGNORE = 0,
+ BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_NO = 0,
+ BNXT_ULP_SYM_L4_HDR_IS_UDP_TCP_YES = 1,
+ BNXT_ULP_SYM_POP_VLAN_NO = 0,
+ BNXT_ULP_SYM_POP_VLAN_YES = 1,
+ BNXT_ULP_SYM_DECAP_FUNC_NONE = 0,
+ BNXT_ULP_SYM_DECAP_FUNC_THRU_TL2 = 3,
+ BNXT_ULP_SYM_DECAP_FUNC_THRU_TL3 = 8,
+ BNXT_ULP_SYM_DECAP_FUNC_THRU_TL4 = 9,
+ BNXT_ULP_SYM_DECAP_FUNC_THRU_TUN = 10,
+ BNXT_ULP_SYM_DECAP_FUNC_THRU_L2 = 11,
+ BNXT_ULP_SYM_DECAP_FUNC_THRU_L3 = 12,
+ BNXT_ULP_SYM_DECAP_FUNC_THRU_L4 = 13,
+ BNXT_ULP_SYM_ECV_VALID_NO = 0,
+ BNXT_ULP_SYM_ECV_VALID_YES = 1,
+ BNXT_ULP_SYM_ECV_CUSTOM_EN_NO = 0,
+ BNXT_ULP_SYM_ECV_CUSTOM_EN_YES = 1,
+ BNXT_ULP_SYM_ECV_L2_EN_NO = 0,
+ BNXT_ULP_SYM_ECV_L2_EN_YES = 1,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_NOP = 0,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI = 1,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_IVLAN_PRI = 2,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_REMAP_DIFFSERV = 3,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_2_ENCAP_PRI = 4,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_2_REMAP_DIFFSERV = 5,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_ENCAP_PRI = 6,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_REMAP_DIFFSERV = 7,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_0 = 8,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_1 = 8,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_2 = 8,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_3 = 8,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_4 = 8,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_5 = 8,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_6 = 8,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_0_PRI_7 = 8,
+ BNXT_ULP_SYM_ECV_L3_TYPE_NONE = 0,
+ BNXT_ULP_SYM_ECV_L3_TYPE_IPV4 = 4,
+ BNXT_ULP_SYM_ECV_L3_TYPE_IPV6 = 5,
+ BNXT_ULP_SYM_ECV_L3_TYPE_MPLS_8847 = 6,
+ BNXT_ULP_SYM_ECV_L3_TYPE_MPLS_8848 = 7,
+ BNXT_ULP_SYM_ECV_L4_TYPE_NONE = 0,
+ BNXT_ULP_SYM_ECV_L4_TYPE_UDP = 4,
+ BNXT_ULP_SYM_ECV_L4_TYPE_UDP_CSUM = 5,
+ BNXT_ULP_SYM_ECV_L4_TYPE_UDP_ENTROPY = 6,
+ BNXT_ULP_SYM_ECV_L4_TYPE_UDP_ENTROPY_CSUM = 7,
+ BNXT_ULP_SYM_ECV_TUN_TYPE_NONE = 0,
+ BNXT_ULP_SYM_ECV_TUN_TYPE_GENERIC = 1,
+ BNXT_ULP_SYM_ECV_TUN_TYPE_VXLAN = 2,
+ BNXT_ULP_SYM_ECV_TUN_TYPE_NGE = 3,
+ BNXT_ULP_SYM_ECV_TUN_TYPE_NVGRE = 4,
+ BNXT_ULP_SYM_ECV_TUN_TYPE_GRE = 5,
BNXT_ULP_SYM_WH_PLUS_INT_ACT_REC = 1,
- BNXT_ULP_SYM_WH_PLUS_LOOPBACK_PORT = 4,
- BNXT_ULP_SYM_WH_PLUS_MC_ACT_REC = 1,
+ BNXT_ULP_SYM_WH_PLUS_EXT_ACT_REC = 0,
BNXT_ULP_SYM_WH_PLUS_UC_ACT_REC = 0,
+ BNXT_ULP_SYM_WH_PLUS_MC_ACT_REC = 1,
+ BNXT_ULP_SYM_ACT_REC_DROP_YES = 1,
+ BNXT_ULP_SYM_ACT_REC_DROP_NO = 0,
+ BNXT_ULP_SYM_ACT_REC_POP_VLAN_YES = 1,
+ BNXT_ULP_SYM_ACT_REC_POP_VLAN_NO = 0,
+ BNXT_ULP_SYM_ACT_REC_METER_EN_YES = 1,
+ BNXT_ULP_SYM_ACT_REC_METER_EN_NO = 0,
+ BNXT_ULP_SYM_WH_PLUS_LOOPBACK_PORT = 4,
+ BNXT_ULP_SYM_WH_PLUS_EXT_EM_MAX_KEY_SIZE = 448,
+ BNXT_ULP_SYM_STINGRAY_LOOPBACK_PORT = 16,
+ BNXT_ULP_SYM_STINGRAY_EXT_EM_MAX_KEY_SIZE = 448,
+ BNXT_ULP_SYM_STINGRAY2_LOOPBACK_PORT = 3,
+ BNXT_ULP_SYM_THOR_LOOPBACK_PORT = 3,
+ BNXT_ULP_SYM_MATCH_TYPE_EM = 0,
+ BNXT_ULP_SYM_MATCH_TYPE_WM = 1,
+ BNXT_ULP_SYM_IP_PROTO_ICMP = 1,
+ BNXT_ULP_SYM_IP_PROTO_IGMP = 2,
+ BNXT_ULP_SYM_IP_PROTO_IP_IN_IP = 4,
+ BNXT_ULP_SYM_IP_PROTO_TCP = 6,
+ BNXT_ULP_SYM_IP_PROTO_UDP = 17,
+ BNXT_ULP_SYM_NO = 0,
BNXT_ULP_SYM_YES = 1
};
enum bnxt_ulp_wh_plus {
- BNXT_ULP_WH_PLUS_EXT_EM_MAX_KEY_SIZE = 448,
- BNXT_ULP_WH_PLUS_LOOPBACK_PORT = 4
+ BNXT_ULP_WH_PLUS_LOOPBACK_PORT = 4,
+ BNXT_ULP_WH_PLUS_EXT_EM_MAX_KEY_SIZE = 448
};
enum bnxt_ulp_act_prop_sz {
@@ -604,18 +605,44 @@ enum bnxt_ulp_act_prop_idx {
enum bnxt_ulp_class_hid {
BNXT_ULP_CLASS_HID_0080 = 0x0080,
- BNXT_ULP_CLASS_HID_0000 = 0x0000,
- BNXT_ULP_CLASS_HID_0087 = 0x0087
+ BNXT_ULP_CLASS_HID_0087 = 0x0087,
+ BNXT_ULP_CLASS_HID_0000 = 0x0000
};
enum bnxt_ulp_act_hid {
- BNXT_ULP_ACT_HID_00a1 = 0x00a1,
+ BNXT_ULP_ACT_HID_0002 = 0x0002,
+ BNXT_ULP_ACT_HID_0022 = 0x0022,
+ BNXT_ULP_ACT_HID_0026 = 0x0026,
+ BNXT_ULP_ACT_HID_0006 = 0x0006,
+ BNXT_ULP_ACT_HID_0009 = 0x0009,
BNXT_ULP_ACT_HID_0029 = 0x0029,
- BNXT_ULP_ACT_HID_0040 = 0x0040
+ BNXT_ULP_ACT_HID_002d = 0x002d,
+ BNXT_ULP_ACT_HID_004b = 0x004b,
+ BNXT_ULP_ACT_HID_004a = 0x004a,
+ BNXT_ULP_ACT_HID_004f = 0x004f,
+ BNXT_ULP_ACT_HID_004e = 0x004e,
+ BNXT_ULP_ACT_HID_006c = 0x006c,
+ BNXT_ULP_ACT_HID_0070 = 0x0070,
+ BNXT_ULP_ACT_HID_0021 = 0x0021,
+ BNXT_ULP_ACT_HID_0025 = 0x0025,
+ BNXT_ULP_ACT_HID_0043 = 0x0043,
+ BNXT_ULP_ACT_HID_0042 = 0x0042,
+ BNXT_ULP_ACT_HID_0047 = 0x0047,
+ BNXT_ULP_ACT_HID_0046 = 0x0046,
+ BNXT_ULP_ACT_HID_0064 = 0x0064,
+ BNXT_ULP_ACT_HID_0068 = 0x0068,
+ BNXT_ULP_ACT_HID_00a1 = 0x00a1,
+ BNXT_ULP_ACT_HID_00df = 0x00df
};
enum bnxt_ulp_df_tpl {
BNXT_ULP_DF_TPL_PORT_TO_VS = 1,
- BNXT_ULP_DF_TPL_VS_TO_PORT = 2
+ BNXT_ULP_DF_TPL_VS_TO_PORT = 2,
+ BNXT_ULP_DF_TPL_VFREP_TO_VF = 3,
+ BNXT_ULP_DF_TPL_VF_TO_VFREP = 4,
+ BNXT_ULP_DF_TPL_DRV_FUNC_SVIF_PUSH_VLAN = 5,
+ BNXT_ULP_DF_TPL_PORT_SVIF_VID_VNIC_POP_VLAN = 6,
+ BNXT_ULP_DF_TPL_LOOPBACK_ACTION_REC = 7
};
+
#endif
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h b/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h
index 84b9523..7695420 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_field.h
@@ -6,220 +6,275 @@
#ifndef ULP_HDR_FIELD_ENUMS_H_
#define ULP_HDR_FIELD_ENUMS_H_
-enum bnxt_ulp_hf0 {
- BNXT_ULP_HF0_IDX_SVIF_INDEX = 0,
- BNXT_ULP_HF0_IDX_O_ETH_DMAC = 1,
- BNXT_ULP_HF0_IDX_O_ETH_SMAC = 2,
- BNXT_ULP_HF0_IDX_O_ETH_TYPE = 3,
- BNXT_ULP_HF0_IDX_OO_VLAN_CFI_PRI = 4,
- BNXT_ULP_HF0_IDX_OO_VLAN_VID = 5,
- BNXT_ULP_HF0_IDX_OO_VLAN_TYPE = 6,
- BNXT_ULP_HF0_IDX_OI_VLAN_CFI_PRI = 7,
- BNXT_ULP_HF0_IDX_OI_VLAN_VID = 8,
- BNXT_ULP_HF0_IDX_OI_VLAN_TYPE = 9,
- BNXT_ULP_HF0_IDX_O_IPV4_VER = 10,
- BNXT_ULP_HF0_IDX_O_IPV4_TOS = 11,
- BNXT_ULP_HF0_IDX_O_IPV4_LEN = 12,
- BNXT_ULP_HF0_IDX_O_IPV4_FRAG_ID = 13,
- BNXT_ULP_HF0_IDX_O_IPV4_FRAG_OFF = 14,
- BNXT_ULP_HF0_IDX_O_IPV4_TTL = 15,
- BNXT_ULP_HF0_IDX_O_IPV4_NEXT_PID = 16,
- BNXT_ULP_HF0_IDX_O_IPV4_CSUM = 17,
- BNXT_ULP_HF0_IDX_O_IPV4_SRC_ADDR = 18,
- BNXT_ULP_HF0_IDX_O_IPV4_DST_ADDR = 19,
- BNXT_ULP_HF0_IDX_O_UDP_SRC_PORT = 20,
- BNXT_ULP_HF0_IDX_O_UDP_DST_PORT = 21,
- BNXT_ULP_HF0_IDX_O_UDP_LENGTH = 22,
- BNXT_ULP_HF0_IDX_O_UDP_CSUM = 23
-};
-
enum bnxt_ulp_hf1 {
- BNXT_ULP_HF1_IDX_SVIF_INDEX = 0,
- BNXT_ULP_HF1_IDX_O_ETH_DMAC = 1,
- BNXT_ULP_HF1_IDX_O_ETH_SMAC = 2,
- BNXT_ULP_HF1_IDX_O_ETH_TYPE = 3,
- BNXT_ULP_HF1_IDX_OO_VLAN_CFI_PRI = 4,
- BNXT_ULP_HF1_IDX_OO_VLAN_VID = 5,
- BNXT_ULP_HF1_IDX_OO_VLAN_TYPE = 6,
- BNXT_ULP_HF1_IDX_OI_VLAN_CFI_PRI = 7,
- BNXT_ULP_HF1_IDX_OI_VLAN_VID = 8,
- BNXT_ULP_HF1_IDX_OI_VLAN_TYPE = 9,
- BNXT_ULP_HF1_IDX_O_IPV4_VER = 10,
- BNXT_ULP_HF1_IDX_O_IPV4_TOS = 11,
- BNXT_ULP_HF1_IDX_O_IPV4_LEN = 12,
- BNXT_ULP_HF1_IDX_O_IPV4_FRAG_ID = 13,
- BNXT_ULP_HF1_IDX_O_IPV4_FRAG_OFF = 14,
- BNXT_ULP_HF1_IDX_O_IPV4_TTL = 15,
- BNXT_ULP_HF1_IDX_O_IPV4_NEXT_PID = 16,
- BNXT_ULP_HF1_IDX_O_IPV4_CSUM = 17,
- BNXT_ULP_HF1_IDX_O_IPV4_SRC_ADDR = 18,
- BNXT_ULP_HF1_IDX_O_IPV4_DST_ADDR = 19,
- BNXT_ULP_HF1_IDX_O_UDP_SRC_PORT = 20,
- BNXT_ULP_HF1_IDX_O_UDP_DST_PORT = 21,
- BNXT_ULP_HF1_IDX_O_UDP_LENGTH = 22,
- BNXT_ULP_HF1_IDX_O_UDP_CSUM = 23
+ BNXT_ULP_HF1_IDX_SVIF_INDEX = 0
};
enum bnxt_ulp_hf2 {
- BNXT_ULP_HF2_IDX_SVIF_INDEX = 0,
- BNXT_ULP_HF2_IDX_O_ETH_DMAC = 1,
- BNXT_ULP_HF2_IDX_O_ETH_SMAC = 2,
- BNXT_ULP_HF2_IDX_O_ETH_TYPE = 3,
- BNXT_ULP_HF2_IDX_OO_VLAN_CFI_PRI = 4,
- BNXT_ULP_HF2_IDX_OO_VLAN_VID = 5,
- BNXT_ULP_HF2_IDX_OO_VLAN_TYPE = 6,
- BNXT_ULP_HF2_IDX_OI_VLAN_CFI_PRI = 7,
- BNXT_ULP_HF2_IDX_OI_VLAN_VID = 8,
- BNXT_ULP_HF2_IDX_OI_VLAN_TYPE = 9,
- BNXT_ULP_HF2_IDX_O_IPV4_VER = 10,
- BNXT_ULP_HF2_IDX_O_IPV4_TOS = 11,
- BNXT_ULP_HF2_IDX_O_IPV4_LEN = 12,
- BNXT_ULP_HF2_IDX_O_IPV4_FRAG_ID = 13,
- BNXT_ULP_HF2_IDX_O_IPV4_FRAG_OFF = 14,
- BNXT_ULP_HF2_IDX_O_IPV4_TTL = 15,
- BNXT_ULP_HF2_IDX_O_IPV4_NEXT_PID = 16,
- BNXT_ULP_HF2_IDX_O_IPV4_CSUM = 17,
- BNXT_ULP_HF2_IDX_O_IPV4_SRC_ADDR = 18,
- BNXT_ULP_HF2_IDX_O_IPV4_DST_ADDR = 19,
- BNXT_ULP_HF2_IDX_O_UDP_SRC_PORT = 20,
- BNXT_ULP_HF2_IDX_O_UDP_DST_PORT = 21,
- BNXT_ULP_HF2_IDX_O_UDP_LENGTH = 22,
- BNXT_ULP_HF2_IDX_O_UDP_CSUM = 23,
- BNXT_ULP_HF2_IDX_T_VXLAN_FLAGS = 24,
- BNXT_ULP_HF2_IDX_T_VXLAN_RSVD0 = 25,
- BNXT_ULP_HF2_IDX_T_VXLAN_VNI = 26,
- BNXT_ULP_HF2_IDX_T_VXLAN_RSVD1 = 27,
- BNXT_ULP_HF2_IDX_I_ETH_DMAC = 28,
- BNXT_ULP_HF2_IDX_I_ETH_SMAC = 29,
- BNXT_ULP_HF2_IDX_I_ETH_TYPE = 30,
- BNXT_ULP_HF2_IDX_IO_VLAN_CFI_PRI = 31,
- BNXT_ULP_HF2_IDX_IO_VLAN_VID = 32,
- BNXT_ULP_HF2_IDX_IO_VLAN_TYPE = 33,
- BNXT_ULP_HF2_IDX_II_VLAN_CFI_PRI = 34,
- BNXT_ULP_HF2_IDX_II_VLAN_VID = 35,
- BNXT_ULP_HF2_IDX_II_VLAN_TYPE = 36,
- BNXT_ULP_HF2_IDX_I_IPV4_VER = 37,
- BNXT_ULP_HF2_IDX_I_IPV4_TOS = 38,
- BNXT_ULP_HF2_IDX_I_IPV4_LEN = 39,
- BNXT_ULP_HF2_IDX_I_IPV4_FRAG_ID = 40,
- BNXT_ULP_HF2_IDX_I_IPV4_FRAG_OFF = 41,
- BNXT_ULP_HF2_IDX_I_IPV4_TTL = 42,
- BNXT_ULP_HF2_IDX_I_IPV4_NEXT_PID = 43,
- BNXT_ULP_HF2_IDX_I_IPV4_CSUM = 44,
- BNXT_ULP_HF2_IDX_I_IPV4_SRC_ADDR = 45,
- BNXT_ULP_HF2_IDX_I_IPV4_DST_ADDR = 46,
- BNXT_ULP_HF2_IDX_I_UDP_SRC_PORT = 47,
- BNXT_ULP_HF2_IDX_I_UDP_DST_PORT = 48,
- BNXT_ULP_HF2_IDX_I_UDP_LENGTH = 49,
- BNXT_ULP_HF2_IDX_I_UDP_CSUM = 50
-};
-
-enum bnxt_ulp_hf_bitmask0 {
- BNXT_ULP_HF0_BITMASK_SVIF_INDEX = 0x8000000000000000,
- BNXT_ULP_HF0_BITMASK_O_ETH_DMAC = 0x4000000000000000,
- BNXT_ULP_HF0_BITMASK_O_ETH_SMAC = 0x2000000000000000,
- BNXT_ULP_HF0_BITMASK_O_ETH_TYPE = 0x1000000000000000,
- BNXT_ULP_HF0_BITMASK_OO_VLAN_CFI_PRI = 0x0800000000000000,
- BNXT_ULP_HF0_BITMASK_OO_VLAN_VID = 0x0400000000000000,
- BNXT_ULP_HF0_BITMASK_OO_VLAN_TYPE = 0x0200000000000000,
- BNXT_ULP_HF0_BITMASK_OI_VLAN_CFI_PRI = 0x0100000000000000,
- BNXT_ULP_HF0_BITMASK_OI_VLAN_VID = 0x0080000000000000,
- BNXT_ULP_HF0_BITMASK_OI_VLAN_TYPE = 0x0040000000000000,
- BNXT_ULP_HF0_BITMASK_O_IPV4_VER = 0x0020000000000000,
- BNXT_ULP_HF0_BITMASK_O_IPV4_TOS = 0x0010000000000000,
- BNXT_ULP_HF0_BITMASK_O_IPV4_LEN = 0x0008000000000000,
- BNXT_ULP_HF0_BITMASK_O_IPV4_FRAG_ID = 0x0004000000000000,
- BNXT_ULP_HF0_BITMASK_O_IPV4_FRAG_OFF = 0x0002000000000000,
- BNXT_ULP_HF0_BITMASK_O_IPV4_TTL = 0x0001000000000000,
- BNXT_ULP_HF0_BITMASK_O_IPV4_NEXT_PID = 0x0000800000000000,
- BNXT_ULP_HF0_BITMASK_O_IPV4_CSUM = 0x0000400000000000,
- BNXT_ULP_HF0_BITMASK_O_IPV4_SRC_ADDR = 0x0000200000000000,
- BNXT_ULP_HF0_BITMASK_O_IPV4_DST_ADDR = 0x0000100000000000,
- BNXT_ULP_HF0_BITMASK_O_UDP_SRC_PORT = 0x0000080000000000,
- BNXT_ULP_HF0_BITMASK_O_UDP_DST_PORT = 0x0000040000000000,
- BNXT_ULP_HF0_BITMASK_O_UDP_LENGTH = 0x0000020000000000,
- BNXT_ULP_HF0_BITMASK_O_UDP_CSUM = 0x0000010000000000
+ BNXT_ULP_HF2_IDX_SVIF_INDEX = 0
+};
+
+enum bnxt_ulp_hf3 {
+ BNXT_ULP_HF3_IDX_SVIF_INDEX = 0
+};
+
+enum bnxt_ulp_hf4 {
+ BNXT_ULP_HF4_IDX_SVIF_INDEX = 0
+};
+
+enum bnxt_ulp_hf5 {
+ BNXT_ULP_HF5_IDX_SVIF_INDEX = 0
+};
+
+enum bnxt_ulp_hf6 {
+ BNXT_ULP_HF6_IDX_SVIF_INDEX = 0
+};
+
+enum bnxt_ulp_hf7 {
+ BNXT_ULP_HF7_IDX_SVIF_INDEX = 0
+};
+
+enum bnxt_ulp_hf8 {
+ BNXT_ULP_HF8_IDX_SVIF_INDEX = 0,
+ BNXT_ULP_HF8_IDX_O_ETH_DMAC = 1,
+ BNXT_ULP_HF8_IDX_O_ETH_SMAC = 2,
+ BNXT_ULP_HF8_IDX_O_ETH_TYPE = 3,
+ BNXT_ULP_HF8_IDX_OO_VLAN_CFI_PRI = 4,
+ BNXT_ULP_HF8_IDX_OO_VLAN_VID = 5,
+ BNXT_ULP_HF8_IDX_OO_VLAN_TYPE = 6,
+ BNXT_ULP_HF8_IDX_OI_VLAN_CFI_PRI = 7,
+ BNXT_ULP_HF8_IDX_OI_VLAN_VID = 8,
+ BNXT_ULP_HF8_IDX_OI_VLAN_TYPE = 9,
+ BNXT_ULP_HF8_IDX_O_IPV4_VER = 10,
+ BNXT_ULP_HF8_IDX_O_IPV4_TOS = 11,
+ BNXT_ULP_HF8_IDX_O_IPV4_LEN = 12,
+ BNXT_ULP_HF8_IDX_O_IPV4_FRAG_ID = 13,
+ BNXT_ULP_HF8_IDX_O_IPV4_FRAG_OFF = 14,
+ BNXT_ULP_HF8_IDX_O_IPV4_TTL = 15,
+ BNXT_ULP_HF8_IDX_O_IPV4_PROTO_ID = 16,
+ BNXT_ULP_HF8_IDX_O_IPV4_CSUM = 17,
+ BNXT_ULP_HF8_IDX_O_IPV4_SRC_ADDR = 18,
+ BNXT_ULP_HF8_IDX_O_IPV4_DST_ADDR = 19,
+ BNXT_ULP_HF8_IDX_O_UDP_SRC_PORT = 20,
+ BNXT_ULP_HF8_IDX_O_UDP_DST_PORT = 21,
+ BNXT_ULP_HF8_IDX_O_UDP_LENGTH = 22,
+ BNXT_ULP_HF8_IDX_O_UDP_CSUM = 23
+};
+
+enum bnxt_ulp_hf9 {
+ BNXT_ULP_HF9_IDX_SVIF_INDEX = 0,
+ BNXT_ULP_HF9_IDX_O_ETH_DMAC = 1,
+ BNXT_ULP_HF9_IDX_O_ETH_SMAC = 2,
+ BNXT_ULP_HF9_IDX_O_ETH_TYPE = 3,
+ BNXT_ULP_HF9_IDX_OO_VLAN_CFI_PRI = 4,
+ BNXT_ULP_HF9_IDX_OO_VLAN_VID = 5,
+ BNXT_ULP_HF9_IDX_OO_VLAN_TYPE = 6,
+ BNXT_ULP_HF9_IDX_OI_VLAN_CFI_PRI = 7,
+ BNXT_ULP_HF9_IDX_OI_VLAN_VID = 8,
+ BNXT_ULP_HF9_IDX_OI_VLAN_TYPE = 9,
+ BNXT_ULP_HF9_IDX_O_IPV4_VER = 10,
+ BNXT_ULP_HF9_IDX_O_IPV4_TOS = 11,
+ BNXT_ULP_HF9_IDX_O_IPV4_LEN = 12,
+ BNXT_ULP_HF9_IDX_O_IPV4_FRAG_ID = 13,
+ BNXT_ULP_HF9_IDX_O_IPV4_FRAG_OFF = 14,
+ BNXT_ULP_HF9_IDX_O_IPV4_TTL = 15,
+ BNXT_ULP_HF9_IDX_O_IPV4_PROTO_ID = 16,
+ BNXT_ULP_HF9_IDX_O_IPV4_CSUM = 17,
+ BNXT_ULP_HF9_IDX_O_IPV4_SRC_ADDR = 18,
+ BNXT_ULP_HF9_IDX_O_IPV4_DST_ADDR = 19,
+ BNXT_ULP_HF9_IDX_O_UDP_SRC_PORT = 20,
+ BNXT_ULP_HF9_IDX_O_UDP_DST_PORT = 21,
+ BNXT_ULP_HF9_IDX_O_UDP_LENGTH = 22,
+ BNXT_ULP_HF9_IDX_O_UDP_CSUM = 23,
+ BNXT_ULP_HF9_IDX_T_VXLAN_FLAGS = 24,
+ BNXT_ULP_HF9_IDX_T_VXLAN_RSVD0 = 25,
+ BNXT_ULP_HF9_IDX_T_VXLAN_VNI = 26,
+ BNXT_ULP_HF9_IDX_T_VXLAN_RSVD1 = 27,
+ BNXT_ULP_HF9_IDX_I_ETH_DMAC = 28,
+ BNXT_ULP_HF9_IDX_I_ETH_SMAC = 29,
+ BNXT_ULP_HF9_IDX_I_ETH_TYPE = 30,
+ BNXT_ULP_HF9_IDX_IO_VLAN_CFI_PRI = 31,
+ BNXT_ULP_HF9_IDX_IO_VLAN_VID = 32,
+ BNXT_ULP_HF9_IDX_IO_VLAN_TYPE = 33,
+ BNXT_ULP_HF9_IDX_II_VLAN_CFI_PRI = 34,
+ BNXT_ULP_HF9_IDX_II_VLAN_VID = 35,
+ BNXT_ULP_HF9_IDX_II_VLAN_TYPE = 36,
+ BNXT_ULP_HF9_IDX_I_IPV4_VER = 37,
+ BNXT_ULP_HF9_IDX_I_IPV4_TOS = 38,
+ BNXT_ULP_HF9_IDX_I_IPV4_LEN = 39,
+ BNXT_ULP_HF9_IDX_I_IPV4_FRAG_ID = 40,
+ BNXT_ULP_HF9_IDX_I_IPV4_FRAG_OFF = 41,
+ BNXT_ULP_HF9_IDX_I_IPV4_TTL = 42,
+ BNXT_ULP_HF9_IDX_I_IPV4_PROTO_ID = 43,
+ BNXT_ULP_HF9_IDX_I_IPV4_CSUM = 44,
+ BNXT_ULP_HF9_IDX_I_IPV4_SRC_ADDR = 45,
+ BNXT_ULP_HF9_IDX_I_IPV4_DST_ADDR = 46,
+ BNXT_ULP_HF9_IDX_I_UDP_SRC_PORT = 47,
+ BNXT_ULP_HF9_IDX_I_UDP_DST_PORT = 48,
+ BNXT_ULP_HF9_IDX_I_UDP_LENGTH = 49,
+ BNXT_ULP_HF9_IDX_I_UDP_CSUM = 50
+};
+
+enum bnxt_ulp_hf10 {
+ BNXT_ULP_HF10_IDX_SVIF_INDEX = 0,
+ BNXT_ULP_HF10_IDX_O_ETH_DMAC = 1,
+ BNXT_ULP_HF10_IDX_O_ETH_SMAC = 2,
+ BNXT_ULP_HF10_IDX_O_ETH_TYPE = 3,
+ BNXT_ULP_HF10_IDX_OO_VLAN_CFI_PRI = 4,
+ BNXT_ULP_HF10_IDX_OO_VLAN_VID = 5,
+ BNXT_ULP_HF10_IDX_OO_VLAN_TYPE = 6,
+ BNXT_ULP_HF10_IDX_OI_VLAN_CFI_PRI = 7,
+ BNXT_ULP_HF10_IDX_OI_VLAN_VID = 8,
+ BNXT_ULP_HF10_IDX_OI_VLAN_TYPE = 9,
+ BNXT_ULP_HF10_IDX_O_IPV4_VER = 10,
+ BNXT_ULP_HF10_IDX_O_IPV4_TOS = 11,
+ BNXT_ULP_HF10_IDX_O_IPV4_LEN = 12,
+ BNXT_ULP_HF10_IDX_O_IPV4_FRAG_ID = 13,
+ BNXT_ULP_HF10_IDX_O_IPV4_FRAG_OFF = 14,
+ BNXT_ULP_HF10_IDX_O_IPV4_TTL = 15,
+ BNXT_ULP_HF10_IDX_O_IPV4_PROTO_ID = 16,
+ BNXT_ULP_HF10_IDX_O_IPV4_CSUM = 17,
+ BNXT_ULP_HF10_IDX_O_IPV4_SRC_ADDR = 18,
+ BNXT_ULP_HF10_IDX_O_IPV4_DST_ADDR = 19,
+ BNXT_ULP_HF10_IDX_O_UDP_SRC_PORT = 20,
+ BNXT_ULP_HF10_IDX_O_UDP_DST_PORT = 21,
+ BNXT_ULP_HF10_IDX_O_UDP_LENGTH = 22,
+ BNXT_ULP_HF10_IDX_O_UDP_CSUM = 23
};
enum bnxt_ulp_hf_bitmask1 {
- BNXT_ULP_HF1_BITMASK_SVIF_INDEX = 0x8000000000000000,
- BNXT_ULP_HF1_BITMASK_O_ETH_DMAC = 0x4000000000000000,
- BNXT_ULP_HF1_BITMASK_O_ETH_SMAC = 0x2000000000000000,
- BNXT_ULP_HF1_BITMASK_O_ETH_TYPE = 0x1000000000000000,
- BNXT_ULP_HF1_BITMASK_OO_VLAN_CFI_PRI = 0x0800000000000000,
- BNXT_ULP_HF1_BITMASK_OO_VLAN_VID = 0x0400000000000000,
- BNXT_ULP_HF1_BITMASK_OO_VLAN_TYPE = 0x0200000000000000,
- BNXT_ULP_HF1_BITMASK_OI_VLAN_CFI_PRI = 0x0100000000000000,
- BNXT_ULP_HF1_BITMASK_OI_VLAN_VID = 0x0080000000000000,
- BNXT_ULP_HF1_BITMASK_OI_VLAN_TYPE = 0x0040000000000000,
- BNXT_ULP_HF1_BITMASK_O_IPV4_VER = 0x0020000000000000,
- BNXT_ULP_HF1_BITMASK_O_IPV4_TOS = 0x0010000000000000,
- BNXT_ULP_HF1_BITMASK_O_IPV4_LEN = 0x0008000000000000,
- BNXT_ULP_HF1_BITMASK_O_IPV4_FRAG_ID = 0x0004000000000000,
- BNXT_ULP_HF1_BITMASK_O_IPV4_FRAG_OFF = 0x0002000000000000,
- BNXT_ULP_HF1_BITMASK_O_IPV4_TTL = 0x0001000000000000,
- BNXT_ULP_HF1_BITMASK_O_IPV4_NEXT_PID = 0x0000800000000000,
- BNXT_ULP_HF1_BITMASK_O_IPV4_CSUM = 0x0000400000000000,
- BNXT_ULP_HF1_BITMASK_O_IPV4_SRC_ADDR = 0x0000200000000000,
- BNXT_ULP_HF1_BITMASK_O_IPV4_DST_ADDR = 0x0000100000000000,
- BNXT_ULP_HF1_BITMASK_O_UDP_SRC_PORT = 0x0000080000000000,
- BNXT_ULP_HF1_BITMASK_O_UDP_DST_PORT = 0x0000040000000000,
- BNXT_ULP_HF1_BITMASK_O_UDP_LENGTH = 0x0000020000000000,
- BNXT_ULP_HF1_BITMASK_O_UDP_CSUM = 0x0000010000000000
+ BNXT_ULP_HF1_BITMASK_SVIF_INDEX = 0x8000000000000000
};
enum bnxt_ulp_hf_bitmask2 {
- BNXT_ULP_HF2_BITMASK_SVIF_INDEX = 0x8000000000000000,
- BNXT_ULP_HF2_BITMASK_O_ETH_DMAC = 0x4000000000000000,
- BNXT_ULP_HF2_BITMASK_O_ETH_SMAC = 0x2000000000000000,
- BNXT_ULP_HF2_BITMASK_O_ETH_TYPE = 0x1000000000000000,
- BNXT_ULP_HF2_BITMASK_OO_VLAN_CFI_PRI = 0x0800000000000000,
- BNXT_ULP_HF2_BITMASK_OO_VLAN_VID = 0x0400000000000000,
- BNXT_ULP_HF2_BITMASK_OO_VLAN_TYPE = 0x0200000000000000,
- BNXT_ULP_HF2_BITMASK_OI_VLAN_CFI_PRI = 0x0100000000000000,
- BNXT_ULP_HF2_BITMASK_OI_VLAN_VID = 0x0080000000000000,
- BNXT_ULP_HF2_BITMASK_OI_VLAN_TYPE = 0x0040000000000000,
- BNXT_ULP_HF2_BITMASK_O_IPV4_VER = 0x0020000000000000,
- BNXT_ULP_HF2_BITMASK_O_IPV4_TOS = 0x0010000000000000,
- BNXT_ULP_HF2_BITMASK_O_IPV4_LEN = 0x0008000000000000,
- BNXT_ULP_HF2_BITMASK_O_IPV4_FRAG_ID = 0x0004000000000000,
- BNXT_ULP_HF2_BITMASK_O_IPV4_FRAG_OFF = 0x0002000000000000,
- BNXT_ULP_HF2_BITMASK_O_IPV4_TTL = 0x0001000000000000,
- BNXT_ULP_HF2_BITMASK_O_IPV4_NEXT_PID = 0x0000800000000000,
- BNXT_ULP_HF2_BITMASK_O_IPV4_CSUM = 0x0000400000000000,
- BNXT_ULP_HF2_BITMASK_O_IPV4_SRC_ADDR = 0x0000200000000000,
- BNXT_ULP_HF2_BITMASK_O_IPV4_DST_ADDR = 0x0000100000000000,
- BNXT_ULP_HF2_BITMASK_O_UDP_SRC_PORT = 0x0000080000000000,
- BNXT_ULP_HF2_BITMASK_O_UDP_DST_PORT = 0x0000040000000000,
- BNXT_ULP_HF2_BITMASK_O_UDP_LENGTH = 0x0000020000000000,
- BNXT_ULP_HF2_BITMASK_O_UDP_CSUM = 0x0000010000000000,
- BNXT_ULP_HF2_BITMASK_T_VXLAN_FLAGS = 0x0000008000000000,
- BNXT_ULP_HF2_BITMASK_T_VXLAN_RSVD0 = 0x0000004000000000,
- BNXT_ULP_HF2_BITMASK_T_VXLAN_VNI = 0x0000002000000000,
- BNXT_ULP_HF2_BITMASK_T_VXLAN_RSVD1 = 0x0000001000000000,
- BNXT_ULP_HF2_BITMASK_I_ETH_DMAC = 0x0000000800000000,
- BNXT_ULP_HF2_BITMASK_I_ETH_SMAC = 0x0000000400000000,
- BNXT_ULP_HF2_BITMASK_I_ETH_TYPE = 0x0000000200000000,
- BNXT_ULP_HF2_BITMASK_IO_VLAN_CFI_PRI = 0x0000000100000000,
- BNXT_ULP_HF2_BITMASK_IO_VLAN_VID = 0x0000000080000000,
- BNXT_ULP_HF2_BITMASK_IO_VLAN_TYPE = 0x0000000040000000,
- BNXT_ULP_HF2_BITMASK_II_VLAN_CFI_PRI = 0x0000000020000000,
- BNXT_ULP_HF2_BITMASK_II_VLAN_VID = 0x0000000010000000,
- BNXT_ULP_HF2_BITMASK_II_VLAN_TYPE = 0x0000000008000000,
- BNXT_ULP_HF2_BITMASK_I_IPV4_VER = 0x0000000004000000,
- BNXT_ULP_HF2_BITMASK_I_IPV4_TOS = 0x0000000002000000,
- BNXT_ULP_HF2_BITMASK_I_IPV4_LEN = 0x0000000001000000,
- BNXT_ULP_HF2_BITMASK_I_IPV4_FRAG_ID = 0x0000000000800000,
- BNXT_ULP_HF2_BITMASK_I_IPV4_FRAG_OFF = 0x0000000000400000,
- BNXT_ULP_HF2_BITMASK_I_IPV4_TTL = 0x0000000000200000,
- BNXT_ULP_HF2_BITMASK_I_IPV4_NEXT_PID = 0x0000000000100000,
- BNXT_ULP_HF2_BITMASK_I_IPV4_CSUM = 0x0000000000080000,
- BNXT_ULP_HF2_BITMASK_I_IPV4_SRC_ADDR = 0x0000000000040000,
- BNXT_ULP_HF2_BITMASK_I_IPV4_DST_ADDR = 0x0000000000020000,
- BNXT_ULP_HF2_BITMASK_I_UDP_SRC_PORT = 0x0000000000010000,
- BNXT_ULP_HF2_BITMASK_I_UDP_DST_PORT = 0x0000000000008000,
- BNXT_ULP_HF2_BITMASK_I_UDP_LENGTH = 0x0000000000004000,
- BNXT_ULP_HF2_BITMASK_I_UDP_CSUM = 0x0000000000002000
+ BNXT_ULP_HF2_BITMASK_SVIF_INDEX = 0x8000000000000000
+};
+
+enum bnxt_ulp_hf_bitmask3 {
+ BNXT_ULP_HF3_BITMASK_SVIF_INDEX = 0x8000000000000000
+};
+
+enum bnxt_ulp_hf_bitmask4 {
+ BNXT_ULP_HF4_BITMASK_SVIF_INDEX = 0x8000000000000000
+};
+
+enum bnxt_ulp_hf_bitmask5 {
+ BNXT_ULP_HF5_BITMASK_SVIF_INDEX = 0x8000000000000000
+};
+
+enum bnxt_ulp_hf_bitmask6 {
+ BNXT_ULP_HF6_BITMASK_SVIF_INDEX = 0x8000000000000000
+};
+
+enum bnxt_ulp_hf_bitmask7 {
+ BNXT_ULP_HF7_BITMASK_SVIF_INDEX = 0x8000000000000000
+};
+
+enum bnxt_ulp_hf_bitmask8 {
+ BNXT_ULP_HF8_BITMASK_SVIF_INDEX = 0x8000000000000000,
+ BNXT_ULP_HF8_BITMASK_O_ETH_DMAC = 0x4000000000000000,
+ BNXT_ULP_HF8_BITMASK_O_ETH_SMAC = 0x2000000000000000,
+ BNXT_ULP_HF8_BITMASK_O_ETH_TYPE = 0x1000000000000000,
+ BNXT_ULP_HF8_BITMASK_OO_VLAN_CFI_PRI = 0x0800000000000000,
+ BNXT_ULP_HF8_BITMASK_OO_VLAN_VID = 0x0400000000000000,
+ BNXT_ULP_HF8_BITMASK_OO_VLAN_TYPE = 0x0200000000000000,
+ BNXT_ULP_HF8_BITMASK_OI_VLAN_CFI_PRI = 0x0100000000000000,
+ BNXT_ULP_HF8_BITMASK_OI_VLAN_VID = 0x0080000000000000,
+ BNXT_ULP_HF8_BITMASK_OI_VLAN_TYPE = 0x0040000000000000,
+ BNXT_ULP_HF8_BITMASK_O_IPV4_VER = 0x0020000000000000,
+ BNXT_ULP_HF8_BITMASK_O_IPV4_TOS = 0x0010000000000000,
+ BNXT_ULP_HF8_BITMASK_O_IPV4_LEN = 0x0008000000000000,
+ BNXT_ULP_HF8_BITMASK_O_IPV4_FRAG_ID = 0x0004000000000000,
+ BNXT_ULP_HF8_BITMASK_O_IPV4_FRAG_OFF = 0x0002000000000000,
+ BNXT_ULP_HF8_BITMASK_O_IPV4_TTL = 0x0001000000000000,
+ BNXT_ULP_HF8_BITMASK_O_IPV4_PROTO_ID = 0x0000800000000000,
+ BNXT_ULP_HF8_BITMASK_O_IPV4_CSUM = 0x0000400000000000,
+ BNXT_ULP_HF8_BITMASK_O_IPV4_SRC_ADDR = 0x0000200000000000,
+ BNXT_ULP_HF8_BITMASK_O_IPV4_DST_ADDR = 0x0000100000000000,
+ BNXT_ULP_HF8_BITMASK_O_UDP_SRC_PORT = 0x0000080000000000,
+ BNXT_ULP_HF8_BITMASK_O_UDP_DST_PORT = 0x0000040000000000,
+ BNXT_ULP_HF8_BITMASK_O_UDP_LENGTH = 0x0000020000000000,
+ BNXT_ULP_HF8_BITMASK_O_UDP_CSUM = 0x0000010000000000
+};
+
+enum bnxt_ulp_hf_bitmask9 {
+ BNXT_ULP_HF9_BITMASK_SVIF_INDEX = 0x8000000000000000,
+ BNXT_ULP_HF9_BITMASK_O_ETH_DMAC = 0x4000000000000000,
+ BNXT_ULP_HF9_BITMASK_O_ETH_SMAC = 0x2000000000000000,
+ BNXT_ULP_HF9_BITMASK_O_ETH_TYPE = 0x1000000000000000,
+ BNXT_ULP_HF9_BITMASK_OO_VLAN_CFI_PRI = 0x0800000000000000,
+ BNXT_ULP_HF9_BITMASK_OO_VLAN_VID = 0x0400000000000000,
+ BNXT_ULP_HF9_BITMASK_OO_VLAN_TYPE = 0x0200000000000000,
+ BNXT_ULP_HF9_BITMASK_OI_VLAN_CFI_PRI = 0x0100000000000000,
+ BNXT_ULP_HF9_BITMASK_OI_VLAN_VID = 0x0080000000000000,
+ BNXT_ULP_HF9_BITMASK_OI_VLAN_TYPE = 0x0040000000000000,
+ BNXT_ULP_HF9_BITMASK_O_IPV4_VER = 0x0020000000000000,
+ BNXT_ULP_HF9_BITMASK_O_IPV4_TOS = 0x0010000000000000,
+ BNXT_ULP_HF9_BITMASK_O_IPV4_LEN = 0x0008000000000000,
+ BNXT_ULP_HF9_BITMASK_O_IPV4_FRAG_ID = 0x0004000000000000,
+ BNXT_ULP_HF9_BITMASK_O_IPV4_FRAG_OFF = 0x0002000000000000,
+ BNXT_ULP_HF9_BITMASK_O_IPV4_TTL = 0x0001000000000000,
+ BNXT_ULP_HF9_BITMASK_O_IPV4_PROTO_ID = 0x0000800000000000,
+ BNXT_ULP_HF9_BITMASK_O_IPV4_CSUM = 0x0000400000000000,
+ BNXT_ULP_HF9_BITMASK_O_IPV4_SRC_ADDR = 0x0000200000000000,
+ BNXT_ULP_HF9_BITMASK_O_IPV4_DST_ADDR = 0x0000100000000000,
+ BNXT_ULP_HF9_BITMASK_O_UDP_SRC_PORT = 0x0000080000000000,
+ BNXT_ULP_HF9_BITMASK_O_UDP_DST_PORT = 0x0000040000000000,
+ BNXT_ULP_HF9_BITMASK_O_UDP_LENGTH = 0x0000020000000000,
+ BNXT_ULP_HF9_BITMASK_O_UDP_CSUM = 0x0000010000000000,
+ BNXT_ULP_HF9_BITMASK_T_VXLAN_FLAGS = 0x0000008000000000,
+ BNXT_ULP_HF9_BITMASK_T_VXLAN_RSVD0 = 0x0000004000000000,
+ BNXT_ULP_HF9_BITMASK_T_VXLAN_VNI = 0x0000002000000000,
+ BNXT_ULP_HF9_BITMASK_T_VXLAN_RSVD1 = 0x0000001000000000,
+ BNXT_ULP_HF9_BITMASK_I_ETH_DMAC = 0x0000000800000000,
+ BNXT_ULP_HF9_BITMASK_I_ETH_SMAC = 0x0000000400000000,
+ BNXT_ULP_HF9_BITMASK_I_ETH_TYPE = 0x0000000200000000,
+ BNXT_ULP_HF9_BITMASK_IO_VLAN_CFI_PRI = 0x0000000100000000,
+ BNXT_ULP_HF9_BITMASK_IO_VLAN_VID = 0x0000000080000000,
+ BNXT_ULP_HF9_BITMASK_IO_VLAN_TYPE = 0x0000000040000000,
+ BNXT_ULP_HF9_BITMASK_II_VLAN_CFI_PRI = 0x0000000020000000,
+ BNXT_ULP_HF9_BITMASK_II_VLAN_VID = 0x0000000010000000,
+ BNXT_ULP_HF9_BITMASK_II_VLAN_TYPE = 0x0000000008000000,
+ BNXT_ULP_HF9_BITMASK_I_IPV4_VER = 0x0000000004000000,
+ BNXT_ULP_HF9_BITMASK_I_IPV4_TOS = 0x0000000002000000,
+ BNXT_ULP_HF9_BITMASK_I_IPV4_LEN = 0x0000000001000000,
+ BNXT_ULP_HF9_BITMASK_I_IPV4_FRAG_ID = 0x0000000000800000,
+ BNXT_ULP_HF9_BITMASK_I_IPV4_FRAG_OFF = 0x0000000000400000,
+ BNXT_ULP_HF9_BITMASK_I_IPV4_TTL = 0x0000000000200000,
+ BNXT_ULP_HF9_BITMASK_I_IPV4_PROTO_ID = 0x0000000000100000,
+ BNXT_ULP_HF9_BITMASK_I_IPV4_CSUM = 0x0000000000080000,
+ BNXT_ULP_HF9_BITMASK_I_IPV4_SRC_ADDR = 0x0000000000040000,
+ BNXT_ULP_HF9_BITMASK_I_IPV4_DST_ADDR = 0x0000000000020000,
+ BNXT_ULP_HF9_BITMASK_I_UDP_SRC_PORT = 0x0000000000010000,
+ BNXT_ULP_HF9_BITMASK_I_UDP_DST_PORT = 0x0000000000008000,
+ BNXT_ULP_HF9_BITMASK_I_UDP_LENGTH = 0x0000000000004000,
+ BNXT_ULP_HF9_BITMASK_I_UDP_CSUM = 0x0000000000002000
};
+enum bnxt_ulp_hf_bitmask10 {
+ BNXT_ULP_HF10_BITMASK_SVIF_INDEX = 0x8000000000000000,
+ BNXT_ULP_HF10_BITMASK_O_ETH_DMAC = 0x4000000000000000,
+ BNXT_ULP_HF10_BITMASK_O_ETH_SMAC = 0x2000000000000000,
+ BNXT_ULP_HF10_BITMASK_O_ETH_TYPE = 0x1000000000000000,
+ BNXT_ULP_HF10_BITMASK_OO_VLAN_CFI_PRI = 0x0800000000000000,
+ BNXT_ULP_HF10_BITMASK_OO_VLAN_VID = 0x0400000000000000,
+ BNXT_ULP_HF10_BITMASK_OO_VLAN_TYPE = 0x0200000000000000,
+ BNXT_ULP_HF10_BITMASK_OI_VLAN_CFI_PRI = 0x0100000000000000,
+ BNXT_ULP_HF10_BITMASK_OI_VLAN_VID = 0x0080000000000000,
+ BNXT_ULP_HF10_BITMASK_OI_VLAN_TYPE = 0x0040000000000000,
+ BNXT_ULP_HF10_BITMASK_O_IPV4_VER = 0x0020000000000000,
+ BNXT_ULP_HF10_BITMASK_O_IPV4_TOS = 0x0010000000000000,
+ BNXT_ULP_HF10_BITMASK_O_IPV4_LEN = 0x0008000000000000,
+ BNXT_ULP_HF10_BITMASK_O_IPV4_FRAG_ID = 0x0004000000000000,
+ BNXT_ULP_HF10_BITMASK_O_IPV4_FRAG_OFF = 0x0002000000000000,
+ BNXT_ULP_HF10_BITMASK_O_IPV4_TTL = 0x0001000000000000,
+ BNXT_ULP_HF10_BITMASK_O_IPV4_PROTO_ID = 0x0000800000000000,
+ BNXT_ULP_HF10_BITMASK_O_IPV4_CSUM = 0x0000400000000000,
+ BNXT_ULP_HF10_BITMASK_O_IPV4_SRC_ADDR = 0x0000200000000000,
+ BNXT_ULP_HF10_BITMASK_O_IPV4_DST_ADDR = 0x0000100000000000,
+ BNXT_ULP_HF10_BITMASK_O_UDP_SRC_PORT = 0x0000080000000000,
+ BNXT_ULP_HF10_BITMASK_O_UDP_DST_PORT = 0x0000040000000000,
+ BNXT_ULP_HF10_BITMASK_O_UDP_LENGTH = 0x0000020000000000,
+ BNXT_ULP_HF10_BITMASK_O_UDP_CSUM = 0x0000010000000000
+};
#endif
diff --git a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c
index f65aeae..f0a57cf 100644
--- a/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c
+++ b/drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c
@@ -294,60 +294,72 @@ struct bnxt_ulp_rte_act_info ulp_act_info[] = {
struct bnxt_ulp_cache_tbl_params ulp_cache_tbl_params[] = {
[BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM << 1 |
- TF_DIR_RX] = {
- .num_entries = 16384
+ TF_DIR_RX] = {
+ .num_entries = 16384
},
[BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_L2_CNTXT_TCAM << 1 |
- TF_DIR_TX] = {
- .num_entries = 16384
+ TF_DIR_TX] = {
+ .num_entries = 16384
},
[BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM << 1 |
- TF_DIR_RX] = {
- .num_entries = 16384
+ TF_DIR_RX] = {
+ .num_entries = 16384
},
[BNXT_ULP_RESOURCE_SUB_TYPE_CACHE_TYPE_PROFILE_TCAM << 1 |
- TF_DIR_TX] = {
- .num_entries = 16384
+ TF_DIR_TX] = {
+ .num_entries = 16384
}
};
struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = {
[BNXT_ULP_DEVICE_ID_WH_PLUS] = {
- .flow_mem_type = BNXT_ULP_FLOW_MEM_TYPE_EXT,
- .byte_order = BNXT_ULP_BYTE_ORDER_LE,
- .encap_byte_swap = 1,
- .flow_db_num_entries = 32768,
- .mark_db_lfid_entries = 65536,
- .mark_db_gfid_entries = 65536,
- .flow_count_db_entries = 16384,
- .num_resources_per_flow = 8,
- .num_phy_ports = 2,
- .ext_cntr_table_type = 0,
- .byte_count_mask = 0x00000003ffffffff,
- .packet_count_mask = 0xfffffffc00000000,
- .byte_count_shift = 0,
- .packet_count_shift = 36
+ .flow_mem_type = BNXT_ULP_FLOW_MEM_TYPE_EXT,
+ .byte_order = BNXT_ULP_BYTE_ORDER_LE,
+ .encap_byte_swap = 1,
+ .flow_db_num_entries = 32768,
+ .mark_db_lfid_entries = 65536,
+ .mark_db_gfid_entries = 65536,
+ .flow_count_db_entries = 16384,
+ .num_resources_per_flow = 8,
+ .num_phy_ports = 2,
+ .ext_cntr_table_type = 0,
+ .byte_count_mask = 0x0000000fffffffff,
+ .packet_count_mask = 0xffffffff00000000,
+ .byte_count_shift = 0,
+ .packet_count_shift = 36
}
};
struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = {
[0] = {
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID,
- .direction = TF_DIR_RX
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_RX
},
[1] = {
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_PROF_FUNC,
- .glb_regfile_index = BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID,
- .direction = TF_DIR_TX
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_PROF_FUNC,
+ .glb_regfile_index = BNXT_ULP_GLB_REGFILE_INDEX_GLB_PROF_FUNC_ID,
+ .direction = TF_DIR_TX
},
[2] = {
- .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
- .resource_type = TF_IDENT_TYPE_L2_CTXT,
- .glb_regfile_index = BNXT_ULP_GLB_REGFILE_INDEX_GLB_L2_CNTXT_ID,
- .direction = TF_DIR_RX
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT,
+ .glb_regfile_index = BNXT_ULP_GLB_REGFILE_INDEX_GLB_L2_CNTXT_ID,
+ .direction = TF_DIR_RX
+ },
+ [3] = {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_IDENTIFIER,
+ .resource_type = TF_IDENT_TYPE_L2_CTXT,
+ .glb_regfile_index = BNXT_ULP_GLB_REGFILE_INDEX_GLB_L2_CNTXT_ID,
+ .direction = TF_DIR_TX
+ },
+ [4] = {
+ .resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
+ .resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
+ .glb_regfile_index = BNXT_ULP_GLB_REGFILE_INDEX_GLB_LB_AREC_PTR,
+ .direction = TF_DIR_TX
}
};
@@ -547,11 +559,11 @@ struct bnxt_ulp_rte_hdr_info ulp_hdr_info[] = {
};
uint32_t bnxt_ulp_encap_vtag_map[] = {
- [0] = BNXT_ULP_SYM_ECV_VTAG_TYPE_NOP,
- [1] = BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI,
- [2] = BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_2_ENCAP_PRI
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_NOP,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI,
+ BNXT_ULP_SYM_ECV_VTAG_TYPE_ADD_2_ENCAP_PRI
};
uint32_t ulp_glb_template_tbl[] = {
+ BNXT_ULP_DF_TPL_LOOPBACK_ACTION_REC
};
-
--
2.7.4
next prev parent reply other threads:[~2020-06-12 13:51 UTC|newest]
Thread overview: 271+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-12 13:28 [dpdk-dev] [PATCH 00/50] add features for host-based flow management Somnath Kotur
2020-06-12 13:28 ` [dpdk-dev] [PATCH 01/50] net/bnxt: Basic infrastructure support for VF representors Somnath Kotur
2020-06-12 13:28 ` [dpdk-dev] [PATCH 02/50] net/bnxt: Infrastructure support for VF-reps data path Somnath Kotur
2020-06-12 13:28 ` [dpdk-dev] [PATCH 03/50] net/bnxt: add support to get FID, default vnic ID and svif of VF-Rep Endpoint Somnath Kotur
2020-06-12 13:28 ` [dpdk-dev] [PATCH 04/50] net/bnxt: initialize parent PF information Somnath Kotur
2020-06-12 13:28 ` [dpdk-dev] [PATCH 05/50] net/bnxt: modify ulp_port_db_dev_port_intf_update prototype Somnath Kotur
2020-06-12 13:28 ` [dpdk-dev] [PATCH 06/50] net/bnxt: get port & function related information Somnath Kotur
2020-06-12 13:28 ` [dpdk-dev] [PATCH 07/50] net/bnxt: add support for bnxt_hwrm_port_phy_qcaps Somnath Kotur
2020-06-12 13:28 ` [dpdk-dev] [PATCH 08/50] net/bnxt: modify port_db to store & retrieve more info Somnath Kotur
2020-06-12 13:28 ` [dpdk-dev] [PATCH 09/50] net/bnxt: add support for Exact Match Somnath Kotur
2020-06-12 13:28 ` [dpdk-dev] [PATCH 10/50] net/bnxt: modify EM insert and delete to use HWRM direct Somnath Kotur
2020-06-12 13:28 ` [dpdk-dev] [PATCH 11/50] net/bnxt: add multi device support Somnath Kotur
2020-06-12 13:28 ` [dpdk-dev] [PATCH 12/50] net/bnxt: support bulk table get and mirror Somnath Kotur
2020-06-12 13:28 ` [dpdk-dev] [PATCH 13/50] net/bnxt: update multi device design support Somnath Kotur
2020-06-12 13:28 ` [dpdk-dev] [PATCH 14/50] net/bnxt: support two-level priority for TCAMs Somnath Kotur
2020-06-12 13:28 ` [dpdk-dev] [PATCH 15/50] net/bnxt: add HCAPI interface support Somnath Kotur
2020-06-12 13:29 ` [dpdk-dev] [PATCH 16/50] net/bnxt: add core changes for EM and EEM lookups Somnath Kotur
2020-06-12 13:29 ` [dpdk-dev] [PATCH 17/50] net/bnxt: implement support for TCAM access Somnath Kotur
2020-06-12 13:29 ` [dpdk-dev] [PATCH 18/50] net/bnxt: multiple device implementation Somnath Kotur
2020-06-12 13:29 ` [dpdk-dev] [PATCH 19/50] net/bnxt: update identifier with remap support Somnath Kotur
2020-06-12 13:29 ` [dpdk-dev] [PATCH 20/50] net/bnxt: update RM with residual checker Somnath Kotur
2020-06-12 13:29 ` [dpdk-dev] [PATCH 21/50] net/bnxt: support two level priority for TCAMs Somnath Kotur
2020-06-12 13:29 ` [dpdk-dev] [PATCH 22/50] net/bnxt: support EM and TCAM lookup with table scope Somnath Kotur
2020-06-12 13:29 ` [dpdk-dev] [PATCH 23/50] net/bnxt: update table get to use new design Somnath Kotur
2020-06-12 13:29 ` [dpdk-dev] [PATCH 24/50] net/bnxt: update RM to support HCAPI only Somnath Kotur
2020-06-12 13:29 ` [dpdk-dev] [PATCH 25/50] net/bnxt: remove table scope from session Somnath Kotur
2020-06-12 13:29 ` [dpdk-dev] [PATCH 26/50] net/bnxt: add external action alloc and free Somnath Kotur
2020-06-12 13:29 ` [dpdk-dev] [PATCH 27/50] net/bnxt: align CFA resources with RM Somnath Kotur
2020-06-12 13:29 ` [dpdk-dev] [PATCH 28/50] net/bnxt: implement IF tables set and get Somnath Kotur
2020-06-12 13:29 ` [dpdk-dev] [PATCH 29/50] net/bnxt: add TF register and unregister Somnath Kotur
2020-06-12 13:29 ` [dpdk-dev] [PATCH 30/50] net/bnxt: add global config set and get APIs Somnath Kotur
2020-06-12 13:29 ` [dpdk-dev] [PATCH 31/50] net/bnxt: add support for EEM System memory Somnath Kotur
2020-06-12 13:29 ` [dpdk-dev] [PATCH 32/50] net/bnxt: integrate with the latest tf_core library Somnath Kotur
2020-06-12 13:29 ` [dpdk-dev] [PATCH 33/50] net/bnxt: add support for internal encap records Somnath Kotur
2020-06-12 13:29 ` [dpdk-dev] [PATCH 34/50] net/bnxt: add support for if table processing Somnath Kotur
2020-06-12 13:29 ` [dpdk-dev] [PATCH 35/50] net/bnxt: disable vector mode in tx direction when truflow is enabled Somnath Kotur
2020-06-12 13:29 ` [dpdk-dev] [PATCH 36/50] net/bnxt: add index opcode and index operand mapper table Somnath Kotur
2020-06-12 13:29 ` [dpdk-dev] [PATCH 37/50] net/bnxt: add support for global resource templates Somnath Kotur
2020-06-12 13:29 ` [dpdk-dev] [PATCH 38/50] net/bnxt: add support for internal exact match entries Somnath Kotur
2020-06-12 13:29 ` [dpdk-dev] [PATCH 39/50] net/bnxt: add support for conditional execution of mapper tables Somnath Kotur
2020-06-12 13:29 ` [dpdk-dev] [PATCH 40/50] net/bnxt: enable HWRM_PORT_MAC_QCFG for trusted vf Somnath Kotur
2020-06-12 13:29 ` [dpdk-dev] [PATCH 41/50] net/bnxt: enhancements for port db Somnath Kotur
2020-06-12 13:29 ` [dpdk-dev] [PATCH 42/50] net/bnxt: fix for VF to VFR conduit Somnath Kotur
2020-06-12 13:29 ` [dpdk-dev] [PATCH 43/50] net/bnxt: fix to parse representor along with other dev-args Somnath Kotur
2020-06-12 13:29 ` [dpdk-dev] [PATCH 44/50] net/bnxt: fill mapper parameters with default rules info Somnath Kotur
2020-06-12 13:29 ` Somnath Kotur [this message]
2020-06-12 13:29 ` [dpdk-dev] [PATCH 46/50] net/bnxt: create default flow rules for the VF-rep conduit Somnath Kotur
2020-06-12 13:29 ` [dpdk-dev] [PATCH 47/50] net/bnxt: add ingress & egress port default rules Somnath Kotur
2020-06-12 13:29 ` [dpdk-dev] [PATCH 48/50] net/bnxt: fill cfa_action in the tx buffer descriptor properly Somnath Kotur
2020-06-12 13:29 ` [dpdk-dev] [PATCH 49/50] net/bnxt: support for ULP Flow counter Manager Somnath Kotur
2020-06-12 13:29 ` [dpdk-dev] [PATCH 50/50] net/bnxt: Add support for flow query with action_type COUNT Somnath Kotur
2020-07-01 6:51 ` [dpdk-dev] [PATCH v2 00/51] add features for host-based flow management Ajit Khaparde
2020-07-01 6:51 ` [dpdk-dev] [PATCH v2 01/51] net/bnxt: add basic infrastructure for VF representors Ajit Khaparde
2020-07-01 6:51 ` [dpdk-dev] [PATCH v2 02/51] net/bnxt: add support for VF-reps data path Ajit Khaparde
2020-07-01 6:51 ` [dpdk-dev] [PATCH v2 03/51] net/bnxt: get IDs for VF-Rep endpoint Ajit Khaparde
2020-07-01 6:51 ` [dpdk-dev] [PATCH v2 04/51] net/bnxt: initialize parent PF information Ajit Khaparde
2020-07-01 6:51 ` [dpdk-dev] [PATCH v2 05/51] net/bnxt: modify port db dev interface Ajit Khaparde
2020-07-01 6:51 ` [dpdk-dev] [PATCH v2 06/51] net/bnxt: get port and function info Ajit Khaparde
2020-07-01 6:51 ` [dpdk-dev] [PATCH v2 07/51] net/bnxt: add support for hwrm port phy qcaps Ajit Khaparde
2020-07-01 6:51 ` [dpdk-dev] [PATCH v2 08/51] net/bnxt: modify port db to handle more info Ajit Khaparde
2020-07-01 6:51 ` [dpdk-dev] [PATCH v2 09/51] net/bnxt: add support for exact match Ajit Khaparde
2020-07-01 6:51 ` [dpdk-dev] [PATCH v2 10/51] net/bnxt: modify EM insert and delete to use HWRM direct Ajit Khaparde
2020-07-01 6:51 ` [dpdk-dev] [PATCH v2 11/51] net/bnxt: add multi device support Ajit Khaparde
2020-07-01 6:51 ` [dpdk-dev] [PATCH v2 12/51] net/bnxt: support bulk table get and mirror Ajit Khaparde
2020-07-01 6:51 ` [dpdk-dev] [PATCH v2 13/51] net/bnxt: update multi device design support Ajit Khaparde
2020-07-01 6:51 ` [dpdk-dev] [PATCH v2 14/51] net/bnxt: support two-level priority for TCAMs Ajit Khaparde
2020-07-01 6:51 ` [dpdk-dev] [PATCH v2 15/51] net/bnxt: add HCAPI interface support Ajit Khaparde
2020-07-01 6:51 ` [dpdk-dev] [PATCH v2 16/51] net/bnxt: add core changes for EM and EEM lookups Ajit Khaparde
2020-07-01 6:51 ` [dpdk-dev] [PATCH v2 17/51] net/bnxt: implement support for TCAM access Ajit Khaparde
2020-07-01 6:51 ` [dpdk-dev] [PATCH v2 18/51] net/bnxt: multiple device implementation Ajit Khaparde
2020-07-01 6:51 ` [dpdk-dev] [PATCH v2 19/51] net/bnxt: update identifier with remap support Ajit Khaparde
2020-07-01 6:51 ` [dpdk-dev] [PATCH v2 20/51] net/bnxt: update RM with residual checker Ajit Khaparde
2020-07-01 6:51 ` [dpdk-dev] [PATCH v2 21/51] net/bnxt: support two level priority for TCAMs Ajit Khaparde
2020-07-01 6:51 ` [dpdk-dev] [PATCH v2 22/51] net/bnxt: support EM and TCAM lookup with table scope Ajit Khaparde
2020-07-01 6:51 ` [dpdk-dev] [PATCH v2 23/51] net/bnxt: update table get to use new design Ajit Khaparde
2020-07-01 6:51 ` [dpdk-dev] [PATCH v2 24/51] net/bnxt: update RM to support HCAPI only Ajit Khaparde
2020-07-01 6:51 ` [dpdk-dev] [PATCH v2 25/51] net/bnxt: remove table scope from session Ajit Khaparde
2020-07-01 6:51 ` [dpdk-dev] [PATCH v2 26/51] net/bnxt: add external action alloc and free Ajit Khaparde
2020-07-01 6:51 ` [dpdk-dev] [PATCH v2 27/51] net/bnxt: align CFA resources with RM Ajit Khaparde
2020-07-01 6:51 ` [dpdk-dev] [PATCH v2 28/51] net/bnxt: implement IF tables set and get Ajit Khaparde
2020-07-01 6:51 ` [dpdk-dev] [PATCH v2 29/51] net/bnxt: add TF register and unregister Ajit Khaparde
2020-07-01 6:51 ` [dpdk-dev] [PATCH v2 30/51] net/bnxt: add global config set and get APIs Ajit Khaparde
2020-07-01 6:51 ` [dpdk-dev] [PATCH v2 31/51] net/bnxt: add support for EEM System memory Ajit Khaparde
2020-07-01 6:51 ` [dpdk-dev] [PATCH v2 32/51] net/bnxt: integrate with the latest tf core changes Ajit Khaparde
2020-07-01 6:51 ` [dpdk-dev] [PATCH v2 33/51] net/bnxt: add support for internal encap records Ajit Khaparde
2020-07-01 6:51 ` [dpdk-dev] [PATCH v2 34/51] net/bnxt: add support for if table processing Ajit Khaparde
2020-07-01 6:51 ` [dpdk-dev] [PATCH v2 35/51] net/bnxt: disable Tx vector mode if truflow is enabled Ajit Khaparde
2020-07-01 6:51 ` [dpdk-dev] [PATCH v2 36/51] net/bnxt: add index opcode and operand to mapper table Ajit Khaparde
2020-07-01 6:51 ` [dpdk-dev] [PATCH v2 37/51] net/bnxt: add support for global resource templates Ajit Khaparde
2020-07-01 6:51 ` [dpdk-dev] [PATCH v2 38/51] net/bnxt: add support for internal exact match entries Ajit Khaparde
2020-07-01 6:52 ` [dpdk-dev] [PATCH v2 39/51] net/bnxt: add support for conditional execution of mapper tables Ajit Khaparde
2020-07-01 6:52 ` [dpdk-dev] [PATCH v2 40/51] net/bnxt: enable port MAC qcfg command for trusted VF Ajit Khaparde
2020-07-01 6:52 ` [dpdk-dev] [PATCH v2 41/51] net/bnxt: enhancements for port db Ajit Khaparde
2020-07-01 6:52 ` [dpdk-dev] [PATCH v2 42/51] net/bnxt: manage VF to VFR conduit Ajit Khaparde
2020-07-01 6:52 ` [dpdk-dev] [PATCH v2 43/51] net/bnxt: parse representor along with other dev-args Ajit Khaparde
2020-07-01 6:52 ` [dpdk-dev] [PATCH v2 44/51] net/bnxt: fill mapper parameters with default rules info Ajit Khaparde
2020-07-01 6:52 ` [dpdk-dev] [PATCH v2 45/51] net/bnxt: add VF-rep and stat templates Ajit Khaparde
2020-07-01 6:52 ` [dpdk-dev] [PATCH v2 46/51] net/bnxt: create default flow rules for the VF-rep conduit Ajit Khaparde
2020-07-01 6:52 ` [dpdk-dev] [PATCH v2 47/51] net/bnxt: add port default rules for ingress and egress Ajit Khaparde
2020-07-01 6:52 ` [dpdk-dev] [PATCH v2 48/51] net/bnxt: fill cfa action in the Tx descriptor Ajit Khaparde
2020-07-01 6:52 ` [dpdk-dev] [PATCH v2 49/51] net/bnxt: add ULP Flow counter Manager Ajit Khaparde
2020-07-01 6:52 ` [dpdk-dev] [PATCH v2 50/51] net/bnxt: add support for count action in flow query Ajit Khaparde
2020-07-01 6:52 ` [dpdk-dev] [PATCH v2 51/51] doc: update release notes Ajit Khaparde
2020-07-01 14:26 ` [dpdk-dev] [PATCH v2 00/51] add features for host-based flow management Ajit Khaparde
2020-07-01 21:31 ` Ferruh Yigit
2020-07-02 4:10 ` [dpdk-dev] [PATCH v3 " Ajit Khaparde
2020-07-02 4:10 ` [dpdk-dev] [PATCH v3 01/51] net/bnxt: add basic infrastructure for VF reps Ajit Khaparde
2020-07-02 4:10 ` [dpdk-dev] [PATCH v3 02/51] net/bnxt: add support for VF-reps data path Ajit Khaparde
2020-07-02 4:10 ` [dpdk-dev] [PATCH v3 03/51] net/bnxt: get IDs for VF-Rep endpoint Ajit Khaparde
2020-07-02 4:10 ` [dpdk-dev] [PATCH v3 04/51] net/bnxt: initialize parent PF information Ajit Khaparde
2020-07-02 4:10 ` [dpdk-dev] [PATCH v3 05/51] net/bnxt: modify port db dev interface Ajit Khaparde
2020-07-02 4:10 ` [dpdk-dev] [PATCH v3 06/51] net/bnxt: get port and function info Ajit Khaparde
2020-07-02 4:10 ` [dpdk-dev] [PATCH v3 07/51] net/bnxt: add support for hwrm port phy qcaps Ajit Khaparde
2020-07-02 4:10 ` [dpdk-dev] [PATCH v3 08/51] net/bnxt: modify port db to handle more info Ajit Khaparde
2020-07-02 4:10 ` [dpdk-dev] [PATCH v3 09/51] net/bnxt: add support for exact match Ajit Khaparde
2020-07-02 4:10 ` [dpdk-dev] [PATCH v3 10/51] net/bnxt: modify EM insert and delete to use HWRM direct Ajit Khaparde
2020-07-02 4:10 ` [dpdk-dev] [PATCH v3 11/51] net/bnxt: add multi device support Ajit Khaparde
2020-07-02 4:10 ` [dpdk-dev] [PATCH v3 12/51] net/bnxt: support bulk table get and mirror Ajit Khaparde
2020-07-02 4:10 ` [dpdk-dev] [PATCH v3 13/51] net/bnxt: update multi device design support Ajit Khaparde
2020-07-02 4:10 ` [dpdk-dev] [PATCH v3 14/51] net/bnxt: support two-level priority for TCAMs Ajit Khaparde
2020-07-02 4:10 ` [dpdk-dev] [PATCH v3 15/51] net/bnxt: add HCAPI interface support Ajit Khaparde
2020-07-02 4:10 ` [dpdk-dev] [PATCH v3 16/51] net/bnxt: add core changes for EM and EEM lookups Ajit Khaparde
2020-07-02 4:11 ` [dpdk-dev] [PATCH v3 17/51] net/bnxt: implement support for TCAM access Ajit Khaparde
2020-07-02 4:11 ` [dpdk-dev] [PATCH v3 18/51] net/bnxt: multiple device implementation Ajit Khaparde
2020-07-02 4:11 ` [dpdk-dev] [PATCH v3 19/51] net/bnxt: update identifier with remap support Ajit Khaparde
2020-07-02 4:11 ` [dpdk-dev] [PATCH v3 20/51] net/bnxt: update RM with residual checker Ajit Khaparde
2020-07-02 4:11 ` [dpdk-dev] [PATCH v3 21/51] net/bnxt: support two level priority for TCAMs Ajit Khaparde
2020-07-02 4:11 ` [dpdk-dev] [PATCH v3 22/51] net/bnxt: support EM and TCAM lookup with table scope Ajit Khaparde
2020-07-02 4:11 ` [dpdk-dev] [PATCH v3 23/51] net/bnxt: update table get to use new design Ajit Khaparde
2020-07-02 4:11 ` [dpdk-dev] [PATCH v3 24/51] net/bnxt: update RM to support HCAPI only Ajit Khaparde
2020-07-02 4:11 ` [dpdk-dev] [PATCH v3 25/51] net/bnxt: remove table scope from session Ajit Khaparde
2020-07-02 4:11 ` [dpdk-dev] [PATCH v3 26/51] net/bnxt: add external action alloc and free Ajit Khaparde
2020-07-02 4:11 ` [dpdk-dev] [PATCH v3 27/51] net/bnxt: align CFA resources with RM Ajit Khaparde
2020-07-02 4:11 ` [dpdk-dev] [PATCH v3 28/51] net/bnxt: implement IF tables set and get Ajit Khaparde
2020-07-02 4:11 ` [dpdk-dev] [PATCH v3 29/51] net/bnxt: add TF register and unregister Ajit Khaparde
2020-07-02 4:11 ` [dpdk-dev] [PATCH v3 30/51] net/bnxt: add global config set and get APIs Ajit Khaparde
2020-07-02 4:11 ` [dpdk-dev] [PATCH v3 31/51] net/bnxt: add support for EEM System memory Ajit Khaparde
2020-07-02 4:11 ` [dpdk-dev] [PATCH v3 32/51] net/bnxt: integrate with the latest tf core changes Ajit Khaparde
2020-07-02 4:11 ` [dpdk-dev] [PATCH v3 33/51] net/bnxt: add support for internal encap records Ajit Khaparde
2020-07-02 4:11 ` [dpdk-dev] [PATCH v3 34/51] net/bnxt: add support for if table processing Ajit Khaparde
2020-07-02 4:11 ` [dpdk-dev] [PATCH v3 35/51] net/bnxt: disable Tx vector mode if truflow is enabled Ajit Khaparde
2020-07-02 4:11 ` [dpdk-dev] [PATCH v3 36/51] net/bnxt: add index opcode and operand to mapper table Ajit Khaparde
2020-07-02 4:11 ` [dpdk-dev] [PATCH v3 37/51] net/bnxt: add support for global resource templates Ajit Khaparde
2020-07-02 4:11 ` [dpdk-dev] [PATCH v3 38/51] net/bnxt: add support for internal exact match entries Ajit Khaparde
2020-07-02 4:11 ` [dpdk-dev] [PATCH v3 39/51] net/bnxt: add conditional execution of mapper tables Ajit Khaparde
2020-07-02 4:11 ` [dpdk-dev] [PATCH v3 40/51] net/bnxt: enable port MAC qcfg for trusted VF Ajit Khaparde
2020-07-02 4:11 ` [dpdk-dev] [PATCH v3 41/51] net/bnxt: enhancements for port db Ajit Khaparde
2020-07-02 4:11 ` [dpdk-dev] [PATCH v3 42/51] net/bnxt: manage VF to VFR conduit Ajit Khaparde
2020-07-02 4:11 ` [dpdk-dev] [PATCH v3 43/51] net/bnxt: parse reps along with other dev-args Ajit Khaparde
2020-07-02 4:11 ` [dpdk-dev] [PATCH v3 44/51] net/bnxt: fill mapper parameters with default rules Ajit Khaparde
2020-07-02 4:11 ` [dpdk-dev] [PATCH v3 45/51] net/bnxt: add VF-rep and stat templates Ajit Khaparde
2020-07-02 4:11 ` [dpdk-dev] [PATCH v3 46/51] net/bnxt: create default flow rules for the VF-rep Ajit Khaparde
2020-07-02 4:11 ` [dpdk-dev] [PATCH v3 47/51] net/bnxt: add port default rules for ingress and egress Ajit Khaparde
2020-07-02 4:11 ` [dpdk-dev] [PATCH v3 48/51] net/bnxt: fill cfa action in the Tx descriptor Ajit Khaparde
2020-07-02 4:11 ` [dpdk-dev] [PATCH v3 49/51] net/bnxt: add ULP Flow counter Manager Ajit Khaparde
2020-07-02 4:11 ` [dpdk-dev] [PATCH v3 50/51] net/bnxt: add support for count action in flow query Ajit Khaparde
2020-07-02 4:11 ` [dpdk-dev] [PATCH v3 51/51] doc: update release notes Ajit Khaparde
2020-07-02 23:27 ` [dpdk-dev] [PATCH v4 00/51] add features for host-based flow management Ajit Khaparde
2020-07-02 23:27 ` [dpdk-dev] [PATCH v4 01/51] net/bnxt: add basic infrastructure for VF reps Ajit Khaparde
2020-07-02 23:27 ` [dpdk-dev] [PATCH v4 02/51] net/bnxt: add support for VF-reps data path Ajit Khaparde
2020-07-02 23:27 ` [dpdk-dev] [PATCH v4 03/51] net/bnxt: get IDs for VF-Rep endpoint Ajit Khaparde
2020-07-02 23:27 ` [dpdk-dev] [PATCH v4 04/51] net/bnxt: initialize parent PF information Ajit Khaparde
2020-07-02 23:27 ` [dpdk-dev] [PATCH v4 05/51] net/bnxt: modify port db dev interface Ajit Khaparde
2020-07-02 23:27 ` [dpdk-dev] [PATCH v4 06/51] net/bnxt: get port and function info Ajit Khaparde
2020-07-02 23:27 ` [dpdk-dev] [PATCH v4 07/51] net/bnxt: add support for hwrm port phy qcaps Ajit Khaparde
2020-07-02 23:27 ` [dpdk-dev] [PATCH v4 08/51] net/bnxt: modify port db to handle more info Ajit Khaparde
2020-07-02 23:27 ` [dpdk-dev] [PATCH v4 09/51] net/bnxt: add support for exact match Ajit Khaparde
2020-07-02 23:27 ` [dpdk-dev] [PATCH v4 10/51] net/bnxt: modify EM insert and delete to use HWRM direct Ajit Khaparde
2020-07-02 23:27 ` [dpdk-dev] [PATCH v4 11/51] net/bnxt: add multi device support Ajit Khaparde
2020-07-02 23:27 ` [dpdk-dev] [PATCH v4 12/51] net/bnxt: support bulk table get and mirror Ajit Khaparde
2020-07-02 23:28 ` [dpdk-dev] [PATCH v4 13/51] net/bnxt: update multi device design support Ajit Khaparde
2020-07-02 23:28 ` [dpdk-dev] [PATCH v4 14/51] net/bnxt: support two-level priority for TCAMs Ajit Khaparde
2020-07-02 23:28 ` [dpdk-dev] [PATCH v4 15/51] net/bnxt: add HCAPI interface support Ajit Khaparde
2020-07-02 23:28 ` [dpdk-dev] [PATCH v4 16/51] net/bnxt: add core changes for EM and EEM lookups Ajit Khaparde
2020-07-02 23:28 ` [dpdk-dev] [PATCH v4 17/51] net/bnxt: implement support for TCAM access Ajit Khaparde
2020-07-02 23:28 ` [dpdk-dev] [PATCH v4 18/51] net/bnxt: multiple device implementation Ajit Khaparde
2020-07-02 23:28 ` [dpdk-dev] [PATCH v4 19/51] net/bnxt: update identifier with remap support Ajit Khaparde
2020-07-02 23:28 ` [dpdk-dev] [PATCH v4 20/51] net/bnxt: update RM with residual checker Ajit Khaparde
2020-07-02 23:28 ` [dpdk-dev] [PATCH v4 21/51] net/bnxt: support two level priority for TCAMs Ajit Khaparde
2020-07-02 23:28 ` [dpdk-dev] [PATCH v4 22/51] net/bnxt: support EM and TCAM lookup with table scope Ajit Khaparde
2020-07-02 23:28 ` [dpdk-dev] [PATCH v4 23/51] net/bnxt: update table get to use new design Ajit Khaparde
2020-07-02 23:28 ` [dpdk-dev] [PATCH v4 24/51] net/bnxt: update RM to support HCAPI only Ajit Khaparde
2020-07-02 23:28 ` [dpdk-dev] [PATCH v4 25/51] net/bnxt: remove table scope from session Ajit Khaparde
2020-07-02 23:28 ` [dpdk-dev] [PATCH v4 26/51] net/bnxt: add external action alloc and free Ajit Khaparde
2020-07-02 23:28 ` [dpdk-dev] [PATCH v4 27/51] net/bnxt: align CFA resources with RM Ajit Khaparde
2020-07-02 23:28 ` [dpdk-dev] [PATCH v4 28/51] net/bnxt: implement IF tables set and get Ajit Khaparde
2020-07-02 23:28 ` [dpdk-dev] [PATCH v4 29/51] net/bnxt: add TF register and unregister Ajit Khaparde
2020-07-02 23:28 ` [dpdk-dev] [PATCH v4 30/51] net/bnxt: add global config set and get APIs Ajit Khaparde
2020-07-02 23:28 ` [dpdk-dev] [PATCH v4 31/51] net/bnxt: add support for EEM System memory Ajit Khaparde
2020-07-02 23:28 ` [dpdk-dev] [PATCH v4 32/51] net/bnxt: integrate with the latest tf core changes Ajit Khaparde
2020-07-02 23:28 ` [dpdk-dev] [PATCH v4 33/51] net/bnxt: add support for internal encap records Ajit Khaparde
2020-07-02 23:28 ` [dpdk-dev] [PATCH v4 34/51] net/bnxt: add support for if table processing Ajit Khaparde
2020-07-02 23:28 ` [dpdk-dev] [PATCH v4 35/51] net/bnxt: disable Tx vector mode if truflow is enabled Ajit Khaparde
2020-07-02 23:28 ` [dpdk-dev] [PATCH v4 36/51] net/bnxt: add index opcode and operand to mapper table Ajit Khaparde
2020-07-02 23:28 ` [dpdk-dev] [PATCH v4 37/51] net/bnxt: add support for global resource templates Ajit Khaparde
2020-07-02 23:28 ` [dpdk-dev] [PATCH v4 38/51] net/bnxt: add support for internal exact match entries Ajit Khaparde
2020-07-02 23:28 ` [dpdk-dev] [PATCH v4 39/51] net/bnxt: add support for conditional execution of mapper tables Ajit Khaparde
2020-07-02 23:28 ` [dpdk-dev] [PATCH v4 40/51] net/bnxt: enable port MAC qcfg command for trusted VF Ajit Khaparde
2020-07-02 23:28 ` [dpdk-dev] [PATCH v4 41/51] net/bnxt: enhancements for port db Ajit Khaparde
2020-07-02 23:28 ` [dpdk-dev] [PATCH v4 42/51] net/bnxt: manage VF to VFR conduit Ajit Khaparde
2020-07-02 23:28 ` [dpdk-dev] [PATCH v4 43/51] net/bnxt: parse reps along with other dev-args Ajit Khaparde
2020-07-02 23:28 ` [dpdk-dev] [PATCH v4 44/51] net/bnxt: fill mapper parameters with default rules Ajit Khaparde
2020-07-02 23:28 ` [dpdk-dev] [PATCH v4 45/51] net/bnxt: add VF-rep and stat templates Ajit Khaparde
2020-07-02 23:28 ` [dpdk-dev] [PATCH v4 46/51] net/bnxt: create default flow rules for the VF-rep Ajit Khaparde
2020-07-02 23:28 ` [dpdk-dev] [PATCH v4 47/51] net/bnxt: add port default rules for ingress and egress Ajit Khaparde
2020-07-02 23:28 ` [dpdk-dev] [PATCH v4 48/51] net/bnxt: fill cfa action in the Tx descriptor Ajit Khaparde
2020-07-02 23:28 ` [dpdk-dev] [PATCH v4 49/51] net/bnxt: add ULP Flow counter Manager Ajit Khaparde
2020-07-02 23:28 ` [dpdk-dev] [PATCH v4 50/51] net/bnxt: add support for count action in flow query Ajit Khaparde
2020-07-02 23:28 ` [dpdk-dev] [PATCH v4 51/51] doc: update release notes Ajit Khaparde
2020-07-03 21:01 ` [dpdk-dev] [PATCH v5 00/51] net/bnxt: add features for host-based flow management Ajit Khaparde
2020-07-03 21:01 ` [dpdk-dev] [PATCH v5 01/51] net/bnxt: add basic infrastructure for VF reps Ajit Khaparde
2020-07-06 10:07 ` Ferruh Yigit
2020-07-06 14:04 ` Somnath Kotur
2020-07-06 14:14 ` Ajit Khaparde
2020-07-06 18:35 ` Ferruh Yigit
2020-07-03 21:01 ` [dpdk-dev] [PATCH v5 02/51] net/bnxt: add support for VF-reps data path Ajit Khaparde
2020-07-03 21:01 ` [dpdk-dev] [PATCH v5 03/51] net/bnxt: get IDs for VF-Rep endpoint Ajit Khaparde
2020-07-03 21:01 ` [dpdk-dev] [PATCH v5 04/51] net/bnxt: initialize parent PF information Ajit Khaparde
2020-07-03 21:01 ` [dpdk-dev] [PATCH v5 05/51] net/bnxt: modify port db dev interface Ajit Khaparde
2020-07-03 21:01 ` [dpdk-dev] [PATCH v5 06/51] net/bnxt: get port and function info Ajit Khaparde
2020-07-03 21:01 ` [dpdk-dev] [PATCH v5 07/51] net/bnxt: add support for hwrm port phy qcaps Ajit Khaparde
2020-07-03 21:01 ` [dpdk-dev] [PATCH v5 08/51] net/bnxt: modify port db to handle more info Ajit Khaparde
2020-07-03 21:01 ` [dpdk-dev] [PATCH v5 09/51] net/bnxt: add support for exact match Ajit Khaparde
2020-07-03 21:01 ` [dpdk-dev] [PATCH v5 10/51] net/bnxt: use HWRM direct for EM insert and delete Ajit Khaparde
2020-07-06 18:47 ` Ferruh Yigit
2020-07-06 19:11 ` Ferruh Yigit
2020-07-03 21:01 ` [dpdk-dev] [PATCH v5 11/51] net/bnxt: add multi device support Ajit Khaparde
2020-07-03 21:01 ` [dpdk-dev] [PATCH v5 12/51] net/bnxt: support bulk table get and mirror Ajit Khaparde
2020-07-03 21:01 ` [dpdk-dev] [PATCH v5 13/51] net/bnxt: update multi device design support Ajit Khaparde
2020-07-03 21:01 ` [dpdk-dev] [PATCH v5 14/51] net/bnxt: support two-level priority for TCAMs Ajit Khaparde
2020-07-03 21:01 ` [dpdk-dev] [PATCH v5 15/51] net/bnxt: add HCAPI interface support Ajit Khaparde
2020-07-07 8:03 ` Ferruh Yigit
2020-07-03 21:01 ` [dpdk-dev] [PATCH v5 16/51] net/bnxt: add core changes for EM and EEM lookups Ajit Khaparde
2020-07-07 8:08 ` Ferruh Yigit
2020-07-03 21:01 ` [dpdk-dev] [PATCH v5 17/51] net/bnxt: implement support for TCAM access Ajit Khaparde
2020-07-03 21:01 ` [dpdk-dev] [PATCH v5 18/51] net/bnxt: multiple device implementation Ajit Khaparde
2020-07-03 21:01 ` [dpdk-dev] [PATCH v5 19/51] net/bnxt: update identifier with remap support Ajit Khaparde
2020-07-03 21:01 ` [dpdk-dev] [PATCH v5 20/51] net/bnxt: update RM with residual checker Ajit Khaparde
2020-07-03 21:01 ` [dpdk-dev] [PATCH v5 21/51] net/bnxt: support two level priority for TCAMs Ajit Khaparde
2020-07-03 21:01 ` [dpdk-dev] [PATCH v5 22/51] net/bnxt: use table scope for EM and TCAM lookup Ajit Khaparde
2020-07-03 21:01 ` [dpdk-dev] [PATCH v5 23/51] net/bnxt: update table get to use new design Ajit Khaparde
2020-07-03 21:01 ` [dpdk-dev] [PATCH v5 24/51] net/bnxt: update RM to support HCAPI only Ajit Khaparde
2020-07-03 21:01 ` [dpdk-dev] [PATCH v5 25/51] net/bnxt: remove table scope from session Ajit Khaparde
2020-07-03 21:01 ` [dpdk-dev] [PATCH v5 26/51] net/bnxt: add external action alloc and free Ajit Khaparde
2020-07-03 21:01 ` [dpdk-dev] [PATCH v5 27/51] net/bnxt: align CFA resources with RM Ajit Khaparde
2020-07-03 21:01 ` [dpdk-dev] [PATCH v5 28/51] net/bnxt: implement IF tables set and get Ajit Khaparde
2020-07-03 21:01 ` [dpdk-dev] [PATCH v5 29/51] net/bnxt: add TF register and unregister Ajit Khaparde
2020-07-03 21:01 ` [dpdk-dev] [PATCH v5 30/51] net/bnxt: add global config set and get APIs Ajit Khaparde
2020-07-03 21:01 ` [dpdk-dev] [PATCH v5 31/51] net/bnxt: add support for EEM System memory Ajit Khaparde
2020-07-03 21:01 ` [dpdk-dev] [PATCH v5 32/51] net/bnxt: integrate with the latest tf core changes Ajit Khaparde
2020-07-03 21:01 ` [dpdk-dev] [PATCH v5 33/51] net/bnxt: add support for internal encap records Ajit Khaparde
2020-07-03 21:01 ` [dpdk-dev] [PATCH v5 34/51] net/bnxt: add support for if table processing Ajit Khaparde
2020-07-03 21:01 ` [dpdk-dev] [PATCH v5 35/51] net/bnxt: disable Tx vector mode if truflow is set Ajit Khaparde
2020-07-03 21:01 ` [dpdk-dev] [PATCH v5 36/51] net/bnxt: add index opcode and operand to mapper table Ajit Khaparde
2020-07-03 21:01 ` [dpdk-dev] [PATCH v5 37/51] net/bnxt: add support for global resource templates Ajit Khaparde
2020-07-03 21:01 ` [dpdk-dev] [PATCH v5 38/51] net/bnxt: add support for internal exact match Ajit Khaparde
2020-07-03 21:01 ` [dpdk-dev] [PATCH v5 39/51] net/bnxt: add conditional execution of mapper tables Ajit Khaparde
2020-07-03 21:01 ` [dpdk-dev] [PATCH v5 40/51] net/bnxt: allow port MAC qcfg command for trusted VF Ajit Khaparde
2020-07-03 21:02 ` [dpdk-dev] [PATCH v5 41/51] net/bnxt: enhancements for port db Ajit Khaparde
2020-07-03 21:02 ` [dpdk-dev] [PATCH v5 42/51] net/bnxt: manage VF to VFR conduit Ajit Khaparde
2020-07-03 21:02 ` [dpdk-dev] [PATCH v5 43/51] net/bnxt: parse reps along with other dev-args Ajit Khaparde
2020-07-03 21:02 ` [dpdk-dev] [PATCH v5 44/51] net/bnxt: fill mapper parameters with default rules Ajit Khaparde
2020-07-03 21:02 ` [dpdk-dev] [PATCH v5 45/51] net/bnxt: add VF-rep and stat templates Ajit Khaparde
2020-07-03 21:02 ` [dpdk-dev] [PATCH v5 46/51] net/bnxt: create default flow rules for the VF-rep Ajit Khaparde
2020-07-03 21:02 ` [dpdk-dev] [PATCH v5 47/51] net/bnxt: add port default rules for ingress and egress Ajit Khaparde
2020-07-03 21:02 ` [dpdk-dev] [PATCH v5 48/51] net/bnxt: fill cfa action in the Tx descriptor Ajit Khaparde
2020-07-03 21:02 ` [dpdk-dev] [PATCH v5 49/51] net/bnxt: add ULP Flow counter Manager Ajit Khaparde
2020-07-03 21:02 ` [dpdk-dev] [PATCH v5 50/51] net/bnxt: add support for count action in flow query Ajit Khaparde
2020-07-03 21:02 ` [dpdk-dev] [PATCH v5 51/51] doc: update release notes Ajit Khaparde
2020-07-06 1:47 ` [dpdk-dev] [PATCH v5 00/51] net/bnxt: add features for host-based flow management Ajit Khaparde
2020-07-06 10:10 ` Ferruh Yigit
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