From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id ED086A00BE; Fri, 12 Jun 2020 23:27:59 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 46D991BFF6; Fri, 12 Jun 2020 23:26:34 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by dpdk.org (Postfix) with ESMTP id EA9361BF81 for ; Fri, 12 Jun 2020 23:26:25 +0200 (CEST) IronPort-SDR: HlLZbSy1r/ShHhS0JIim6u+MZaBzaVLHsp2T4jWutbML02g53ZmeBJY9aoTkos67OTNu7gNxEN X1tHGjCHmgEg== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jun 2020 14:26:25 -0700 IronPort-SDR: gu/bzvRqSqLuQe12+Y2VDhpsJzFWzTK/x2ErX4jgdRfc1y+H0uDwMJv9FzXMtcHGtYESpVj4w7 GUsoHJOqAe1g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,504,1583222400"; d="scan'208";a="272035816" Received: from txasoft-yocto.an.intel.com ([10.123.72.192]) by orsmga003.jf.intel.com with ESMTP; 12 Jun 2020 14:26:24 -0700 From: "McDaniel, Timothy" To: jerinj@marvell.com Cc: dev@dpdk.org, gage.eads@intel.com, harry.van.haaren@intel.com Date: Fri, 12 Jun 2020 16:24:16 -0500 Message-Id: <20200612212434.6852-10-timothy.mcdaniel@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20200612212434.6852-1-timothy.mcdaniel@intel.com> References: <20200612212434.6852-1-timothy.mcdaniel@intel.com> Subject: [dpdk-dev] [PATCH 09/27] event/dlb: inline functions used in multiple files X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Change-Id: I61196d9c19cd2add26b6600fb42588ef523febac Signed-off-by: McDaniel, Timothy --- drivers/event/dlb/dlb_inline_fns.h | 80 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) create mode 100644 drivers/event/dlb/dlb_inline_fns.h diff --git a/drivers/event/dlb/dlb_inline_fns.h b/drivers/event/dlb/dlb_inline_fns.h new file mode 100644 index 000000000..0f036f6ee --- /dev/null +++ b/drivers/event/dlb/dlb_inline_fns.h @@ -0,0 +1,80 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2016-2020 Intel Corporation + */ + +#include "rte_memcpy.h" +#include "rte_io.h" + +/* Inline functions required in more than one source file. + */ + +static inline struct dlb_eventdev * +dlb_pmd_priv(const struct rte_eventdev *eventdev) +{ + return eventdev->data->dev_private; +} + +static inline void +dlb_umonitor(volatile void *addr) +{ + asm volatile(".byte 0xf3, 0x0f, 0xae, 0xf7\t\n" + : + : "D" (addr)); +} + +static inline void +dlb_umwait(int state, uint64_t timeout) +{ + uint32_t eax = timeout & UINT32_MAX; + uint32_t edx = timeout >> 32; + + asm volatile(".byte 0xf2, 0x0f, 0xae, 0xf7\t\n" + : + : "D" (state), "a" (eax), "d" (edx)); +} + +static inline void +dlb_movntdq(struct dlb_enqueue_qe *qe4, uint64_t *pp_addr) +{ + /* Move entire 64B cache line of QEs, 128 bits (16B) at a time. */ + long long *_qe = (long long *)qe4; + __v2di src_data0 = (__v2di){_qe[0], _qe[1]}; + __v2di src_data1 = (__v2di){_qe[2], _qe[3]}; + __v2di src_data2 = (__v2di){_qe[4], _qe[5]}; + __v2di src_data3 = (__v2di){_qe[6], _qe[7]}; + + __builtin_ia32_movntdq((__v2di *)pp_addr + 0, (__v2di)src_data0); + rte_wmb(); + __builtin_ia32_movntdq((__v2di *)pp_addr + 1, (__v2di)src_data1); + rte_wmb(); + __builtin_ia32_movntdq((__v2di *)pp_addr + 2, (__v2di)src_data2); + rte_wmb(); + __builtin_ia32_movntdq((__v2di *)pp_addr + 3, (__v2di)src_data3); + rte_wmb(); +} + +static inline void +dlb_movntdq_single(void *qe4, void *pp_addr) +{ + long long *_qe = (long long *)qe4; + __v2di src_data0 = (__v2di){_qe[0], _qe[1]}; + + __builtin_ia32_movntdq((__v2di *)pp_addr, (__v2di)src_data0); +} + +static inline void +dlb_cldemote(void *addr) +{ + /* Load addr into RSI, then demote the cache line of the address + * contained in that register. + */ + asm volatile(".byte 0x0f, 0x1c, 0x06" :: "S" (addr)); +} + +static inline void +dlb_movdir64b(struct dlb_enqueue_qe *qe4, uint64_t *pp_addr) +{ + asm volatile(".byte 0x66, 0x0f, 0x38, 0xf8, 0x02" + : + : "a" (pp_addr), "d" (qe4)); +} -- 2.13.6