From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 593FAA0350; Mon, 22 Jun 2020 09:09:32 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 544241D426; Mon, 22 Jun 2020 09:06:01 +0200 (CEST) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id 753881D42B for ; Mon, 22 Jun 2020 09:05:59 +0200 (CEST) IronPort-SDR: 7YzFGQVecBCBhMOcNfgjsJK7MBg592EpvKxcybtCj/S+m/24dpLvYwjnyLvMgngybbDVJ3r7TN Qcm+2t0Aaofw== X-IronPort-AV: E=McAfee;i="6000,8403,9659"; a="141944803" X-IronPort-AV: E=Sophos;i="5.75,266,1589266800"; d="scan'208";a="141944803" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jun 2020 00:05:59 -0700 IronPort-SDR: ewkoYZtAYyR13Z8EmGl9hNwfSK35SU5vt8qLKa1EaTc7/+kO5eP8vaRg2DL03oUtBSeddq6/fu V1B5OZoC4BTQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,266,1589266800"; d="scan'208";a="384408915" Received: from dpdk.sh.intel.com ([10.239.255.83]) by fmsmga001.fm.intel.com with ESMTP; 22 Jun 2020 00:05:56 -0700 From: Guinan Sun To: dev@dpdk.org Cc: Jeff Guo , Zhao1 Wei , Guinan Sun , Jeff Kirsher , Sasha Neftin Date: Mon, 22 Jun 2020 06:45:47 +0000 Message-Id: <20200622064634.70941-24-guinanx.sun@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200622064634.70941-1-guinanx.sun@intel.com> References: <20200622064634.70941-1-guinanx.sun@intel.com> Subject: [dpdk-dev] [PATCH 23/70] net/e1000/base: remove duplicated codes from 82575 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" These files will improve e1000_82575 codes. Remove the code duplication from e1000_82575 files. Remove the licenses. Clean family specific functions from base. Signed-off-by: Jeff Kirsher Signed-off-by: Sasha Neftin Signed-off-by: Guinan Sun --- drivers/net/e1000/Makefile | 1 + drivers/net/e1000/base/e1000_82575.c | 493 +++++++++------------------ drivers/net/e1000/base/e1000_82575.h | 107 +----- drivers/net/e1000/base/e1000_base.c | 191 +++++++++++ drivers/net/e1000/base/e1000_base.h | 127 +++++++ drivers/net/e1000/base/e1000_hw.h | 1 + drivers/net/e1000/base/e1000_i210.c | 2 +- drivers/net/e1000/base/e1000_i225.c | 2 +- drivers/net/e1000/base/meson.build | 1 + drivers/net/e1000/igb_rxtx.c | 2 +- 10 files changed, 489 insertions(+), 438 deletions(-) create mode 100644 drivers/net/e1000/base/e1000_base.c create mode 100644 drivers/net/e1000/base/e1000_base.h diff --git a/drivers/net/e1000/Makefile b/drivers/net/e1000/Makefile index 82e156ecb..b7f749454 100644 --- a/drivers/net/e1000/Makefile +++ b/drivers/net/e1000/Makefile @@ -60,6 +60,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_E1000_PMD) += e1000_82575.c SRCS-$(CONFIG_RTE_LIBRTE_E1000_PMD) += e1000_i210.c SRCS-$(CONFIG_RTE_LIBRTE_E1000_PMD) += e1000_i225.c SRCS-$(CONFIG_RTE_LIBRTE_E1000_PMD) += e1000_api.c +SRCS-$(CONFIG_RTE_LIBRTE_E1000_PMD) += e1000_base.c SRCS-$(CONFIG_RTE_LIBRTE_E1000_PMD) += e1000_ich8lan.c SRCS-$(CONFIG_RTE_LIBRTE_E1000_PMD) += e1000_logs.c SRCS-$(CONFIG_RTE_LIBRTE_E1000_PMD) += e1000_mac.c diff --git a/drivers/net/e1000/base/e1000_82575.c b/drivers/net/e1000/base/e1000_82575.c index 49c065014..b392d1f2a 100644 --- a/drivers/net/e1000/base/e1000_82575.c +++ b/drivers/net/e1000/base/e1000_82575.c @@ -18,8 +18,6 @@ STATIC s32 e1000_init_phy_params_82575(struct e1000_hw *hw); STATIC s32 e1000_init_mac_params_82575(struct e1000_hw *hw); -STATIC s32 e1000_acquire_phy_82575(struct e1000_hw *hw); -STATIC void e1000_release_phy_82575(struct e1000_hw *hw); STATIC s32 e1000_acquire_nvm_82575(struct e1000_hw *hw); STATIC void e1000_release_nvm_82575(struct e1000_hw *hw); STATIC s32 e1000_check_for_link_82575(struct e1000_hw *hw); @@ -31,6 +29,7 @@ STATIC s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw); STATIC s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset, u16 *data); STATIC s32 e1000_reset_hw_82575(struct e1000_hw *hw); +STATIC s32 e1000_init_hw_82575(struct e1000_hw *hw); STATIC s32 e1000_reset_hw_82580(struct e1000_hw *hw); STATIC s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data); @@ -56,10 +55,8 @@ STATIC s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw, STATIC s32 e1000_get_phy_id_82575(struct e1000_hw *hw); STATIC void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask); STATIC bool e1000_sgmii_active_82575(struct e1000_hw *hw); -STATIC s32 e1000_reset_init_script_82575(struct e1000_hw *hw); STATIC s32 e1000_read_mac_addr_82575(struct e1000_hw *hw); STATIC void e1000_config_collision_dist_82575(struct e1000_hw *hw); -STATIC void e1000_power_down_phy_copper_82575(struct e1000_hw *hw); STATIC void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw); STATIC void e1000_power_up_serdes_link_82575(struct e1000_hw *hw); STATIC s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw); @@ -128,8 +125,8 @@ STATIC bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw) } /** - * e1000_init_phy_params_82575 - Init PHY func ptrs. - * @hw: pointer to the HW structure + * e1000_init_phy_params_82575 - Initialize PHY function ptrs + * @hw: pointer to the HW structure **/ STATIC s32 e1000_init_phy_params_82575(struct e1000_hw *hw) { @@ -147,17 +144,17 @@ STATIC s32 e1000_init_phy_params_82575(struct e1000_hw *hw) goto out; } - phy->ops.power_up = e1000_power_up_phy_copper; - phy->ops.power_down = e1000_power_down_phy_copper_82575; + phy->ops.power_up = e1000_power_up_phy_copper; + phy->ops.power_down = e1000_power_down_phy_copper_base; phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; phy->reset_delay_us = 100; - phy->ops.acquire = e1000_acquire_phy_82575; + phy->ops.acquire = e1000_acquire_phy_base; phy->ops.check_reset_block = e1000_check_reset_block_generic; phy->ops.commit = e1000_phy_sw_reset_generic; phy->ops.get_cfg_done = e1000_get_cfg_done_82575; - phy->ops.release = e1000_release_phy_82575; + phy->ops.release = e1000_release_phy_base; ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT); @@ -204,76 +201,38 @@ STATIC s32 e1000_init_phy_params_82575(struct e1000_hw *hw) case I347AT4_E_PHY_ID: case M88E1112_E_PHY_ID: case M88E1340M_E_PHY_ID: + phy->type = e1000_phy_m88; + phy->ops.check_polarity = e1000_check_polarity_m88; + phy->ops.get_info = e1000_get_phy_info_m88; + phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2; + phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; + break; case M88E1111_I_PHY_ID: phy->type = e1000_phy_m88; phy->ops.check_polarity = e1000_check_polarity_m88; phy->ops.get_info = e1000_get_phy_info_m88; - if (phy->id == I347AT4_E_PHY_ID || - phy->id == M88E1112_E_PHY_ID || - phy->id == M88E1340M_E_PHY_ID) - phy->ops.get_cable_length = - e1000_get_cable_length_m88_gen2; - else if (phy->id == M88E1543_E_PHY_ID || - phy->id == M88E1512_E_PHY_ID) - phy->ops.get_cable_length = - e1000_get_cable_length_m88_gen2; - else - phy->ops.get_cable_length = e1000_get_cable_length_m88; + phy->ops.get_cable_length = e1000_get_cable_length_m88; phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88; - /* Check if this PHY is confgured for media swap. */ - if (phy->id == M88E1112_E_PHY_ID) { - u16 data; - - ret_val = phy->ops.write_reg(hw, - E1000_M88E1112_PAGE_ADDR, - 2); - if (ret_val) - goto out; - - ret_val = phy->ops.read_reg(hw, - E1000_M88E1112_MAC_CTRL_1, - &data); - if (ret_val) - goto out; - - data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >> - E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT; - if (data == E1000_M88E1112_AUTO_COPPER_SGMII || - data == E1000_M88E1112_AUTO_COPPER_BASEX) - hw->mac.ops.check_for_link = - e1000_check_for_link_media_swap; - } - if (phy->id == M88E1512_E_PHY_ID) { - ret_val = e1000_initialize_M88E1512_phy(hw); - if (ret_val) - goto out; - } - if (phy->id == M88E1543_E_PHY_ID) { - ret_val = e1000_initialize_M88E1543_phy(hw); - if (ret_val) - goto out; - } break; case IGP03E1000_E_PHY_ID: case IGP04E1000_E_PHY_ID: - phy->type = e1000_phy_igp_3; - phy->ops.check_polarity = e1000_check_polarity_igp; - phy->ops.get_info = e1000_get_phy_info_igp; + phy->type = e1000_phy_igp_3; + phy->ops.check_polarity = e1000_check_polarity_igp; + phy->ops.get_info = e1000_get_phy_info_igp; phy->ops.get_cable_length = e1000_get_cable_length_igp_2; - phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp; phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575; phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic; + phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp; break; case I82580_I_PHY_ID: case I350_I_PHY_ID: - phy->type = e1000_phy_82580; - phy->ops.check_polarity = e1000_check_polarity_82577; - phy->ops.force_speed_duplex = - e1000_phy_force_speed_duplex_82577; + phy->type = e1000_phy_82580; + phy->ops.check_polarity = e1000_check_polarity_82577; + phy->ops.get_info = e1000_get_phy_info_82577; phy->ops.get_cable_length = e1000_get_cable_length_82577; - phy->ops.get_info = e1000_get_phy_info_82577; phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580; phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580; + phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_82577; break; case I210_I_PHY_ID: phy->type = e1000_phy_i210; @@ -292,98 +251,50 @@ STATIC s32 e1000_init_phy_params_82575(struct e1000_hw *hw) goto out; } -out: - return ret_val; -} - -/** - * e1000_init_nvm_params_82575 - Init NVM func ptrs. - * @hw: pointer to the HW structure - **/ -s32 e1000_init_nvm_params_82575(struct e1000_hw *hw) -{ - struct e1000_nvm_info *nvm = &hw->nvm; - u32 eecd = E1000_READ_REG(hw, E1000_EECD); - u16 size; - - DEBUGFUNC("e1000_init_nvm_params_82575"); - - size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> - E1000_EECD_SIZE_EX_SHIFT); - /* - * Added to a constant, "size" becomes the left-shift value - * for setting word_size. - */ - size += NVM_WORD_SIZE_BASE_SHIFT; - - /* Just in case size is out of range, cap it to the largest - * EEPROM size supported - */ - if (size > 15) - size = 15; - - nvm->word_size = 1 << size; - if (hw->mac.type < e1000_i210) { - nvm->opcode_bits = 8; - nvm->delay_usec = 1; + /* Check if this PHY is configured for media swap. */ + switch (phy->id) { + case M88E1112_E_PHY_ID: + { + u16 data; - switch (nvm->override) { - case e1000_nvm_override_spi_large: - nvm->page_size = 32; - nvm->address_bits = 16; - break; - case e1000_nvm_override_spi_small: - nvm->page_size = 8; - nvm->address_bits = 8; - break; - default: - nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; - nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? - 16 : 8; - break; - } - if (nvm->word_size == (1 << 15)) - nvm->page_size = 128; + ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 2); + if (ret_val) + goto out; + ret_val = phy->ops.read_reg(hw, E1000_M88E1112_MAC_CTRL_1, + &data); + if (ret_val) + goto out; - nvm->type = e1000_nvm_eeprom_spi; - } else { - nvm->type = e1000_nvm_flash_hw; + data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >> + E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT; + if (data == E1000_M88E1112_AUTO_COPPER_SGMII || + data == E1000_M88E1112_AUTO_COPPER_BASEX) + hw->mac.ops.check_for_link = + e1000_check_for_link_media_swap; + break; } - - /* Function Pointers */ - nvm->ops.acquire = e1000_acquire_nvm_82575; - nvm->ops.release = e1000_release_nvm_82575; - if (nvm->word_size < (1 << 15)) - nvm->ops.read = e1000_read_nvm_eerd; - else - nvm->ops.read = e1000_read_nvm_spi; - - nvm->ops.write = e1000_write_nvm_spi; - nvm->ops.validate = e1000_validate_nvm_checksum_generic; - nvm->ops.update = e1000_update_nvm_checksum_generic; - nvm->ops.valid_led_default = e1000_valid_led_default_82575; - - /* override generic family function pointers for specific descendants */ - switch (hw->mac.type) { - case e1000_82580: - nvm->ops.validate = e1000_validate_nvm_checksum_82580; - nvm->ops.update = e1000_update_nvm_checksum_82580; + case M88E1512_E_PHY_ID: + { + ret_val = e1000_initialize_M88E1512_phy(hw); break; - case e1000_i350: - case e1000_i354: - nvm->ops.validate = e1000_validate_nvm_checksum_i350; - nvm->ops.update = e1000_update_nvm_checksum_i350; + } + case M88E1543_E_PHY_ID: + { + ret_val = e1000_initialize_M88E1543_phy(hw); break; + } default: - break; + goto out; } - return E1000_SUCCESS; +out: + return ret_val; } + /** - * e1000_init_mac_params_82575 - Init MAC func ptrs. - * @hw: pointer to the HW structure + * e1000_init_mac_params_82575 - Initialize MAC function ptrs + * @hw: pointer to the HW structure **/ STATIC s32 e1000_init_mac_params_82575(struct e1000_hw *hw) { @@ -392,13 +303,16 @@ STATIC s32 e1000_init_mac_params_82575(struct e1000_hw *hw) DEBUGFUNC("e1000_init_mac_params_82575"); + /* Initialize function pointer */ + e1000_init_mac_ops_generic(hw); + /* Derives media type */ e1000_get_media_type_82575(hw); - /* Set mta register count */ + /* Set MTA register count */ mac->mta_reg_count = 128; - /* Set uta register count */ + /* Set UTA register count */ mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128; - /* Set rar entry count */ + /* Set RAR entry count */ mac->rar_entry_count = E1000_RAR_ENTRIES_82575; if (mac->type == e1000_82576) mac->rar_entry_count = E1000_RAR_ENTRIES_82576; @@ -432,16 +346,11 @@ STATIC s32 e1000_init_mac_params_82575(struct e1000_hw *hw) mac->ops.reset_hw = e1000_reset_hw_82580; else mac->ops.reset_hw = e1000_reset_hw_82575; - /* hw initialization */ + /* HW initialization */ if (mac->type == e1000_i210 || mac->type == e1000_i211) mac->ops.init_hw = e1000_init_hw_i210; else -#ifndef NO_I225_SUPPORT - if (mac->type == e1000_i225) - mac->ops.init_hw = e1000_init_hw_i225; - else -#endif /* NO_I225_SUPPORT */ - mac->ops.init_hw = e1000_init_hw_82575; + mac->ops.init_hw = e1000_init_hw_82575; /* link setup */ mac->ops.setup_link = e1000_setup_link_generic; /* physical interface link setup */ @@ -473,7 +382,7 @@ STATIC s32 e1000_init_mac_params_82575(struct e1000_hw *hw) } if (hw->mac.type >= e1000_82580) mac->ops.validate_mdi_setting = - e1000_validate_mdi_setting_crossover_generic; + e1000_validate_mdi_setting_crossover_generic; /* ID LED init */ mac->ops.id_led_init = e1000_id_led_init_generic; /* blink LED */ @@ -491,18 +400,13 @@ STATIC s32 e1000_init_mac_params_82575(struct e1000_hw *hw) mac->ops.get_link_up_info = e1000_get_link_up_info_82575; /* acquire SW_FW sync */ mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_82575; + /* release SW_FW sync */ mac->ops.release_swfw_sync = e1000_release_swfw_sync_82575; if (mac->type == e1000_i210 || mac->type == e1000_i211) { mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_i210; mac->ops.release_swfw_sync = e1000_release_swfw_sync_i210; } -#ifndef NO_I225_SUPPORT - if (mac->type >= e1000_i225) { - mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_i225; - mac->ops.release_swfw_sync = e1000_release_swfw_sync_i225; - } -#endif /* NO_I225_SUPPORT */ /* set lan id for port to determine which phy lock to use */ hw->mac.ops.set_lan_id(hw); @@ -510,63 +414,102 @@ STATIC s32 e1000_init_mac_params_82575(struct e1000_hw *hw) } /** - * e1000_init_function_pointers_82575 - Init func ptrs. - * @hw: pointer to the HW structure - * - * Called to initialize all function pointers and parameters. + * e1000_init_nvm_params_82575 - Initialize NVM function ptrs + * @hw: pointer to the HW structure **/ -void e1000_init_function_pointers_82575(struct e1000_hw *hw) +s32 e1000_init_nvm_params_82575(struct e1000_hw *hw) { - DEBUGFUNC("e1000_init_function_pointers_82575"); + struct e1000_nvm_info *nvm = &hw->nvm; + u32 eecd = E1000_READ_REG(hw, E1000_EECD); + u16 size; - hw->mac.ops.init_params = e1000_init_mac_params_82575; - hw->nvm.ops.init_params = e1000_init_nvm_params_82575; - hw->phy.ops.init_params = e1000_init_phy_params_82575; - hw->mbx.ops.init_params = e1000_init_mbx_params_pf; -} + DEBUGFUNC("e1000_init_nvm_params_82575"); -/** - * e1000_acquire_phy_82575 - Acquire rights to access PHY - * @hw: pointer to the HW structure - * - * Acquire access rights to the correct PHY. - **/ -STATIC s32 e1000_acquire_phy_82575(struct e1000_hw *hw) -{ - u16 mask = E1000_SWFW_PHY0_SM; + size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >> + E1000_EECD_SIZE_EX_SHIFT); + /* Added to a constant, "size" becomes the left-shift value + * for setting word_size. + */ + size += NVM_WORD_SIZE_BASE_SHIFT; + + /* Just in case size is out of range, cap it to the largest + * EEPROM size supported + */ + if (size > 15) + size = 15; - DEBUGFUNC("e1000_acquire_phy_82575"); + nvm->word_size = 1 << size; + if (hw->mac.type < e1000_i210) { + nvm->opcode_bits = 8; + nvm->delay_usec = 1; - if (hw->bus.func == E1000_FUNC_1) - mask = E1000_SWFW_PHY1_SM; - else if (hw->bus.func == E1000_FUNC_2) - mask = E1000_SWFW_PHY2_SM; - else if (hw->bus.func == E1000_FUNC_3) - mask = E1000_SWFW_PHY3_SM; + switch (nvm->override) { + case e1000_nvm_override_spi_large: + nvm->page_size = 32; + nvm->address_bits = 16; + break; + case e1000_nvm_override_spi_small: + nvm->page_size = 8; + nvm->address_bits = 8; + break; + default: + nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8; + nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? + 16 : 8; + break; + } + if (nvm->word_size == (1 << 15)) + nvm->page_size = 128; + + nvm->type = e1000_nvm_eeprom_spi; + } else { + nvm->type = e1000_nvm_flash_hw; + } + + /* Function Pointers */ + nvm->ops.acquire = e1000_acquire_nvm_82575; + nvm->ops.release = e1000_release_nvm_82575; + if (nvm->word_size < (1 << 15)) + nvm->ops.read = e1000_read_nvm_eerd; + else + nvm->ops.read = e1000_read_nvm_spi; + + nvm->ops.write = e1000_write_nvm_spi; + nvm->ops.validate = e1000_validate_nvm_checksum_generic; + nvm->ops.update = e1000_update_nvm_checksum_generic; + nvm->ops.valid_led_default = e1000_valid_led_default_82575; + + /* override generic family function pointers for specific descendants */ + switch (hw->mac.type) { + case e1000_82580: + nvm->ops.validate = e1000_validate_nvm_checksum_82580; + nvm->ops.update = e1000_update_nvm_checksum_82580; + break; + case e1000_i350: + nvm->ops.validate = e1000_validate_nvm_checksum_i350; + nvm->ops.update = e1000_update_nvm_checksum_i350; + break; + default: + break; + } - return hw->mac.ops.acquire_swfw_sync(hw, mask); + return E1000_SUCCESS; } /** - * e1000_release_phy_82575 - Release rights to access PHY + * e1000_init_function_pointers_82575 - Init func ptrs. * @hw: pointer to the HW structure * - * A wrapper to release access rights to the correct PHY. + * Called to initialize all function pointers and parameters. **/ -STATIC void e1000_release_phy_82575(struct e1000_hw *hw) +void e1000_init_function_pointers_82575(struct e1000_hw *hw) { - u16 mask = E1000_SWFW_PHY0_SM; - - DEBUGFUNC("e1000_release_phy_82575"); - - if (hw->bus.func == E1000_FUNC_1) - mask = E1000_SWFW_PHY1_SM; - else if (hw->bus.func == E1000_FUNC_2) - mask = E1000_SWFW_PHY2_SM; - else if (hw->bus.func == E1000_FUNC_3) - mask = E1000_SWFW_PHY3_SM; + DEBUGFUNC("e1000_init_function_pointers_82575"); - hw->mac.ops.release_swfw_sync(hw, mask); + hw->mac.ops.init_params = e1000_init_mac_params_82575; + hw->nvm.ops.init_params = e1000_init_nvm_params_82575; + hw->phy.ops.init_params = e1000_init_phy_params_82575; + hw->mbx.ops.init_params = e1000_init_mbx_params_pf; } /** @@ -1467,16 +1410,15 @@ STATIC s32 e1000_reset_hw_82575(struct e1000_hw *hw) } /** - * e1000_init_hw_82575 - Initialize hardware - * @hw: pointer to the HW structure + * e1000_init_hw_82575 - Initialize hardware + * @hw: pointer to the HW structure * - * This inits the hardware readying it for operation. + * This inits the hardware readying it for operation. **/ -s32 e1000_init_hw_82575(struct e1000_hw *hw) +STATIC s32 e1000_init_hw_82575(struct e1000_hw *hw) { struct e1000_mac_info *mac = &hw->mac; s32 ret_val; - u16 i, rar_count = mac->rar_entry_count; DEBUGFUNC("e1000_init_hw_82575"); @@ -1491,27 +1433,12 @@ s32 e1000_init_hw_82575(struct e1000_hw *hw) DEBUGOUT("Initializing the IEEE VLAN\n"); mac->ops.clear_vfta(hw); - /* Setup the receive address */ - e1000_init_rx_addrs_generic(hw, rar_count); - - /* Zero out the Multicast HASH table */ - DEBUGOUT("Zeroing the MTA\n"); - for (i = 0; i < mac->mta_reg_count; i++) - E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); - - /* Zero out the Unicast HASH table */ - DEBUGOUT("Zeroing the UTA\n"); - for (i = 0; i < mac->uta_reg_count; i++) - E1000_WRITE_REG_ARRAY(hw, E1000_UTA, i, 0); - - /* Setup link and flow control */ - ret_val = mac->ops.setup_link(hw); + ret_val = e1000_init_hw_base(hw); /* Set the default MTU size */ hw->dev_spec._82575.mtu = 1500; - /* - * Clear all of the statistics registers (clear on read). It is + /* Clear all of the statistics registers (clear on read). It is * important that we do this after we have tried to establish link * because the symbol error count will increment wildly if there * is no link. @@ -1520,7 +1447,6 @@ s32 e1000_init_hw_82575(struct e1000_hw *hw) return ret_val; } - /** * e1000_setup_copper_link_82575 - Configure copper link settings * @hw: pointer to the HW structure @@ -1531,9 +1457,9 @@ s32 e1000_init_hw_82575(struct e1000_hw *hw) **/ STATIC s32 e1000_setup_copper_link_82575(struct e1000_hw *hw) { - u32 ctrl; - s32 ret_val; u32 phpm_reg; + s32 ret_val; + u32 ctrl; DEBUGFUNC("e1000_setup_copper_link_82575"); @@ -1572,14 +1498,21 @@ STATIC s32 e1000_setup_copper_link_82575(struct e1000_hw *hw) } switch (hw->phy.type) { case e1000_phy_i210: + /* fall through */ case e1000_phy_m88: switch (hw->phy.id) { case I347AT4_E_PHY_ID: + /* fall through */ case M88E1112_E_PHY_ID: + /* fall through */ case M88E1340M_E_PHY_ID: + /* fall through */ case M88E1543_E_PHY_ID: + /* fall through */ case M88E1512_E_PHY_ID: + /* fall through */ case I210_I_PHY_ID: + /* fall through */ ret_val = e1000_copper_link_setup_m88_gen2(hw); break; default: @@ -1593,8 +1526,6 @@ STATIC s32 e1000_setup_copper_link_82575(struct e1000_hw *hw) case e1000_phy_82580: ret_val = e1000_copper_link_setup_82577(hw); break; - case e1000_phy_none: - break; default: ret_val = -E1000_ERR_PHY; break; @@ -1956,7 +1887,7 @@ STATIC bool e1000_sgmii_active_82575(struct e1000_hw *hw) * Inits recommended HW defaults after a reset when there is no EEPROM * detected. This is only for the 82575. **/ -STATIC s32 e1000_reset_init_script_82575(struct e1000_hw *hw) +s32 e1000_reset_init_script_82575(struct e1000_hw *hw) { DEBUGFUNC("e1000_reset_init_script_82575"); @@ -2034,27 +1965,6 @@ STATIC void e1000_config_collision_dist_82575(struct e1000_hw *hw) E1000_WRITE_FLUSH(hw); } -/** - * e1000_power_down_phy_copper_82575 - Remove link during PHY power down - * @hw: pointer to the HW structure - * - * In the case of a PHY power down to save power, or to turn off link during a - * driver unload, or wake on lan is not enabled, remove the link. - **/ -STATIC void e1000_power_down_phy_copper_82575(struct e1000_hw *hw) -{ - struct e1000_phy_info *phy = &hw->phy; - - if (!(phy->ops.check_reset_block)) - return; - - /* If the management interface is not enabled, then power down */ - if (!(e1000_enable_mng_pass_thru(hw) || phy->ops.check_reset_block(hw))) - e1000_power_down_phy_copper(hw); - - return; -} - /** * e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters * @hw: pointer to the HW structure @@ -2120,85 +2030,6 @@ STATIC void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw) E1000_READ_REG(hw, E1000_SCVPC); } -/** - * e1000_rx_fifo_flush_82575 - Clean rx fifo after Rx enable - * @hw: pointer to the HW structure - * - * After Rx enable, if manageability is enabled then there is likely some - * bad data at the start of the fifo and possibly in the DMA fifo. This - * function clears the fifos and flushes any packets that came in as rx was - * being enabled. - **/ -void e1000_rx_fifo_flush_82575(struct e1000_hw *hw) -{ - u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled; - int i, ms_wait; - - DEBUGFUNC("e1000_rx_fifo_flush_82575"); - - /* disable IPv6 options as per hardware errata */ - rfctl = E1000_READ_REG(hw, E1000_RFCTL); - rfctl |= E1000_RFCTL_IPV6_EX_DIS; - E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); - - if (hw->mac.type != e1000_82575 || - !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN)) - return; - - /* Disable all Rx queues */ - for (i = 0; i < 4; i++) { - rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i)); - E1000_WRITE_REG(hw, E1000_RXDCTL(i), - rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE); - } - /* Poll all queues to verify they have shut down */ - for (ms_wait = 0; ms_wait < 10; ms_wait++) { - msec_delay(1); - rx_enabled = 0; - for (i = 0; i < 4; i++) - rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i)); - if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE)) - break; - } - - if (ms_wait == 10) - DEBUGOUT("Queue disable timed out after 10ms\n"); - - /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all - * incoming packets are rejected. Set enable and wait 2ms so that - * any packet that was coming in as RCTL.EN was set is flushed - */ - E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF); - - rlpml = E1000_READ_REG(hw, E1000_RLPML); - E1000_WRITE_REG(hw, E1000_RLPML, 0); - - rctl = E1000_READ_REG(hw, E1000_RCTL); - temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP); - temp_rctl |= E1000_RCTL_LPE; - - E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl); - E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN); - E1000_WRITE_FLUSH(hw); - msec_delay(2); - - /* Enable Rx queues that were previously enabled and restore our - * previous state - */ - for (i = 0; i < 4; i++) - E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]); - E1000_WRITE_REG(hw, E1000_RCTL, rctl); - E1000_WRITE_FLUSH(hw); - - E1000_WRITE_REG(hw, E1000_RLPML, rlpml); - E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); - - /* Flush receive errors generated by workaround */ - E1000_READ_REG(hw, E1000_ROC); - E1000_READ_REG(hw, E1000_RNBC); - E1000_READ_REG(hw, E1000_MPC); -} - /** * e1000_set_pcie_completion_timeout - set pci-e completion timeout * @hw: pointer to the HW structure diff --git a/drivers/net/e1000/base/e1000_82575.h b/drivers/net/e1000/base/e1000_82575.h index 52dd7a9a1..25fc20ba8 100644 --- a/drivers/net/e1000/base/e1000_82575.h +++ b/drivers/net/e1000/base/e1000_82575.h @@ -93,11 +93,8 @@ struct e1000_adv_context_desc { #endif /* SRRCTL bit definitions */ -#define E1000_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */ #define E1000_SRRCTL_BSIZEHDRSIZE_MASK 0x00000F00 -#define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */ #define E1000_SRRCTL_DESCTYPE_LEGACY 0x00000000 -#define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000 #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000 #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000 #define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION 0x06000000 @@ -160,38 +157,6 @@ struct e1000_adv_context_desc { #define E1000_IMIREXT_CTRL_FIN 0x00040000 /* Check FIN bit in header */ #define E1000_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of ctrl bits */ -/* Receive Descriptor - Advanced */ -union e1000_adv_rx_desc { - struct { - __le64 pkt_addr; /* Packet buffer address */ - __le64 hdr_addr; /* Header buffer address */ - } read; - struct { - struct { - union { - __le32 data; - struct { - __le16 pkt_info; /*RSS type, Pkt type*/ - /* Split Header, header buffer len */ - __le16 hdr_info; - } hs_rss; - } lo_dword; - union { - __le32 rss; /* RSS Hash */ - struct { - __le16 ip_id; /* IP id */ - __le16 csum; /* Packet Checksum */ - } csum_ip; - } hi_dword; - } lower; - struct { - __le32 status_error; /* ext status/error */ - __le16 length; /* Packet length */ - __le16 vlan; /* VLAN tag */ - } upper; - } wb; /* writeback */ -}; - #define E1000_RXDADV_RSSTYPE_MASK 0x0000000F #define E1000_RXDADV_RSSTYPE_SHIFT 12 #define E1000_RXDADV_HDRBUFLEN_MASK 0x7FE0 @@ -248,77 +213,10 @@ union e1000_adv_rx_desc { #define E1000_RXDADV_IPSEC_ERROR_INVALID_LENGTH 0x10000000 #define E1000_RXDADV_IPSEC_ERROR_AUTHENTICATION_FAILED 0x18000000 -/* Transmit Descriptor - Advanced */ -union e1000_adv_tx_desc { - struct { - __le64 buffer_addr; /* Address of descriptor's data buf */ - __le32 cmd_type_len; - __le32 olinfo_status; - } read; - struct { - __le64 rsvd; /* Reserved */ - __le32 nxtseq_seed; - __le32 status; - } wb; -}; - -/* Adv Transmit Descriptor Config Masks */ -#define E1000_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */ -#define E1000_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */ -#define E1000_ADVTXD_DCMD_EOP 0x01000000 /* End of Packet */ -#define E1000_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ -#define E1000_ADVTXD_DCMD_RS 0x08000000 /* Report Status */ -#define E1000_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */ -#define E1000_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */ -#define E1000_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */ -#define E1000_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */ -#define E1000_ADVTXD_MAC_LINKSEC 0x00040000 /* Apply LinkSec on pkt */ -#define E1000_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE1588 Timestamp pkt */ -#define E1000_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED prsnt in WB */ -#define E1000_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */ -#define E1000_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */ -#define E1000_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */ -#define E1000_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */ -/* 1st & Last TSO-full iSCSI PDU*/ -#define E1000_ADVTXD_POPTS_ISCO_FULL 0x00001800 -#define E1000_ADVTXD_POPTS_IPSEC 0x00000400 /* IPSec offload request */ -#define E1000_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */ - -/* Context descriptors */ -struct e1000_adv_tx_context_desc { - __le32 vlan_macip_lens; - __le32 seqnum_seed; - __le32 type_tucmd_mlhl; - __le32 mss_l4len_idx; -}; - -#define E1000_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */ -#define E1000_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */ -#define E1000_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */ -#define E1000_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */ -#define E1000_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */ -#define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */ -#define E1000_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */ -#define E1000_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */ -/* IPSec Encrypt Enable for ESP */ -#define E1000_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000 -/* Req requires Markers and CRC */ -#define E1000_ADVTXD_TUCMD_MKRREQ 0x00002000 -#define E1000_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */ -#define E1000_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */ -/* Adv ctxt IPSec SA IDX mask */ -#define E1000_ADVTXD_IPSEC_SA_INDEX_MASK 0x000000FF -/* Adv ctxt IPSec ESP len mask */ -#define E1000_ADVTXD_IPSEC_ESP_LEN_MASK 0x000000FF - -/* Additional Transmit Descriptor Control definitions */ -#define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Tx Queue */ #define E1000_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. wbk flushing */ /* Tx Queue Arbitration Priority 0=low, 1=high */ #define E1000_TXDCTL_PRIORITY 0x08000000 -/* Additional Receive Descriptor Control definitions */ -#define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Rx Queue */ #define E1000_RXDCTL_SWFLSH 0x04000000 /* Rx Desc. wbk flushing */ /* Direct Cache Access (DCA) definitions */ @@ -444,13 +342,14 @@ struct e1000_adv_tx_context_desc { #define ALL_QUEUES 0xFFFF +s32 e1000_reset_init_script_82575(struct e1000_hw *hw); +s32 e1000_init_nvm_params_82575(struct e1000_hw *hw); + /* Rx packet buffer size defines */ #define E1000_RXPBS_SIZE_MASK_82576 0x0000007F void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable); void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf); void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable); -s32 e1000_init_nvm_params_82575(struct e1000_hw *hw); -s32 e1000_init_hw_82575(struct e1000_hw *hw); enum e1000_promisc_type { e1000_promisc_disabled = 0, /* all promisc modes disabled */ diff --git a/drivers/net/e1000/base/e1000_base.c b/drivers/net/e1000/base/e1000_base.c new file mode 100644 index 000000000..342735693 --- /dev/null +++ b/drivers/net/e1000/base/e1000_base.c @@ -0,0 +1,191 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2001-2020 Intel Corporation + */ + +#include "e1000_hw.h" +#include "e1000_82575.h" +#include "e1000_i225.h" +#include "e1000_mac.h" +#include "e1000_base.h" +#include "e1000_manage.h" + +/** + * e1000_acquire_phy_base - Acquire rights to access PHY + * @hw: pointer to the HW structure + * + * Acquire access rights to the correct PHY. + **/ +s32 e1000_acquire_phy_base(struct e1000_hw *hw) +{ + u16 mask = E1000_SWFW_PHY0_SM; + + DEBUGFUNC("e1000_acquire_phy_base"); + + if (hw->bus.func == E1000_FUNC_1) + mask = E1000_SWFW_PHY1_SM; + else if (hw->bus.func == E1000_FUNC_2) + mask = E1000_SWFW_PHY2_SM; + else if (hw->bus.func == E1000_FUNC_3) + mask = E1000_SWFW_PHY3_SM; + + return hw->mac.ops.acquire_swfw_sync(hw, mask); +} + +/** + * e1000_release_phy_base - Release rights to access PHY + * @hw: pointer to the HW structure + * + * A wrapper to release access rights to the correct PHY. + **/ +void e1000_release_phy_base(struct e1000_hw *hw) +{ + u16 mask = E1000_SWFW_PHY0_SM; + + DEBUGFUNC("e1000_release_phy_base"); + + if (hw->bus.func == E1000_FUNC_1) + mask = E1000_SWFW_PHY1_SM; + else if (hw->bus.func == E1000_FUNC_2) + mask = E1000_SWFW_PHY2_SM; + else if (hw->bus.func == E1000_FUNC_3) + mask = E1000_SWFW_PHY3_SM; + + hw->mac.ops.release_swfw_sync(hw, mask); +} + +/** + * e1000_init_hw_base - Initialize hardware + * @hw: pointer to the HW structure + * + * This inits the hardware readying it for operation. + **/ +s32 e1000_init_hw_base(struct e1000_hw *hw) +{ + struct e1000_mac_info *mac = &hw->mac; + s32 ret_val; + u16 i, rar_count = mac->rar_entry_count; + + DEBUGFUNC("e1000_init_hw_base"); + + /* Setup the receive address */ + e1000_init_rx_addrs_generic(hw, rar_count); + + /* Zero out the Multicast HASH table */ + DEBUGOUT("Zeroing the MTA\n"); + for (i = 0; i < mac->mta_reg_count; i++) + E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); + + /* Zero out the Unicast HASH table */ + DEBUGOUT("Zeroing the UTA\n"); + for (i = 0; i < mac->uta_reg_count; i++) + E1000_WRITE_REG_ARRAY(hw, E1000_UTA, i, 0); + + /* Setup link and flow control */ + ret_val = mac->ops.setup_link(hw); + /* + * Clear all of the statistics registers (clear on read). It is + * important that we do this after we have tried to establish link + * because the symbol error count will increment wildly if there + * is no link. + */ + e1000_clear_hw_cntrs_base_generic(hw); + + return ret_val; +} + +/** + * e1000_power_down_phy_copper_base - Remove link during PHY power down + * @hw: pointer to the HW structure + * + * In the case of a PHY power down to save power, or to turn off link during a + * driver unload, or wake on lan is not enabled, remove the link. + **/ +void e1000_power_down_phy_copper_base(struct e1000_hw *hw) +{ + struct e1000_phy_info *phy = &hw->phy; + + if (!(phy->ops.check_reset_block)) + return; + + /* If the management interface is not enabled, then power down */ + if (phy->ops.check_reset_block(hw)) + e1000_power_down_phy_copper(hw); +} + +/** + * e1000_rx_fifo_flush_base - Clean Rx FIFO after Rx enable + * @hw: pointer to the HW structure + * + * After Rx enable, if manageability is enabled then there is likely some + * bad data at the start of the FIFO and possibly in the DMA FIFO. This + * function clears the FIFOs and flushes any packets that came in as Rx was + * being enabled. + **/ +void e1000_rx_fifo_flush_base(struct e1000_hw *hw) +{ + u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled; + int i, ms_wait; + + DEBUGFUNC("e1000_rx_fifo_flush_base"); + + /* disable IPv6 options as per hardware errata */ + rfctl = E1000_READ_REG(hw, E1000_RFCTL); + rfctl |= E1000_RFCTL_IPV6_EX_DIS; + E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); + + if (!(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN)) + return; + + /* Disable all Rx queues */ + for (i = 0; i < 4; i++) { + rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i)); + E1000_WRITE_REG(hw, E1000_RXDCTL(i), + rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE); + } + /* Poll all queues to verify they have shut down */ + for (ms_wait = 0; ms_wait < 10; ms_wait++) { + msec_delay(1); + rx_enabled = 0; + for (i = 0; i < 4; i++) + rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i)); + if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE)) + break; + } + + if (ms_wait == 10) + DEBUGOUT("Queue disable timed out after 10ms\n"); + + /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all + * incoming packets are rejected. Set enable and wait 2ms so that + * any packet that was coming in as RCTL.EN was set is flushed + */ + E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF); + + rlpml = E1000_READ_REG(hw, E1000_RLPML); + E1000_WRITE_REG(hw, E1000_RLPML, 0); + + rctl = E1000_READ_REG(hw, E1000_RCTL); + temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP); + temp_rctl |= E1000_RCTL_LPE; + + E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl); + E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN); + E1000_WRITE_FLUSH(hw); + msec_delay(2); + + /* Enable Rx queues that were previously enabled and restore our + * previous state + */ + for (i = 0; i < 4; i++) + E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]); + E1000_WRITE_REG(hw, E1000_RCTL, rctl); + E1000_WRITE_FLUSH(hw); + + E1000_WRITE_REG(hw, E1000_RLPML, rlpml); + E1000_WRITE_REG(hw, E1000_RFCTL, rfctl); + + /* Flush receive errors generated by workaround */ + E1000_READ_REG(hw, E1000_ROC); + E1000_READ_REG(hw, E1000_RNBC); + E1000_READ_REG(hw, E1000_MPC); +} diff --git a/drivers/net/e1000/base/e1000_base.h b/drivers/net/e1000/base/e1000_base.h new file mode 100644 index 000000000..0d6172b6d --- /dev/null +++ b/drivers/net/e1000/base/e1000_base.h @@ -0,0 +1,127 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright(c) 2001-2020 Intel Corporation + */ + +#ifndef _E1000_BASE_H_ +#define _E1000_BASE_H_ + +/* forward declaration */ +s32 e1000_init_hw_base(struct e1000_hw *hw); +void e1000_power_down_phy_copper_base(struct e1000_hw *hw); +extern void e1000_rx_fifo_flush_base(struct e1000_hw *hw); +s32 e1000_acquire_phy_base(struct e1000_hw *hw); +void e1000_release_phy_base(struct e1000_hw *hw); + +/* Transmit Descriptor - Advanced */ +union e1000_adv_tx_desc { + struct { + __le64 buffer_addr; /* Address of descriptor's data buf */ + __le32 cmd_type_len; + __le32 olinfo_status; + } read; + struct { + __le64 rsvd; /* Reserved */ + __le32 nxtseq_seed; + __le32 status; + } wb; +}; + +/* Context descriptors */ +struct e1000_adv_tx_context_desc { + __le32 vlan_macip_lens; + union { + __le32 launch_time; + __le32 seqnum_seed; + } u; + __le32 type_tucmd_mlhl; + __le32 mss_l4len_idx; +}; + +/* Adv Transmit Descriptor Config Masks */ +#define E1000_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */ +#define E1000_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */ +#define E1000_ADVTXD_DCMD_EOP 0x01000000 /* End of Packet */ +#define E1000_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ +#define E1000_ADVTXD_DCMD_RS 0x08000000 /* Report Status */ +#define E1000_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */ +#define E1000_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */ +#define E1000_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */ +#define E1000_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */ +#define E1000_ADVTXD_MAC_LINKSEC 0x00040000 /* Apply LinkSec on pkt */ +#define E1000_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE1588 Timestamp pkt */ +#define E1000_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED prsnt in WB */ +#define E1000_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */ +#define E1000_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */ +#define E1000_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */ +#define E1000_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */ +/* 1st & Last TSO-full iSCSI PDU*/ +#define E1000_ADVTXD_POPTS_ISCO_FULL 0x00001800 +#define E1000_ADVTXD_POPTS_IPSEC 0x00000400 /* IPSec offload request */ +#define E1000_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */ + +/* Advanced Transmit Context Descriptor Config */ +#define E1000_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */ +#define E1000_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */ +#define E1000_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */ +#define E1000_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */ +#define E1000_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */ +#define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */ +#define E1000_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */ +#define E1000_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */ +/* IPSec Encrypt Enable for ESP */ +#define E1000_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000 +/* Req requires Markers and CRC */ +#define E1000_ADVTXD_TUCMD_MKRREQ 0x00002000 +#define E1000_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */ +#define E1000_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */ +/* Adv ctxt IPSec SA IDX mask */ +#define E1000_ADVTXD_IPSEC_SA_INDEX_MASK 0x000000FF +/* Adv ctxt IPSec ESP len mask */ +#define E1000_ADVTXD_IPSEC_ESP_LEN_MASK 0x000000FF + +#define E1000_RAR_ENTRIES_BASE 16 + +/* Receive Descriptor - Advanced */ +union e1000_adv_rx_desc { + struct { + __le64 pkt_addr; /* Packet buffer address */ + __le64 hdr_addr; /* Header buffer address */ + } read; + struct { + struct { + union { + __le32 data; + struct { + __le16 pkt_info; /*RSS type, Pkt type*/ + /* Split Header, header buffer len */ + __le16 hdr_info; + } hs_rss; + } lo_dword; + union { + __le32 rss; /* RSS Hash */ + struct { + __le16 ip_id; /* IP id */ + __le16 csum; /* Packet Checksum */ + } csum_ip; + } hi_dword; + } lower; + struct { + __le32 status_error; /* ext status/error */ + __le16 length; /* Packet length */ + __le16 vlan; /* VLAN tag */ + } upper; + } wb; /* writeback */ +}; + +/* Additional Transmit Descriptor Control definitions */ +#define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Tx Queue */ + +/* Additional Receive Descriptor Control definitions */ +#define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Rx Queue */ + +/* SRRCTL bit definitions */ +#define E1000_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */ +#define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */ +#define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000 + +#endif /* _E1000_BASE_H_ */ diff --git a/drivers/net/e1000/base/e1000_hw.h b/drivers/net/e1000/base/e1000_hw.h index 76b4dd5c1..848d21645 100644 --- a/drivers/net/e1000/base/e1000_hw.h +++ b/drivers/net/e1000/base/e1000_hw.h @@ -1032,6 +1032,7 @@ struct e1000_hw { #include "e1000_82575.h" #include "e1000_i210.h" #include "e1000_i225.h" +#include "e1000_base.h" /* These functions must be implemented by drivers */ void e1000_pci_clear_mwi(struct e1000_hw *hw); diff --git a/drivers/net/e1000/base/e1000_i210.c b/drivers/net/e1000/base/e1000_i210.c index c00161456..d4e4b527a 100644 --- a/drivers/net/e1000/base/e1000_i210.c +++ b/drivers/net/e1000/base/e1000_i210.c @@ -936,6 +936,6 @@ s32 e1000_init_hw_i210(struct e1000_hw *hw) return ret_val; } hw->phy.ops.get_cfg_done = e1000_get_cfg_done_i210; - ret_val = e1000_init_hw_82575(hw); + ret_val = e1000_init_hw_base(hw); return ret_val; } diff --git a/drivers/net/e1000/base/e1000_i225.c b/drivers/net/e1000/base/e1000_i225.c index 87ccf6d9c..505eff8f9 100644 --- a/drivers/net/e1000/base/e1000_i225.c +++ b/drivers/net/e1000/base/e1000_i225.c @@ -1144,7 +1144,7 @@ s32 e1000_init_hw_i225(struct e1000_hw *hw) return ret_val; } hw->phy.ops.get_cfg_done = e1000_get_cfg_done_i225; - ret_val = e1000_init_hw_82575(hw); + ret_val = e1000_init_hw_base(hw); return ret_val; } diff --git a/drivers/net/e1000/base/meson.build b/drivers/net/e1000/base/meson.build index d13c32033..f1ff51a04 100644 --- a/drivers/net/e1000/base/meson.build +++ b/drivers/net/e1000/base/meson.build @@ -10,6 +10,7 @@ sources = [ 'e1000_82571.c', 'e1000_82575.c', 'e1000_api.c', + 'e1000_base.c', 'e1000_i210.c', 'e1000_i225.c', 'e1000_ich8lan.c', diff --git a/drivers/net/e1000/igb_rxtx.c b/drivers/net/e1000/igb_rxtx.c index 684fa4ad8..688320284 100644 --- a/drivers/net/e1000/igb_rxtx.c +++ b/drivers/net/e1000/igb_rxtx.c @@ -320,7 +320,7 @@ igbe_set_xmit_ctx(struct igb_tx_queue* txq, vlan_macip_lens = (uint32_t)tx_offload.data; ctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens); ctx_txd->mss_l4len_idx = rte_cpu_to_le_32(mss_l4len_idx); - ctx_txd->seqnum_seed = 0; + ctx_txd->u.seqnum_seed = 0; } /* -- 2.17.1