From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id E3C3AA0350; Wed, 24 Jun 2020 10:07:03 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 720251D73B; Wed, 24 Jun 2020 10:02:23 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id 8E2511D976 for ; Wed, 24 Jun 2020 10:02:18 +0200 (CEST) IronPort-SDR: ukvS8jL/0q1FMcojWcvX2tZ38vOP3Jj7E1NpKK6ymqYfIbSEh9/9Grt0eycIed45estDrlK1he lLnwELez9mnA== X-IronPort-AV: E=McAfee;i="6000,8403,9661"; a="143472950" X-IronPort-AV: E=Sophos;i="5.75,274,1589266800"; d="scan'208";a="143472950" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jun 2020 01:02:18 -0700 IronPort-SDR: gI1m/turzGSgY4ngIpmTN0I5r6R9g/oQcYx7jvzrvaTKNY+28XDNeVRr7ph1Rv+cFnL5kGWDzo KXPh1ZcFiVxQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,274,1589266800"; d="scan'208";a="385102936" Received: from intel.sh.intel.com ([10.239.255.48]) by fmsmga001.fm.intel.com with ESMTP; 24 Jun 2020 01:02:16 -0700 From: Guinan Sun To: dev@dpdk.org Cc: Jeff Guo , Wenzhuo Lu , Guinan Sun , Efrati Nir Date: Wed, 24 Jun 2020 07:53:20 +0000 Message-Id: <20200624075337.6768-26-guinanx.sun@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200624075337.6768-1-guinanx.sun@intel.com> References: <20200622064634.70941-1-guinanx.sun@intel.com> <20200624075337.6768-1-guinanx.sun@intel.com> Subject: [dpdk-dev] [PATCH v2 25/42] net/e1000/base: increased timeout for ME ULP exit X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Due timing issues in WHL and since recovery by host is not always supported, increased timeout for ME to finish ULP exit flow for Nahum before timer expiration. Signed-off-by: Efrati Nir Signed-off-by: Guinan Sun --- drivers/net/e1000/base/e1000_ich8lan.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/net/e1000/base/e1000_ich8lan.c b/drivers/net/e1000/base/e1000_ich8lan.c index 1dc29553e..b79e3bad8 100644 --- a/drivers/net/e1000/base/e1000_ich8lan.c +++ b/drivers/net/e1000/base/e1000_ich8lan.c @@ -1268,6 +1268,7 @@ s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx) s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force) { s32 ret_val = E1000_SUCCESS; + u8 ulp_exit_timeout = 30; u32 mac_reg; u16 phy_reg; int i = 0; @@ -1289,10 +1290,12 @@ s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force) E1000_WRITE_REG(hw, E1000_H2ME, mac_reg); } - /* Poll up to 300msec for ME to clear ULP_CFG_DONE. */ + if (hw->mac.type == e1000_pch_cnp) + ulp_exit_timeout = 100; + while (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_ULP_CFG_DONE) { - if (i++ == 30) { + if (i++ == ulp_exit_timeout) { ret_val = -E1000_ERR_PHY; goto out; } -- 2.17.1