From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5085FA0350; Wed, 24 Jun 2020 10:10:49 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 593111D9F4; Wed, 24 Jun 2020 10:02:58 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id 050F91D9E6 for ; Wed, 24 Jun 2020 10:02:52 +0200 (CEST) IronPort-SDR: L1LQ+XMDbuCtFTUmdo/FWlNvjG/nUUafKD9ULUfUWN2Gt8CE2AdxwovFAfkClnDsSOzoAJraaL 8h3pxBAIL8MA== X-IronPort-AV: E=McAfee;i="6000,8403,9661"; a="143473026" X-IronPort-AV: E=Sophos;i="5.75,274,1589266800"; d="scan'208";a="143473026" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jun 2020 01:02:52 -0700 IronPort-SDR: /75fWuihgZvsYQYnqyP1j/1HxUBfYK2tJ21umE3yIQMKpU0tnyrRBRZ91gDAnDiqjy7Z5ucugB GbjhOW9tT8aQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,274,1589266800"; d="scan'208";a="385103077" Received: from intel.sh.intel.com ([10.239.255.48]) by fmsmga001.fm.intel.com with ESMTP; 24 Jun 2020 01:02:50 -0700 From: Guinan Sun To: dev@dpdk.org Cc: Jeff Guo , Wenzhuo Lu , Guinan Sun Date: Wed, 24 Jun 2020 07:53:35 +0000 Message-Id: <20200624075337.6768-41-guinanx.sun@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200624075337.6768-1-guinanx.sun@intel.com> References: <20200622064634.70941-1-guinanx.sun@intel.com> <20200624075337.6768-1-guinanx.sun@intel.com> Subject: [dpdk-dev] [PATCH v2 40/42] net/e1000/base: remove conditional compilation wrapper X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Remove conditional compilation statements. Signed-off-by: Guinan Sun --- drivers/net/e1000/base/e1000_82575.c | 2 +- drivers/net/e1000/base/e1000_82575.h | 2 -- drivers/net/e1000/base/e1000_defines.h | 9 +-------- drivers/net/e1000/base/e1000_hw.h | 4 ---- drivers/net/e1000/base/e1000_ich8lan.c | 19 ------------------- drivers/net/e1000/base/e1000_ich8lan.h | 18 ++---------------- drivers/net/e1000/base/e1000_mac.h | 2 -- drivers/net/e1000/base/e1000_manage.c | 4 ++-- drivers/net/e1000/base/e1000_regs.h | 5 +++-- 9 files changed, 9 insertions(+), 56 deletions(-) diff --git a/drivers/net/e1000/base/e1000_82575.c b/drivers/net/e1000/base/e1000_82575.c index 18593552d..db92cc207 100644 --- a/drivers/net/e1000/base/e1000_82575.c +++ b/drivers/net/e1000/base/e1000_82575.c @@ -1595,7 +1595,7 @@ STATIC s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw) case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: /* disable PCS autoneg and support parallel detect only */ pcs_autoneg = false; - /* fall through to default case */ + /* Fall through */ default: if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) { diff --git a/drivers/net/e1000/base/e1000_82575.h b/drivers/net/e1000/base/e1000_82575.h index 14887e25f..10383b03f 100644 --- a/drivers/net/e1000/base/e1000_82575.h +++ b/drivers/net/e1000/base/e1000_82575.h @@ -26,7 +26,6 @@ #define E1000_SW_SYNCH_MB 0x00000100 #define E1000_STAT_DEV_RST_SET 0x00100000 -#ifdef E1000_BIT_FIELDS struct e1000_adv_data_desc { __le64 buffer_addr; /* Address of the descriptor's data buffer */ union { @@ -89,7 +88,6 @@ struct e1000_adv_context_desc { } fields; } l4_setup; }; -#endif /* SRRCTL bit definitions */ #define E1000_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */ diff --git a/drivers/net/e1000/base/e1000_defines.h b/drivers/net/e1000/base/e1000_defines.h index 3d015fb20..c09635344 100644 --- a/drivers/net/e1000/base/e1000_defines.h +++ b/drivers/net/e1000/base/e1000_defines.h @@ -128,9 +128,7 @@ E1000_RXDEXT_STATERR_CXE | \ E1000_RXDEXT_STATERR_RXE) -#if !defined(EXTERNAL_RELEASE) || defined(E1000E_MQ) #define E1000_MRQC_ENABLE_RSS_2Q 0x00000001 -#endif /* !EXTERNAL_RELEASE || E1000E_MQ */ #define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000 #define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 #define E1000_MRQC_RSS_FIELD_IPV4 0x00020000 @@ -1221,9 +1219,7 @@ #define PCIE_LINK_SPEED_5000 0x02 #define PCIE_DEVICE_CONTROL2_16ms 0x0005 -#ifndef ETH_ADDR_LEN #define ETH_ADDR_LEN 6 -#endif #define PHY_REVISION_MASK 0xFFFFFFF0 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ @@ -1490,10 +1486,7 @@ /* Lan ID bit field offset in status register */ #define E1000_STATUS_LAN_ID_OFFSET 2 #define E1000_VFTA_ENTRIES 128 -#ifndef E1000_UNUSEDARG + #define E1000_UNUSEDARG -#endif /* E1000_UNUSEDARG */ -#ifndef ERROR_REPORT #define ERROR_REPORT(fmt) do { } while (0) -#endif /* ERROR_REPORT */ #endif /* _E1000_DEFINES_H_ */ diff --git a/drivers/net/e1000/base/e1000_hw.h b/drivers/net/e1000/base/e1000_hw.h index 85d09feae..6e2697248 100644 --- a/drivers/net/e1000/base/e1000_hw.h +++ b/drivers/net/e1000/base/e1000_hw.h @@ -931,7 +931,6 @@ struct e1000_shadow_ram { #define E1000_SHADOW_RAM_WORDS 2048 -#ifdef ULP_SUPPORT /* I218 PHY Ultra Low Power (ULP) states */ enum e1000_ulp_state { e1000_ulp_state_unknown, @@ -939,7 +938,6 @@ enum e1000_ulp_state { e1000_ulp_state_on, }; -#endif /* ULP_SUPPORT */ struct e1000_dev_spec_ich8lan { bool kmrn_lock_loss_workaround_enabled; struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS]; @@ -949,12 +947,10 @@ struct e1000_dev_spec_ich8lan { bool disable_k1_off; bool eee_disable; u16 eee_lp_ability; -#ifdef ULP_SUPPORT enum e1000_ulp_state ulp_state; bool ulp_capability_disabled; bool during_suspend_flow; bool during_dpg_exit; -#endif /* ULP_SUPPORT */ u16 lat_enc; u16 max_ltr_enc; bool smbus_disable; diff --git a/drivers/net/e1000/base/e1000_ich8lan.c b/drivers/net/e1000/base/e1000_ich8lan.c index 61dcc1e61..bf77bfa1d 100644 --- a/drivers/net/e1000/base/e1000_ich8lan.c +++ b/drivers/net/e1000/base/e1000_ich8lan.c @@ -51,11 +51,9 @@ STATIC bool e1000_check_mng_mode_pchlan(struct e1000_hw *hw); STATIC int e1000_rar_set_pch2lan(struct e1000_hw *hw, u8 *addr, u32 index); STATIC int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index); STATIC s32 e1000_sw_lcd_config_ich8lan(struct e1000_hw *hw); -#ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT STATIC void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw, u8 *mc_addr_list, u32 mc_addr_count); -#endif /* NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT */ STATIC s32 e1000_check_reset_block_ich8lan(struct e1000_hw *hw); STATIC s32 e1000_phy_hw_reset_ich8lan(struct e1000_hw *hw); STATIC s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active); @@ -297,13 +295,11 @@ STATIC s32 e1000_init_phy_workarounds_pchlan(struct e1000_hw *hw) */ e1000_gate_hw_phy_config_ich8lan(hw, true); -#ifdef ULP_SUPPORT /* It is not possible to be certain of the current state of ULP * so forcibly disable it. */ hw->dev_spec.ich8lan.ulp_state = e1000_ulp_state_unknown; -#endif /* ULP_SUPPORT */ ret_val = hw->phy.ops.acquire(hw); if (ret_val) { DEBUGOUT("Failed to initialize PHY flow\n"); @@ -701,9 +697,7 @@ STATIC s32 e1000_init_nvm_params_ich8lan(struct e1000_hw *hw) STATIC s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw) { struct e1000_mac_info *mac = &hw->mac; -#if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT) u16 pci_cfg; -#endif /* QV_RELEASE || !defined(NO_PCH_LPT_B0_SUPPORT) */ DEBUGFUNC("e1000_init_mac_params_ich8lan"); @@ -780,7 +774,6 @@ STATIC s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw) e1000_update_mc_addr_list_pch2lan; /* fall-through */ case e1000_pchlan: -#if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT) /* save PCH revision_id */ e1000_read_pci_cfg(hw, E1000_PCI_REVISION_ID_REG, &pci_cfg); /* SPT uses full byte for revision ID, @@ -790,7 +783,6 @@ STATIC s32 e1000_init_mac_params_ich8lan(struct e1000_hw *hw) hw->revision_id = (u8)(pci_cfg &= 0x00FF); else hw->revision_id = (u8)(pci_cfg &= 0x000F); -#endif /* QV_RELEASE || !defined(NO_PCH_LPT_B0_SUPPORT) */ /* check management mode */ mac->ops.check_mng_mode = e1000_check_mng_mode_pchlan; /* ID LED init */ @@ -1074,7 +1066,6 @@ STATIC s32 e1000_k1_workaround_lpt_lp(struct e1000_hw *hw, bool link) return ret_val; } -#ifdef ULP_SUPPORT /** * e1000_enable_ulp_lpt_lp - configure Ultra Low Power mode for LynxPoint-LP * @hw: pointer to the HW structure @@ -1453,7 +1444,6 @@ s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force) return ret_val; } -#endif /* ULP_SUPPORT */ /** @@ -2080,7 +2070,6 @@ STATIC int e1000_rar_set_pch_lpt(struct e1000_hw *hw, u8 *addr, u32 index) return -E1000_ERR_CONFIG; } -#ifndef NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT /** * e1000_update_mc_addr_list_pch2lan - Update Multicast addresses * @hw: pointer to the HW structure @@ -2125,7 +2114,6 @@ STATIC void e1000_update_mc_addr_list_pch2lan(struct e1000_hw *hw, hw->phy.ops.release(hw); } -#endif /* NO_NON_BLOCKING_PHY_MTA_UPDATE_SUPPORT */ /** * e1000_check_reset_block_ich8lan - Check if PHY reset is blocked * @hw: pointer to the HW structure @@ -2677,7 +2665,6 @@ void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw) hw->phy.ops.release(hw); } -#ifndef CRC32_OS_SUPPORT STATIC u32 e1000_calc_rx_da_crc(u8 mac[]) { u32 poly = 0xEDB88320; /* Polynomial for 802.3 CRC calculation */ @@ -2696,7 +2683,6 @@ STATIC u32 e1000_calc_rx_da_crc(u8 mac[]) return ~crc; } -#endif /* CRC32_OS_SUPPORT */ /** * e1000_lv_jumbo_workaround_ich8lan - required for jumbo frame operation * with 82579 PHY @@ -2741,13 +2727,8 @@ s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable) mac_addr[4] = (addr_high & 0xFF); mac_addr[5] = ((addr_high >> 8) & 0xFF); -#ifndef CRC32_OS_SUPPORT E1000_WRITE_REG(hw, E1000_PCH_RAICC(i), e1000_calc_rx_da_crc(mac_addr)); -#else /* CRC32_OS_SUPPORT */ - E1000_WRITE_REG(hw, E1000_PCH_RAICC(i), - E1000_CRC32(ETH_ADDR_LEN, mac_addr)); -#endif /* CRC32_OS_SUPPORT */ } /* Write Rx addresses to the PHY */ diff --git a/drivers/net/e1000/base/e1000_ich8lan.h b/drivers/net/e1000/base/e1000_ich8lan.h index 3be3ee246..5e89f4442 100644 --- a/drivers/net/e1000/base/e1000_ich8lan.h +++ b/drivers/net/e1000/base/e1000_ich8lan.h @@ -40,22 +40,16 @@ #define E1000_FWSM_WLOCK_MAC_MASK 0x0380 #define E1000_FWSM_WLOCK_MAC_SHIFT 7 -#if !defined(EXTERNAL_RELEASE) || defined(ULP_SUPPORT) #define E1000_FWSM_ULP_CFG_DONE 0x00000400 /* Low power cfg done */ -#endif /* !EXTERNAL_RELEASE || ULP_SUPPORT */ /* Shared Receive Address Registers */ #define E1000_SHRAL_PCH_LPT(_i) (0x05408 + ((_i) * 8)) #define E1000_SHRAH_PCH_LPT(_i) (0x0540C + ((_i) * 8)) -#if !defined(EXTERNAL_RELEASE) || defined(ULP_SUPPORT) #define E1000_H2ME 0x05B50 /* Host to ME */ -#endif /* !EXTERNAL_RELEASE || ULP_SUPPORT */ -#if !defined(EXTERNAL_RELEASE) || defined(ULP_SUPPORT) #define E1000_H2ME_ULP 0x00000800 /* ULP Indication Bit */ #define E1000_H2ME_ENFORCE_SETTINGS 0x00001000 /* Enforce Settings */ -#endif /* !EXTERNAL_RELEASE || ULP_SUPPORT */ #define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \ (ID_LED_OFF1_OFF2 << 8) | \ (ID_LED_OFF1_ON2 << 4) | \ @@ -68,11 +62,9 @@ #define E1000_ICH8_LAN_INIT_TIMEOUT 1500 -#if !defined(EXTERNAL_RELEASE) || defined(ULP_SUPPORT) /* FEXT register bit definition */ #define E1000_FEXT_PHY_CABLE_DISCONNECTED 0x00000004 -#endif /* !EXTERNAL_RELEASE || ULP_SUPPORT */ #define E1000_FEXTNVM_SW_CONFIG 1 #define E1000_FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* different on ICH8M */ @@ -89,9 +81,7 @@ /* bit for disabling packet buffer read */ #define E1000_FEXTNVM7_DISABLE_PB_READ 0x00040000 #define E1000_FEXTNVM7_SIDE_CLK_UNGATE 0x00000004 -#if !defined(EXTERNAL_RELEASE) || defined(ULP_SUPPORT) #define E1000_FEXTNVM7_DISABLE_SMB_PERST 0x00000020 -#endif /* !EXTERNAL_RELEASE || ULP_SUPPORT */ #define E1000_FEXTNVM8_UNBIND_DPG_FROM_MPHY 0x00000400 #define E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS 0x00000800 #define E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS 0x00001000 @@ -174,7 +164,6 @@ #define CV_SMB_CTRL PHY_REG(769, 23) #define CV_SMB_CTRL_FORCE_SMBUS 0x0001 -#if !defined(EXTERNAL_RELEASE) || defined(ULP_SUPPORT) /* I218 Ultra Low Power Configuration 1 Register */ #define I218_ULP_CONFIG1 PHY_REG(779, 16) #define I218_ULP_CONFIG1_START 0x0001 /* Start auto ULP config */ @@ -189,7 +178,7 @@ #define I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST 0x0800 #define I218_ULP_CONFIG1_DISABLE_SMB_PERST 0x1000 /* Disable on PERST# */ -#endif /* !EXTERNAL_RELEASE || ULP_SUPPORT */ + /* SMBus Address Phy Register */ #define HV_SMB_ADDR PHY_REG(768, 26) #define HV_SMB_ADDR_MASK 0x007F @@ -289,9 +278,8 @@ #define E1000_PCH_RAICC(_n) (0x05F50 + ((_n) * 4)) #define E1000_PCI_VENDOR_ID_REGISTER 0x00 -#if defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT) + #define E1000_PCI_REVISION_ID_REG 0x08 -#endif /* defined(QV_RELEASE) || !defined(NO_PCH_LPT_B0_SUPPORT) */ void e1000_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, bool state); void e1000_igp3_phy_powerdown_workaround_ich8lan(struct e1000_hw *hw); @@ -305,9 +293,7 @@ s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable); s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data); s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data); s32 e1000_set_eee_pchlan(struct e1000_hw *hw); -#ifdef ULP_SUPPORT s32 e1000_enable_ulp_lpt_lp(struct e1000_hw *hw, bool to_sx); s32 e1000_disable_ulp_lpt_lp(struct e1000_hw *hw, bool force); -#endif /* ULP_SUPPORT */ #endif /* _E1000_ICH8LAN_H_ */ void e1000_demote_ltr(struct e1000_hw *hw, bool demote, bool link); diff --git a/drivers/net/e1000/base/e1000_mac.h b/drivers/net/e1000/base/e1000_mac.h index 35a691f63..8a4f1635b 100644 --- a/drivers/net/e1000/base/e1000_mac.h +++ b/drivers/net/e1000/base/e1000_mac.h @@ -6,9 +6,7 @@ #define _E1000_MAC_H_ void e1000_init_mac_ops_generic(struct e1000_hw *hw); -#ifndef E1000_REMOVED #define E1000_REMOVED(a) (0) -#endif /* E1000_REMOVED */ void e1000_null_mac_generic(struct e1000_hw *hw); s32 e1000_null_ops_generic(struct e1000_hw *hw); s32 e1000_null_link_info(struct e1000_hw *hw, u16 *s, u16 *d); diff --git a/drivers/net/e1000/base/e1000_manage.c b/drivers/net/e1000/base/e1000_manage.c index 7fb63dd72..74b4480de 100644 --- a/drivers/net/e1000/base/e1000_manage.c +++ b/drivers/net/e1000/base/e1000_manage.c @@ -3,6 +3,7 @@ */ #include "e1000_api.h" +#include "e1000_manage.h" /** * e1000_calculate_checksum - Calculate checksum for buffer @@ -425,6 +426,7 @@ s32 e1000_host_interface_command(struct e1000_hw *hw, u8 *buffer, u32 length) return E1000_SUCCESS; } + /** * e1000_load_firmware - Writes proxy FW code buffer to host interface * and execute. @@ -543,5 +545,3 @@ s32 e1000_load_firmware(struct e1000_hw *hw, u8 *buffer, u32 length) return E1000_SUCCESS; } - - diff --git a/drivers/net/e1000/base/e1000_regs.h b/drivers/net/e1000/base/e1000_regs.h index a60506264..786e519e7 100644 --- a/drivers/net/e1000/base/e1000_regs.h +++ b/drivers/net/e1000/base/e1000_regs.h @@ -29,9 +29,7 @@ #define E1000_SCTL 0x00024 /* SerDes Control - RW */ #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */ #define E1000_FCAH 0x0002C /* Flow Control Address High -RW */ -#if !defined(EXTERNAL_RELEASE) || defined(ULP_SUPPORT) #define E1000_FEXT 0x0002C /* Future Extended - RW */ -#endif /* !EXTERNAL_RELEASE || ULP_SUPPORT */ #define E1000_FEXTNVM 0x00028 /* Future Extended NVM - RW */ #define E1000_FEXTNVM3 0x0003C /* Future Extended NVM 3 - RW */ #define E1000_FEXTNVM4 0x00024 /* Future Extended NVM 4 - RW */ @@ -353,6 +351,7 @@ #define E1000_TSCTC 0x040F8 /* TCP Segmentation Context Tx - R/clr */ #define E1000_TSCTFC 0x040FC /* TCP Segmentation Context Tx Fail - R/clr */ #define E1000_IAC 0x04100 /* Interrupt Assertion Count */ +/* Interrupt Cause */ #define E1000_ICRXPTC 0x04104 /* Interrupt Cause Rx Pkt Timer Expire Count */ #define E1000_ICRXATC 0x04108 /* Interrupt Cause Rx Abs Timer Expire Count */ #define E1000_ICTXPTC 0x0410C /* Interrupt Cause Tx Pkt Timer Expire Count */ @@ -475,12 +474,14 @@ #define E1000_WUC 0x05800 /* Wakeup Control - RW */ #define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */ #define E1000_WUS 0x05810 /* Wakeup Status - RO */ +/* Management registers */ #define E1000_MANC 0x05820 /* Management Control - RW */ #define E1000_IPAV 0x05838 /* IP Address Valid - RW */ #define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */ #define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */ #define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */ #define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */ +/* MSI-X Table Register Descriptions */ #define E1000_PBACL 0x05B68 /* MSIx PBA Clear - Read/Write 1's to clear */ #define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */ #define E1000_HOST_IF 0x08800 /* Host Interface */ -- 2.17.1