From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id C5C0BA0524; Fri, 3 Jul 2020 20:57:56 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 234D41DCD3; Fri, 3 Jul 2020 20:57:56 +0200 (CEST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by dpdk.org (Postfix) with ESMTP id 252DF1DCD1 for ; Fri, 3 Jul 2020 20:57:55 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7F27F2F; Fri, 3 Jul 2020 11:57:54 -0700 (PDT) Received: from qc2400f-1.austin.arm.com (qc2400f-1.austin.arm.com [10.118.12.27]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6B3313F68F; Fri, 3 Jul 2020 11:57:54 -0700 (PDT) From: Honnappa Nagarahalli To: dev@dpdk.org, honnappa.nagarahalli@arm.com, ruifeng.wang@arm.com, jerinj@marvell.com, hemant.agrawal@nxp.com, ajit.khaparde@broadcom.com, igorch@amazon.com, thomas@monjalon.net, viacheslavo@mellanox.com, arybchenko@solarflare.com, bruce.richardson@intel.com Cc: nd@arm.com Date: Fri, 3 Jul 2020 13:57:39 -0500 Message-Id: <20200703185741.22184-1-honnappa.nagarahalli@arm.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200410164127.54229-1-gavin.hu@arm.com> References: <20200410164127.54229-1-gavin.hu@arm.com> Subject: [dpdk-dev] [PATCH v3 1/3] eal: adjust barriers for IO on Armv8-a X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Change the barrier APIs for IO to reflect that Armv8-a is other-multi-copy atomicity memory model. Armv8-a memory model has been strengthened to require other-multi-copy atomicity. This property requires memory accesses from an observer to become visible to all other observers simultaneously [3]. This means a) A write arriving at an endpoint shared between multiple CPUs is visible to all CPUs b) A write that is visible to all CPUs is also visible to all other observers in the shareability domain This allows for using cheaper DMB instructions in the place of DSB for devices that are visible to all CPUs (i.e. devices that DPDK caters to). Please refer to [1], [2] and [3] for more information. [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=22ec71615d824f4f11d38d0e55a88d8956b7e45f [2] https://www.youtube.com/watch?v=i6DayghhA8Q [3] https://www.cl.cam.ac.uk/~pes20/armv8-mca/ Signed-off-by: Honnappa Nagarahalli Acked-by: Jerin Jacob Tested-by: Ruifeng Wang --- lib/librte_eal/arm/include/rte_atomic_64.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/lib/librte_eal/arm/include/rte_atomic_64.h b/lib/librte_eal/arm/include/rte_atomic_64.h index 7b7099cdc..e42f69edc 100644 --- a/lib/librte_eal/arm/include/rte_atomic_64.h +++ b/lib/librte_eal/arm/include/rte_atomic_64.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: BSD-3-Clause * Copyright(c) 2015 Cavium, Inc - * Copyright(c) 2019 Arm Limited + * Copyright(c) 2020 Arm Limited */ #ifndef _RTE_ATOMIC_ARM64_H_ @@ -19,11 +19,11 @@ extern "C" { #include #include -#define rte_mb() asm volatile("dsb sy" : : : "memory") +#define rte_mb() asm volatile("dmb osh" : : : "memory") -#define rte_wmb() asm volatile("dsb st" : : : "memory") +#define rte_wmb() asm volatile("dmb oshst" : : : "memory") -#define rte_rmb() asm volatile("dsb ld" : : : "memory") +#define rte_rmb() asm volatile("dmb oshld" : : : "memory") #define rte_smp_mb() asm volatile("dmb ish" : : : "memory") @@ -37,9 +37,9 @@ extern "C" { #define rte_io_rmb() rte_rmb() -#define rte_cio_wmb() asm volatile("dmb oshst" : : : "memory") +#define rte_cio_wmb() rte_wmb() -#define rte_cio_rmb() asm volatile("dmb oshld" : : : "memory") +#define rte_cio_rmb() rte_rmb() /*------------------------ 128 bit atomic operations -------------------------*/ -- 2.17.1