From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 22B5BA0540; Mon, 13 Jul 2020 17:14:48 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 0A0191D700; Mon, 13 Jul 2020 17:14:48 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id B04DC1D615 for ; Mon, 13 Jul 2020 17:14:45 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 06DF9gpw016477; Mon, 13 Jul 2020 08:14:45 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0818; bh=XIoRUEblCfX1RrVCbNyJAjMu+1I69ptwDJVyAe4zFTY=; b=DDELmNUZqQTjjYbna+wpfEr56bwnblvWJaWcTJJK1W99SfgyfCIn46gbQX+Io8YIXrON t2jGOJN6m0tgOMTfkYX5FJCXtDii2rUzkwoSc89RlG3syi/7G1JjhpAwBJVMDv0uGDcG JwjOmHPPTqgQYazd4n6D+TMuVw7vsI3wpYwTp00bXzoSjBfTByclmUCVvNg+m27YsP20 sAyAxKtsK2coD+INjL1dw8gRV4j27Tksflf3fxQtd9ffwcQ8H8HMveYRAg81gHWiVIHP gPkLKqkbIbS+UerD89YDv9mAIb5rV58jf75Ei1a+h1vPF3V7gaA1Qhh3+xc7JQHQ1uG9 2A== Received: from sc-exch01.marvell.com ([199.233.58.181]) by mx0b-0016f401.pphosted.com with ESMTP id 328mmhh7qs-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Mon, 13 Jul 2020 08:14:45 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 13 Jul 2020 08:14:42 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Mon, 13 Jul 2020 08:14:43 -0700 Received: from dut1171.mv.qlogic.com (unknown [10.112.88.18]) by maili.marvell.com (Postfix) with ESMTP id 2C2383F703F; Mon, 13 Jul 2020 08:14:43 -0700 (PDT) Received: from dut1171.mv.qlogic.com (localhost [127.0.0.1]) by dut1171.mv.qlogic.com (8.14.7/8.14.7) with ESMTP id 06DFEgHG017609; Mon, 13 Jul 2020 08:14:42 -0700 Received: (from root@localhost) by dut1171.mv.qlogic.com (8.14.7/8.14.7/Submit) id 06DFEgRD017599; Mon, 13 Jul 2020 08:14:42 -0700 From: Manish Chopra To: , , , CC: , , , , , , , , , , , Date: Mon, 13 Jul 2020 08:13:14 -0700 Message-ID: <20200713151319.17547-3-manishc@marvell.com> X-Mailer: git-send-email 2.12.0 In-Reply-To: <20200713151319.17547-1-manishc@marvell.com> References: <20200713151319.17547-1-manishc@marvell.com> MIME-Version: 1.0 Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-07-13_14:2020-07-13, 2020-07-13 signatures=0 Subject: [dpdk-dev] [PATCH v2 2/7] drivers: add generic API to find PCI extended cap X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" By adding generic API, this patch removes individual functions/defines implemented by drivers to find PCI extended capability. Signed-off-by: Manish Chopra Signed-off-by: Igor Russkikh --- drivers/bus/pci/pci_common.c | 41 +++++++++++++++++ drivers/bus/pci/rte_bus_pci.h | 11 +++++ drivers/net/ice/ice_ethdev.c | 53 ++-------------------- drivers/net/nfp/nfpcore/nfp_cpp_pcie_ops.c | 48 ++------------------ lib/librte_pci/rte_pci_regs.h | 2 +- 5 files changed, 60 insertions(+), 95 deletions(-) diff --git a/drivers/bus/pci/pci_common.c b/drivers/bus/pci/pci_common.c index a8e5fd52c..5117c8e7b 100644 --- a/drivers/bus/pci/pci_common.c +++ b/drivers/bus/pci/pci_common.c @@ -23,6 +23,7 @@ #include #include #include +#include #include "private.h" @@ -665,6 +666,46 @@ rte_pci_get_iommu_class(void) return iova_mode; } +int rte_pci_find_next_ext_capability(struct rte_pci_device *dev, int cap) +{ + int pos = PCI_CFG_SPACE_SIZE; + uint32_t header; + int ttl; + + /* minimum 8 bytes per capability */ + ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; + + if (rte_pci_read_config(dev, &header, 4, pos) < 0) { + RTE_LOG(ERR, EAL, "error in reading extended capabilities\n"); + return -EINVAL; + } + + /* + * If we have no capabilities, this is indicated by cap ID, + * cap version and next pointer all being 0. + */ + if (header == 0) + return 0; + + while (ttl-- > 0) { + if (PCI_EXT_CAP_ID(header) == cap) + return pos; + + pos = PCI_EXT_CAP_NEXT(header); + + if (pos < PCI_CFG_SPACE_SIZE) + break; + + if (rte_pci_read_config(dev, &header, 4, pos) < 0) { + RTE_LOG(ERR, EAL, + "error in reading extended capabilities\n"); + return -EINVAL; + } + } + + return 0; +} + struct rte_pci_bus rte_pci_bus = { .bus = { .scan = rte_pci_scan, diff --git a/drivers/bus/pci/rte_bus_pci.h b/drivers/bus/pci/rte_bus_pci.h index 29bea6d70..3cc66220a 100644 --- a/drivers/bus/pci/rte_bus_pci.h +++ b/drivers/bus/pci/rte_bus_pci.h @@ -224,6 +224,17 @@ void rte_pci_unmap_device(struct rte_pci_device *dev); */ void rte_pci_dump(FILE *f); +/** + * Find device's extended capability + * + * @param dev + * A pointer to rte_pci_device structure + * + * @param cap + * Extended capability to find + */ +int rte_pci_find_next_ext_capability(struct rte_pci_device *dev, int cap); + /** * Register a PCI driver. * diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c index 3534d18ca..0724324d2 100644 --- a/drivers/net/ice/ice_ethdev.c +++ b/drivers/net/ice/ice_ethdev.c @@ -4,6 +4,8 @@ #include #include +#include +#include #include #include @@ -1730,53 +1732,6 @@ ice_pf_setup(struct ice_pf *pf) return 0; } -/* PCIe configuration space setting */ -#define PCI_CFG_SPACE_SIZE 256 -#define PCI_CFG_SPACE_EXP_SIZE 4096 -#define PCI_EXT_CAP_ID(header) (int)((header) & 0x0000ffff) -#define PCI_EXT_CAP_NEXT(header) (((header) >> 20) & 0xffc) -#define PCI_EXT_CAP_ID_DSN 0x03 - -static int -ice_pci_find_next_ext_capability(struct rte_pci_device *dev, int cap) -{ - uint32_t header; - int ttl; - int pos = PCI_CFG_SPACE_SIZE; - - /* minimum 8 bytes per capability */ - ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; - - if (rte_pci_read_config(dev, &header, 4, pos) < 0) { - PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n"); - return -1; - } - - /* - * If we have no capabilities, this is indicated by cap ID, - * cap version and next pointer all being 0. - */ - if (header == 0) - return 0; - - while (ttl-- > 0) { - if (PCI_EXT_CAP_ID(header) == cap) - return pos; - - pos = PCI_EXT_CAP_NEXT(header); - - if (pos < PCI_CFG_SPACE_SIZE) - break; - - if (rte_pci_read_config(dev, &header, 4, pos) < 0) { - PMD_INIT_LOG(ERR, "ice error reading extended capabilities\n"); - return -1; - } - } - - return 0; -} - /* * Extract device serial number from PCIe Configuration Space and * determine the pkg file path according to the DSN. @@ -1789,9 +1744,9 @@ ice_pkg_file_search_path(struct rte_pci_device *pci_dev, char *pkg_file) uint32_t dsn_low, dsn_high; memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE); - pos = ice_pci_find_next_ext_capability(pci_dev, PCI_EXT_CAP_ID_DSN); + pos = rte_pci_find_next_ext_capability(pci_dev, PCI_EXT_CAP_ID_DSN); - if (pos) { + if (pos > 0) { rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4); rte_pci_read_config(pci_dev, &dsn_high, 4, pos + 8); snprintf(opt_ddp_filename, ICE_MAX_PKG_FILENAME_SIZE, diff --git a/drivers/net/nfp/nfpcore/nfp_cpp_pcie_ops.c b/drivers/net/nfp/nfpcore/nfp_cpp_pcie_ops.c index 0b9db974e..b11d8148a 100644 --- a/drivers/net/nfp/nfpcore/nfp_cpp_pcie_ops.c +++ b/drivers/net/nfp/nfpcore/nfp_cpp_pcie_ops.c @@ -35,6 +35,8 @@ #include #include +#include +#include #include "nfp_cpp.h" #include "nfp_target.h" @@ -746,50 +748,6 @@ nfp6000_set_interface(struct rte_pci_device *dev, struct nfp_cpp *cpp) return 0; } -#define PCI_CFG_SPACE_SIZE 256 -#define PCI_CFG_SPACE_EXP_SIZE 4096 -#define PCI_EXT_CAP_ID(header) (int)(header & 0x0000ffff) -#define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc) -#define PCI_EXT_CAP_ID_DSN 0x03 -static int -nfp_pci_find_next_ext_capability(struct rte_pci_device *dev, int cap) -{ - uint32_t header; - int ttl; - int pos = PCI_CFG_SPACE_SIZE; - - /* minimum 8 bytes per capability */ - ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; - - if (rte_pci_read_config(dev, &header, 4, pos) < 0) { - printf("nfp error reading extended capabilities\n"); - return -1; - } - - /* - * If we have no capabilities, this is indicated by cap ID, - * cap version and next pointer all being 0. - */ - if (header == 0) - return 0; - - while (ttl-- > 0) { - if (PCI_EXT_CAP_ID(header) == cap) - return pos; - - pos = PCI_EXT_CAP_NEXT(header); - if (pos < PCI_CFG_SPACE_SIZE) - break; - - if (rte_pci_read_config(dev, &header, 4, pos) < 0) { - printf("nfp error reading extended capabilities\n"); - return -1; - } - } - - return 0; -} - static int nfp6000_set_serial(struct rte_pci_device *dev, struct nfp_cpp *cpp) { @@ -798,7 +756,7 @@ nfp6000_set_serial(struct rte_pci_device *dev, struct nfp_cpp *cpp) int serial_len = 6; int pos; - pos = nfp_pci_find_next_ext_capability(dev, PCI_EXT_CAP_ID_DSN); + pos = rte_pci_find_next_ext_capability(dev, PCI_EXT_CAP_ID_DSN); if (pos <= 0) { printf("PCI_EXT_CAP_ID_DSN not found. nfp set serial failed\n"); return -1; diff --git a/lib/librte_pci/rte_pci_regs.h b/lib/librte_pci/rte_pci_regs.h index 1d11f4de5..108193049 100644 --- a/lib/librte_pci/rte_pci_regs.h +++ b/lib/librte_pci/rte_pci_regs.h @@ -686,7 +686,7 @@ #define PCI_EXP_SLTSTA2 58 /* Slot Status 2 */ /* Extended Capabilities (PCI-X 2.0 and Express) */ -#define PCI_EXT_CAP_ID(header) (header & 0x0000ffff) +#define PCI_EXT_CAP_ID(header) (int)(header & 0x0000ffff) #define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf) #define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc) -- 2.17.1