From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id BBB1BA0540; Tue, 14 Jul 2020 15:46:35 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id BE02E1D570; Tue, 14 Jul 2020 15:46:29 +0200 (CEST) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id 38D131D412; Tue, 14 Jul 2020 15:46:25 +0200 (CEST) IronPort-SDR: 8c3KuC3eOOj2Iyl7uWBSxSFaiCgkaq0SCz5j5hKw2hDKB9dw3ag7bQSQHFcUXRB7jI0sHrqasU 6JltkS0rDL2g== X-IronPort-AV: E=McAfee;i="6000,8403,9681"; a="146905631" X-IronPort-AV: E=Sophos;i="5.75,350,1589266800"; d="scan'208";a="146905631" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jul 2020 06:46:24 -0700 IronPort-SDR: P1woQovwT77/7FM+EdrKTlNmUA/23yj/E1vK+UmpeqLCp4KcRp1QR6jXSTBEo4Osz0+AtebQmS qNyeU64ZAw/A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,350,1589266800"; d="scan'208";a="268658781" Received: from figo-optiplex-9020.sh.intel.com ([10.238.169.50]) by fmsmga007.fm.intel.com with ESMTP; 14 Jul 2020 06:46:23 -0700 From: Tianfei zhang To: dev@dpdk.org, rosen.xu@intel.com Cc: Tianfei Zhang , stable@dpdk.org Date: Wed, 15 Jul 2020 05:35:09 +0800 Message-Id: <20200714213509.13650-2-tianfei.zhang@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200714213509.13650-1-tianfei.zhang@intel.com> References: <20200709163553.8677-1-tianfei.zhang@intel.com> <20200714213509.13650-1-tianfei.zhang@intel.com> Subject: [dpdk-dev] [PATCH v3 2/2] raw/ifpga/base: fix NIOS SPI initial X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Tianfei Zhang Add fecmode setting on NIOS SPI primary initialization. this SPI is shared by NIOS core inside FPGA, NIOS will use this SPI primary to do some one-time initialization after power up, and then release the control to DPDK. Fix the timeout initialization for polling the NIOS_INIT_DONE. Fixes: bc44402f ("raw/ifpga/base: configure FEC mode") Cc: stable@dpdk.org Signed-off-by: Tianfei Zhang --- v3: resend the patch with threaded option for git send-email v2: fix coding style issue --- drivers/raw/ifpga/base/ifpga_fme.c | 27 ++++++++++++++++++++------- drivers/raw/ifpga/base/opae_spi.h | 1 + 2 files changed, 21 insertions(+), 7 deletions(-) diff --git a/drivers/raw/ifpga/base/ifpga_fme.c b/drivers/raw/ifpga/base/ifpga_fme.c index c31a94cf8..9057087b5 100644 --- a/drivers/raw/ifpga/base/ifpga_fme.c +++ b/drivers/raw/ifpga/base/ifpga_fme.c @@ -979,28 +979,32 @@ struct ifpga_feature_ops fme_spi_master_ops = { static int nios_spi_wait_init_done(struct altera_spi_device *dev) { u32 val = 0; - unsigned long timeout = msecs_to_timer_cycles(10000); + unsigned long timeout = rte_get_timer_cycles() + + msecs_to_timer_cycles(10000); unsigned long ticks; int major_version; + int fecmode = FEC_MODE_NO; if (spi_reg_read(dev, NIOS_VERSION, &val)) return -EIO; - major_version = (val >> NIOS_VERSION_MAJOR_SHIFT) & - NIOS_VERSION_MAJOR; - dev_debug(dev, "A10 NIOS FW version %d\n", major_version); + major_version = + (val & NIOS_VERSION_MAJOR) >> NIOS_VERSION_MAJOR_SHIFT; + dev_info(dev, "A10 NIOS FW version %d\n", major_version); if (major_version >= 3) { /* read NIOS_INIT to check if PKVL INIT done or not */ if (spi_reg_read(dev, NIOS_INIT, &val)) return -EIO; + dev_debug(dev, "read NIOS_INIT: 0x%x\n", val); + /* check if PKVLs are initialized already */ if (val & NIOS_INIT_DONE || val & NIOS_INIT_START) goto nios_init_done; /* start to config the default FEC mode */ - val = NIOS_INIT_START; + val = fecmode | NIOS_INIT_START; if (spi_reg_write(dev, NIOS_INIT, val)) return -EIO; @@ -1010,14 +1014,23 @@ static int nios_spi_wait_init_done(struct altera_spi_device *dev) do { if (spi_reg_read(dev, NIOS_INIT, &val)) return -EIO; - if (val) + if (val & NIOS_INIT_DONE) break; ticks = rte_get_timer_cycles(); if (time_after(ticks, timeout)) return -ETIMEDOUT; msleep(100); - } while (!val); + } while (1); + + /* get the fecmode */ + if (spi_reg_read(dev, NIOS_INIT, &val)) + return -EIO; + dev_debug(dev, "read NIOS_INIT: 0x%x\n", val); + fecmode = (val & REQ_FEC_MODE) >> REQ_FEC_MODE_SHIFT; + dev_info(dev, "fecmode: 0x%x, %s\n", fecmode, + (fecmode == FEC_MODE_KR) ? "kr" : + ((fecmode == FEC_MODE_RS) ? "rs" : "no")); return 0; } diff --git a/drivers/raw/ifpga/base/opae_spi.h b/drivers/raw/ifpga/base/opae_spi.h index d20a4c3ed..73a227673 100644 --- a/drivers/raw/ifpga/base/opae_spi.h +++ b/drivers/raw/ifpga/base/opae_spi.h @@ -153,6 +153,7 @@ int spi_reg_read(struct altera_spi_device *dev, u32 reg, u32 *val); #define NIOS_INIT 0x1000 #define REQ_FEC_MODE GENMASK(23, 8) +#define REQ_FEC_MODE_SHIFT 8 #define FEC_MODE_NO 0x0 #define FEC_MODE_KR 0x5555 #define FEC_MODE_RS 0xaaaa -- 2.17.1