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X-Microsoft-Antispam-Message-Info: 7gDbWaFbLnYAfh1u54VETfs02blZmoJ15BMt4gx6eDTiVTcCMLSYK2GN+8JmSPyjMhzfDxDEL2LThqcwAwIktJRN6SDqpAgA/CmUHBcgX5FY/lF4xE3pv9ONKM2QLO1iXuYm3pWJiGEsquOZ5NTFMo+Y5396Q5MjVYbIicim3nk97hLYuFQHxOR+no9cfm67IPYOLpUd4VPjtwoz4Hr15Fp2LXfSrFjVIKSSbOXWJxLenifRTNrGPlQKok7prYFoeT47B5pht0ce1Rii21EzZeTVs0zuAWvOF2GM+hW9mUjmG0dhacd3nyrVCrkGlxeFNbWD8XKxHLfcbeH84jUcvA== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:AM0PR05MB4866.eurprd05.prod.outlook.com; PTR:; CAT:NONE; SFTY:; SFS:(4636009)(376002)(136003)(366004)(396003)(39860400002)(346002)(52116002)(6506007)(2906002)(54906003)(316002)(6486002)(1076003)(5660300002)(8936002)(8676002)(478600001)(6666004)(6512007)(26005)(16526019)(186003)(66946007)(66556008)(66476007)(86362001)(2616005)(956004)(4326008)(83380400001)(36756003); DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData: InWYeWebcI8icFUOIxPM3Xa6yN5BZvR/yeJFs8Pa3OTfsseolQT04ecca3Ix+oxSNXJup07F9GhiHEgNqmTcyi2rNhg8F+E+u2UbfVdjuEWDqLMyUhFMASs6Vw8GIup+v1Ka81WCq/v8o+FEGAI6y47Oaeyfo5P1uEeghBpMEKFYyxtf4Z4nMaDgdQ02eHMUkzcnhL3OP4Vh2oaVaDeiLbokf26ztlHHFfaDeIoKRjiw0B0X9bhCSYSgvBLqWL85Fzqu+5eruN0e/q/o3UZpsZVWeBRYsBXH3zo5c7uhmo1fHWYNfn6LnRwW1fGkHmI7uBmvPKhajdrr8Cdiwlo+2izyedb5o7g6m9Q+/rSfCNbDKbYdDFdoIzLb5T+PdZit8RALF+uvYRKxC/22vxIlAfgn8lO5a7nG+mTUcnY7+PCip6gIMQJnLjiH+5zQHpQDKuqTVHDdWubY61zqAby0mQA3XI7CzlFk3AZ7JVzAtoX4BG5Q4FFlIWcmOW+AWcFM X-OriginatorOrg: Mellanox.com X-MS-Exchange-CrossTenant-Network-Message-Id: fff92490-40f4-431d-41e2-08d832552afa X-MS-Exchange-CrossTenant-AuthSource: AM0PR05MB4866.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jul 2020 17:47:44.9616 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: a652971c-7d2e-4d9b-a6a4-d149256f461b X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: A/rMB4w5GzBciO0fr2JtV8CDKuo/TngmDUfkGfjwdKvJJ/+QyL7L4pVkdJr+6W3a94bFnS6+LKO5Lk//0GL1Hw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR05MB6227 Subject: [dpdk-dev] [PATCH v12 01/10] eal: introduce macro for bit definition X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" There are several drivers which duplicate bit generation macro. Introduce a generic bit macros so that such drivers avoid redefining same in multiple drivers. Signed-off-by: Parav Pandit Acked-by: Matan Azrad Acked-by: Morten Brørup --- Changelog: v11->v12: - Define RTE_BIT32 macro as well - Use RTE_BIT32 and RTE_BIT64 macros in bitops as well v4->v5: - Addressed comments from Morten Brørup - Renamed newly added macro to RTE_BIT64 - Added doxygen comment section for the macro v1->v2: - Addressed comments from Thomas and Gaten. - Avoided new file, added macro to rte_bitops.h --- lib/librte_eal/include/rte_bitops.h | 34 +++++++++++++++++++++-------- 1 file changed, 25 insertions(+), 9 deletions(-) diff --git a/lib/librte_eal/include/rte_bitops.h b/lib/librte_eal/include/rte_bitops.h index 740927f3b..141e8ea73 100644 --- a/lib/librte_eal/include/rte_bitops.h +++ b/lib/librte_eal/include/rte_bitops.h @@ -17,6 +17,22 @@ #include #include +/** + * Get the uint64_t value for a specified bit set. + * + * @param nr + * The bit number in range of 0 to 63. + */ +#define RTE_BIT64(nr) (UINT64_C(1) << (nr)) + +/** + * Get the uint32_t value for a specified bit set. + * + * @param nr + * The bit number in range of 0 to 31. + */ +#define RTE_BIT32(nr) (UINT32_C(1) << (nr)) + /*------------------------ 32-bit relaxed operations ------------------------*/ /** @@ -59,7 +75,7 @@ rte_bit_relaxed_set32(unsigned int nr, volatile uint32_t *addr) { RTE_ASSERT(nr < 32); - uint32_t mask = UINT32_C(1) << nr; + uint32_t mask = RTE_BIT32(nr); *addr = (*addr) | mask; } @@ -80,7 +96,7 @@ rte_bit_relaxed_clear32(unsigned int nr, volatile uint32_t *addr) { RTE_ASSERT(nr < 32); - uint32_t mask = UINT32_C(1) << nr; + uint32_t mask = RTE_BIT32(nr); *addr = (*addr) & (~mask); } @@ -104,7 +120,7 @@ rte_bit_relaxed_test_and_set32(unsigned int nr, volatile uint32_t *addr) { RTE_ASSERT(nr < 32); - uint32_t mask = UINT32_C(1) << nr; + uint32_t mask = RTE_BIT32(nr); uint32_t val = *addr; *addr = val | mask; return val & mask; @@ -130,7 +146,7 @@ rte_bit_relaxed_test_and_clear32(unsigned int nr, volatile uint32_t *addr) { RTE_ASSERT(nr < 32); - uint32_t mask = UINT32_C(1) << nr; + uint32_t mask = RTE_BIT32(nr); uint32_t val = *addr; *addr = val & (~mask); return val & mask; @@ -157,7 +173,7 @@ rte_bit_relaxed_get64(unsigned int nr, volatile uint64_t *addr) { RTE_ASSERT(nr < 64); - uint64_t mask = UINT64_C(1) << nr; + uint64_t mask = RTE_BIT64(nr); return (*addr) & mask; } @@ -178,7 +194,7 @@ rte_bit_relaxed_set64(unsigned int nr, volatile uint64_t *addr) { RTE_ASSERT(nr < 64); - uint64_t mask = UINT64_C(1) << nr; + uint64_t mask = RTE_BIT64(nr); (*addr) = (*addr) | mask; } @@ -199,7 +215,7 @@ rte_bit_relaxed_clear64(unsigned int nr, volatile uint64_t *addr) { RTE_ASSERT(nr < 64); - uint64_t mask = UINT64_C(1) << nr; + uint64_t mask = RTE_BIT64(nr); *addr = (*addr) & (~mask); } @@ -223,7 +239,7 @@ rte_bit_relaxed_test_and_set64(unsigned int nr, volatile uint64_t *addr) { RTE_ASSERT(nr < 64); - uint64_t mask = UINT64_C(1) << nr; + uint64_t mask = RTE_BIT64(nr); uint64_t val = *addr; *addr = val | mask; return val; @@ -249,7 +265,7 @@ rte_bit_relaxed_test_and_clear64(unsigned int nr, volatile uint64_t *addr) { RTE_ASSERT(nr < 64); - uint64_t mask = UINT64_C(1) << nr; + uint64_t mask = RTE_BIT64(nr); uint64_t val = *addr; *addr = val & (~mask); return val & mask; -- 2.26.2