From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id B575BA04B0; Fri, 7 Aug 2020 18:08:33 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 691E71C11F; Fri, 7 Aug 2020 18:06:46 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id 4E0E01C0CD for ; Fri, 7 Aug 2020 18:06:42 +0200 (CEST) IronPort-SDR: M5AGP8viWFGnbXfsbu/jlBJsHfde/cnRKToO/mDD/PCzFOkbUq8AxlBasH4Efd2AaxnW1QGC5e 5ehXm5dr0cDQ== X-IronPort-AV: E=McAfee;i="6000,8403,9705"; a="171183134" X-IronPort-AV: E=Sophos;i="5.75,446,1589266800"; d="scan'208";a="171183134" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Aug 2020 09:06:41 -0700 IronPort-SDR: xgcmzQ5aNO8/0lKiRPJ/vnapbVyyEa/enilWSQyKZk4CNdZ2rrQgktyENjIr3g9Q02grCrYHBk j5NRa+b72+eQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,446,1589266800"; d="scan'208";a="275407942" Received: from silpixa00399953.ir.intel.com (HELO silpixa00399953.ger.corp.intel.com) ([10.237.222.53]) by fmsmga007.fm.intel.com with ESMTP; 07 Aug 2020 09:06:40 -0700 From: Ciara Power To: dev@dpdk.org Cc: bruce.richardson@intel.com, Ciara Power , Matan Azrad , Shahaf Shuler , Viacheslav Ovsiienko Date: Fri, 7 Aug 2020 16:58:58 +0100 Message-Id: <20200807155859.63888-12-ciara.power@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200807155859.63888-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> Subject: [dpdk-dev] [PATCH 20.11 11/12] net/mlx5: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. Cc: Matan Azrad Cc: Shahaf Shuler Cc: Viacheslav Ovsiienko Signed-off-by: Ciara Power --- drivers/net/mlx5/mlx5_ethdev.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/mlx5/mlx5_ethdev.c b/drivers/net/mlx5/mlx5_ethdev.c index cefb45064e..f322f82029 100644 --- a/drivers/net/mlx5/mlx5_ethdev.c +++ b/drivers/net/mlx5/mlx5_ethdev.c @@ -479,7 +479,8 @@ mlx5_select_rx_function(struct rte_eth_dev *dev) eth_rx_burst_t rx_pkt_burst = mlx5_rx_burst; MLX5_ASSERT(dev != NULL); - if (mlx5_check_vec_rx_support(dev) > 0) { + if (mlx5_check_vec_rx_support(dev) > 0 && + rte_get_max_simd_bitwidth() >= RTE_MAX_128_SIMD) { rx_pkt_burst = mlx5_rx_burst_vec; DRV_LOG(DEBUG, "port %u selected Rx vectorized function", dev->data->port_id); -- 2.17.1