From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id AD799A04B4; Sat, 8 Aug 2020 16:37:09 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id ADCA92BF9; Sat, 8 Aug 2020 16:37:08 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 07F692BF9 for ; Sat, 8 Aug 2020 16:37:06 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 078EVPHQ012912; Sat, 8 Aug 2020 07:36:51 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0818; bh=keY3nFWuUS93XNH1qlCqa889eNL3wGrUTp2OW3v2hqY=; b=SXIudBbUmbAj0AXrdaS5+2V5VFS0jwDqTmplVpDj1hTeMcAUAONU+q4sfTvur2hJkhUW zF3MY50XoLTyk0QEF/FZkflD3eknRjO/nxJxVBdCPAiSboXMZFe2HfWru8+A8ChwC322 X3xENRrDenS6UJojybeEh9tBbxA8rQrCmn+5ypX30kr57thMx9PlLWwXRcv0y0DFoRa6 X1VbqhU9aAQgiabqm8FwObIvvHJUNHLPpOGPmYhF4EFNdWc4UWrj9lke2IrjgJ+zeqFJ S1B8g6CeSuullcR79KgtmhWWGDZXLDA9majvx9pRnC8a2+EDnFVzf/mqF4+jFMWcPb0B Aw== Received: from sc-exch02.marvell.com ([199.233.58.182]) by mx0a-0016f401.pphosted.com with ESMTP id 32ssdngpb9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Sat, 08 Aug 2020 07:36:51 -0700 Received: from DC5-EXCH01.marvell.com (10.69.176.38) by SC-EXCH02.marvell.com (10.93.176.82) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 8 Aug 2020 07:36:49 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sat, 8 Aug 2020 07:36:48 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sat, 8 Aug 2020 07:36:48 -0700 Received: from localhost.localdomain (unknown [10.28.34.15]) by maili.marvell.com (Postfix) with ESMTP id 7F4443F703F; Sat, 8 Aug 2020 07:36:35 -0700 (PDT) From: To: Thomas Monjalon , Ferruh Yigit , Andrew Rybchenko CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Kiran Kumar K Date: Sat, 8 Aug 2020 20:06:30 +0530 Message-ID: <20200808143631.1704756-1-kirankumark@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200807120434.1701726-1-kirankumark@marvell.com> References: <20200807120434.1701726-1-kirankumark@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-08-08_06:2020-08-06, 2020-08-08 signatures=0 Subject: [dpdk-dev] [PATCH v2 1/2] ethdev: add level support for RSS offload types X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Kiran Kumar K This patch reserves 2 bits as input selection to select Inner and outer layers for RSS computation. It is combined with existing ETH_RSS_* to choose Inner or outer layers for L2, L3 and L4. This functionality already exists in rte_flow through level parameter in RSS action configuration rte_flow_action_rss. Signed-off-by: Kiran Kumar K --- v2 changes: * Reserved bit 50 & 51 lib/librte_ethdev/rte_ethdev.h | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/lib/librte_ethdev/rte_ethdev.h b/lib/librte_ethdev/rte_ethdev.h index d29930fd8..28184cc85 100644 --- a/lib/librte_ethdev/rte_ethdev.h +++ b/lib/librte_ethdev/rte_ethdev.h @@ -552,6 +552,33 @@ struct rte_eth_rss_conf { #define RTE_ETH_RSS_L3_PRE64 (1ULL << 53) #define RTE_ETH_RSS_L3_PRE96 (1ULL << 52) +/* + * We use the following macros to combine with the above layers to choose + * inner and outer layers or both for RSS computation. + * Note: Default is 0: inner layers, 1: outer layers, 2: both + * bit 50 and 51 are reserved for this. + */ + +/** + * Level 0, It basically stands for the innermost encapsulation level RSS + * can be performed on according to PMD and device capabilities. + */ +#define ETH_RSS_LEVEL_INNER (0ULL << 50) +/** + * Level 1, It basically stands for the outermost encapsulation level RSS + * can be performed on according to PMD and device capabilities. + */ +#define ETH_RSS_LEVEL_OUTER (1ULL << 50) +/** + * Level 2, It basically stands for the both inner and outermost + * encapsulation level RSS can be performed on according to PMD and + * device capabilities. + */ +#define ETH_RSS_LEVEL_INNER_OUTER (2ULL << 50) +#define ETH_RSS_LEVEL_MASK (3ULL << 50) + +#define ETH_RSS_LEVEL(rss_hf) ((rss_hf & ETH_RSS_LEVEL_MASK) >> 50) + /** * For input set change of hash filter, if SRC_ONLY and DST_ONLY of * the same level are used simultaneously, it is the same case as -- 2.25.1