From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id E5CEBA0351; Mon, 17 Aug 2020 14:47:26 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 98CA91C0BC; Mon, 17 Aug 2020 14:47:26 +0200 (CEST) Received: from mail.chinasoftinc.com (unknown [114.113.233.8]) by dpdk.org (Postfix) with ESMTP id C674F5F13 for ; Mon, 17 Aug 2020 14:47:23 +0200 (CEST) Received: from localhost.localdomain (65.49.108.226) by INCCAS001.ito.icss (10.168.0.60) with Microsoft SMTP Server id 14.3.487.0; Mon, 17 Aug 2020 20:47:13 +0800 From: "Wei Hu (Xavier)" To: CC: , , , Date: Mon, 17 Aug 2020 20:47:03 +0800 Message-ID: <20200817124703.58157-1-huwei013@chinasoftinc.com> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [65.49.108.226] Subject: [dpdk-dev] [PATCH v2] lib/librte_eal: support SVE flag on ARM64 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: "Wei Hu (Xavier)" SVE is the next-generation SIMD extension of the ARMv8-A AArch64 instruction set. The related marco definition can be found in linux kernel: arch/arm64/include/uapi/asm/hwcap.h This patch supports getting cpu SVE feature on ARM64 platform. Signed-off-by: Chengwen Feng Signed-off-by: Wei Hu (Xavier) --- v1 -> v2: Adds more sve-related definition to rte_cpu_feature_table, sunch as SVE2, etc. --- lib/librte_eal/arm/include/rte_cpuflags_64.h | 1 + lib/librte_eal/arm/rte_cpuflags.c | 11 +++++++++++ 2 files changed, 12 insertions(+) diff --git a/lib/librte_eal/arm/include/rte_cpuflags_64.h b/lib/librte_eal/arm/include/rte_cpuflags_64.h index 95cc01474..069844ddb 100644 --- a/lib/librte_eal/arm/include/rte_cpuflags_64.h +++ b/lib/librte_eal/arm/include/rte_cpuflags_64.h @@ -22,6 +22,7 @@ enum rte_cpu_flag_t { RTE_CPUFLAG_SHA2, RTE_CPUFLAG_CRC32, RTE_CPUFLAG_ATOMICS, + RTE_CPUFLAG_SVE, RTE_CPUFLAG_AARCH64, /* The last item */ RTE_CPUFLAG_NUMFLAGS,/**< This should always be the last! */ diff --git a/lib/librte_eal/arm/rte_cpuflags.c b/lib/librte_eal/arm/rte_cpuflags.c index caf3dc83a..97a9fcfd4 100644 --- a/lib/librte_eal/arm/rte_cpuflags.c +++ b/lib/librte_eal/arm/rte_cpuflags.c @@ -95,6 +95,17 @@ const struct feature_entry rte_cpu_feature_table[] = { FEAT_DEF(SHA2, REG_HWCAP, 6) FEAT_DEF(CRC32, REG_HWCAP, 7) FEAT_DEF(ATOMICS, REG_HWCAP, 8) + FEAT_DEF(SVE, REG_HWCAP, 22) + FEAT_DEF(SVE2, REG_HWCAP2, 1) + FEAT_DEF(SVEAES, REG_HWCAP2, 2) + FEAT_DEF(SVEPMULL, REG_HWCAP2, 3) + FEAT_DEF(SVEBITPERM, REG_HWCAP2, 4) + FEAT_DEF(SVESHA3, REG_HWCAP2, 5) + FEAT_DEF(SVESM4, REG_HWCAP2, 6) + FEAT_DEF(SVEI8MM, REG_HWCAP2, 9) + FEAT_DEF(SVEF32MM, REG_HWCAP2, 10) + FEAT_DEF(SVEF64MM, REG_HWCAP2, 11) + FEAT_DEF(SVEBF16, REG_HWCAP2, 12) FEAT_DEF(AARCH64, REG_PLATFORM, 1) }; #endif /* RTE_ARCH */ -- 2.27.0