From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 4B8E0A04B1; Thu, 27 Aug 2020 18:15:37 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 968F41C123; Thu, 27 Aug 2020 18:13:54 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by dpdk.org (Postfix) with ESMTP id 923071C0B0 for ; Thu, 27 Aug 2020 18:13:41 +0200 (CEST) IronPort-SDR: ka23vjhKJILOadwciy36qMnFNqacQB6xqYVKBfDRf3QTKUcocXJlBX8FVUUN2FxHk3gwP+mcl8 iI4M4PI2ADmw== X-IronPort-AV: E=McAfee;i="6000,8403,9726"; a="220767039" X-IronPort-AV: E=Sophos;i="5.76,360,1592895600"; d="scan'208";a="220767039" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Aug 2020 09:13:33 -0700 IronPort-SDR: mpV9JsaStZpiZef9I+/NkOtuYZZDADH4HAgBx3T1mislzIAqmsuFHP+pAn8le8TOk/Ynqq5BjP oD9pVfyDQ4ig== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.76,360,1592895600"; d="scan'208";a="280681552" Received: from silpixa00399953.ir.intel.com (HELO silpixa00399953.ger.corp.intel.com) ([10.237.222.53]) by fmsmga007.fm.intel.com with ESMTP; 27 Aug 2020 09:13:31 -0700 From: Ciara Power To: dev@dpdk.org Cc: Ciara Power , Matan Azrad , Shahaf Shuler , Viacheslav Ovsiienko Date: Thu, 27 Aug 2020 17:12:59 +0100 Message-Id: <20200827161304.32300-13-ciara.power@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200827161304.32300-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20200827161304.32300-1-ciara.power@intel.com> Subject: [dpdk-dev] [PATCH v2 12/17] net/mlx5: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Archived-At: List-Archive: When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. Cc: Matan Azrad Cc: Shahaf Shuler Cc: Viacheslav Ovsiienko Signed-off-by: Ciara Power --- v2: Moved check for max bitwidth into existing check vec support function. --- drivers/net/mlx5/mlx5_rxtx_vec.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/net/mlx5/mlx5_rxtx_vec.c b/drivers/net/mlx5/mlx5_rxtx_vec.c index 711dcd35fa..c384c737dc 100644 --- a/drivers/net/mlx5/mlx5_rxtx_vec.c +++ b/drivers/net/mlx5/mlx5_rxtx_vec.c @@ -148,6 +148,8 @@ mlx5_check_vec_rx_support(struct rte_eth_dev *dev) struct mlx5_priv *priv = dev->data->dev_private; uint32_t i; + if (rte_get_max_simd_bitwidth() < RTE_MAX_128_SIMD) + return -ENOTSUP; if (!priv->config.rx_vec_en) return -ENOTSUP; if (mlx5_mprq_enabled(dev)) -- 2.17.1