From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 0C952A04B1; Thu, 27 Aug 2020 18:16:42 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 47C2A1C1A5; Thu, 27 Aug 2020 18:14:02 +0200 (CEST) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by dpdk.org (Postfix) with ESMTP id 0E0451C0AF for ; Thu, 27 Aug 2020 18:13:43 +0200 (CEST) IronPort-SDR: 6ZriZ5tpS8y35gBVms1zB0tyNTqcgwV6rItNeiRQd11+P8tpY99yKjkTpZ+m/ojfqB4bAeWZah aiCj8erkPP5g== X-IronPort-AV: E=McAfee;i="6000,8403,9726"; a="220767065" X-IronPort-AV: E=Sophos;i="5.76,360,1592895600"; d="scan'208";a="220767065" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Aug 2020 09:13:42 -0700 IronPort-SDR: 6GlkRZUth5iAoXjjDeVVKZ5slXkZ7NHWovn+j9BYrgzWLMnAmpiPaZk0xKPIm2R/Qad+Y+EkAQ gs4nm6k8flIA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.76,360,1592895600"; d="scan'208";a="280681637" Received: from silpixa00399953.ir.intel.com (HELO silpixa00399953.ger.corp.intel.com) ([10.237.222.53]) by fmsmga007.fm.intel.com with ESMTP; 27 Aug 2020 09:13:41 -0700 From: Ciara Power To: dev@dpdk.org Cc: Ciara Power , Jasvinder Singh , Olivier Matz Date: Thu, 27 Aug 2020 17:13:04 +0100 Message-Id: <20200827161304.32300-18-ciara.power@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200827161304.32300-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20200827161304.32300-1-ciara.power@intel.com> Subject: [dpdk-dev] [PATCH v2 17/17] net: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. This check is done just before the handler is called, it cannot be done when setting the handlers initially as the EAL max simd bitwidth value has not yet been set. Cc: Jasvinder Singh Signed-off-by: Ciara Power --- lib/librte_net/rte_net_crc.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/lib/librte_net/rte_net_crc.c b/lib/librte_net/rte_net_crc.c index 9fd4794a9d..d3d3206919 100644 --- a/lib/librte_net/rte_net_crc.c +++ b/lib/librte_net/rte_net_crc.c @@ -9,6 +9,7 @@ #include #include #include +#include #if defined(RTE_ARCH_X86_64) && defined(RTE_MACHINE_CPUFLAG_PCLMULQDQ) #define X86_64_SSE42_PCLMULQDQ 1 @@ -60,6 +61,8 @@ static rte_net_crc_handler handlers_neon[] = { }; #endif +static uint16_t max_simd_bitwidth; + /** * Reflect the bits about the middle * @@ -175,6 +178,11 @@ rte_net_crc_calc(const void *data, uint32_t ret; rte_net_crc_handler f_handle; + if (max_simd_bitwidth == 0) + max_simd_bitwidth = rte_get_max_simd_bitwidth(); + if (max_simd_bitwidth < RTE_MAX_128_SIMD && + handlers != handlers_scalar) + rte_net_crc_set_alg(RTE_NET_CRC_SCALAR); f_handle = handlers[type]; ret = f_handle(data, data_len); -- 2.17.1