From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id C98B5A04C5; Fri, 4 Sep 2020 08:58:35 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id E22F51BC25; Fri, 4 Sep 2020 08:58:34 +0200 (CEST) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by dpdk.org (Postfix) with ESMTP id CFD6DDE0; Fri, 4 Sep 2020 08:58:32 +0200 (CEST) IronPort-SDR: Ty0QM5F2+3rMa6rYUM4dD+m7f501z+xp5deAWipRqnhZ2OGAdCCpPxFxZ5ykCnJVNISt6y1e3K 4pqI8DAm21fw== X-IronPort-AV: E=McAfee;i="6000,8403,9733"; a="145403233" X-IronPort-AV: E=Sophos;i="5.76,388,1592895600"; d="scan'208";a="145403233" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Sep 2020 23:58:31 -0700 IronPort-SDR: eZ5XY/VEePwVaxsSSXdRoDacfgq74FURk8bkidhgPouzgh7+fdaqD/0MrXnopvKdxUQvYDwswY Q3BoCK8LKiRg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.76,388,1592895600"; d="scan'208";a="315751502" Received: from unknown (HELO localhost.localdomain) ([10.240.183.65]) by orsmga002.jf.intel.com with ESMTP; 03 Sep 2020 23:58:29 -0700 From: yanx.fu@intel.com To: qi.z.zhang@intel.com Cc: dev@dpdk.org, stable@dpdk.org, FuYanX Date: Thu, 3 Sep 2020 22:25:20 +0000 Message-Id: <20200903222520.45572-1-yanx.fu@intel.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [dpdk-dev] [PATCH v1 1/1] driver/net/ice sleep in dev_init X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: FuYanX Fix a hardware issue at C0 4 port NIC via fiber. When ice_driver send resetHW cmd, there is need to wait 100ms, then the HW functions will be completed. Otherwise, the function of the port link status will be unstable. Solution just follow datasheet requirement. The operating system sets the FLR bit in the Device Control register of the PF. The operating system is required by PCIe specification to wait 100 ms before it can assume that the FLR sequence is completed by hardware. Signed-off-by: FuYanX --- drivers/net/ice/base/ice_common.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c index 6168fb4f0..f5ea94ece 100644 --- a/drivers/net/ice/base/ice_common.c +++ b/drivers/net/ice/base/ice_common.c @@ -705,6 +705,12 @@ enum ice_status ice_init_hw(struct ice_hw *hw) if (status) return status; + /* The driver e.g. vfio-pci may triggle a FLR reset. + * The operating system sets the FLR bit in the Device Control register of the PF. + * The operating system is required by PCIe specification to wait 100 ms + * before it can assume that the FLR sequence is completed by hardware. + */ + rte_delay_ms(100); hw->pf_id = (u8)(rd32(hw, PF_FUNC_RID) & PF_FUNC_RID_FUNCTION_NUMBER_M) >> PF_FUNC_RID_FUNCTION_NUMBER_S; -- 2.25.1