From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5C8B9A04C5; Sat, 5 Sep 2020 05:00:10 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 19CE31C0D5; Sat, 5 Sep 2020 04:59:47 +0200 (CEST) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by dpdk.org (Postfix) with ESMTP id 6A9D01C0D1 for ; Sat, 5 Sep 2020 04:59:45 +0200 (CEST) IronPort-SDR: lIqn/UFA1xF6cmnFYIBZzODWaHRlTBOA56upCgMBP9UcsKi7kZGfHnI1+TlUCjjPJ8LByW01Oc 1lJbGtd6DgAA== X-IronPort-AV: E=McAfee;i="6000,8403,9734"; a="137886675" X-IronPort-AV: E=Sophos;i="5.76,392,1592895600"; d="scan'208";a="137886675" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Sep 2020 19:59:45 -0700 IronPort-SDR: 0X87ostCIUE0wxQr7K7YM3QNr9TV3FyDz9/UdPvTLev1ua71oO3JpRavjud2UTlc7QQkQd3yqv qMAbhdb69QBg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.76,392,1592895600"; d="scan'208";a="406052712" Received: from unknown (HELO localhost.localdomain) ([10.239.255.52]) by fmsmga001.fm.intel.com with ESMTP; 04 Sep 2020 19:59:43 -0700 From: Guinan Sun To: dev@dpdk.org Cc: Beilei Xing , Qi Zhang , Qiming Yang , Guinan Sun , Jesse Brandeburg Date: Sat, 5 Sep 2020 02:49:32 +0000 Message-Id: <20200905024938.14609-4-guinanx.sun@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200905024938.14609-1-guinanx.sun@intel.com> References: <20200905024938.14609-1-guinanx.sun@intel.com> Subject: [dpdk-dev] [PATCH 3/9] net/i40e/base: enable pipe monitor thresholds X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Enable several registers and defines for software controlled DCB, particularly around the receive pipe monitor configuration which is necessary to help ports achieve the right throughput under load in several different configurations. Signed-off-by: Jesse Brandeburg Signed-off-by: Guinan Sun --- drivers/net/i40e/base/i40e_register.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/net/i40e/base/i40e_register.h b/drivers/net/i40e/base/i40e_register.h index ee4f333f9..ee443e9c9 100644 --- a/drivers/net/i40e/base/i40e_register.h +++ b/drivers/net/i40e/base/i40e_register.h @@ -203,6 +203,9 @@ #define I40E_VFCM_PE_ERRINFO1_RLU_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO1_RLU_ERROR_CNT_SHIFT) #define I40E_VFCM_PE_ERRINFO1_RLS_ERROR_CNT_SHIFT 24 #define I40E_VFCM_PE_ERRINFO1_RLS_ERROR_CNT_MASK I40E_MASK(0xFF, I40E_VFCM_PE_ERRINFO1_RLS_ERROR_CNT_SHIFT) +#define I40E_PRT_SWR_PM_THR 0x0026CD00 /* Reset: CORER */ +#define I40E_PRT_SWR_PM_THR_THRESHOLD_SHIFT 0 +#define I40E_PRT_SWR_PM_THR_THRESHOLD_MASK I40E_MASK(0xFF, I40E_PRT_SWR_PM_THR_THRESHOLD_SHIFT) #define I40E_GLDCB_GENC 0x00083044 /* Reset: CORER */ #define I40E_GLDCB_GENC_PCIRTT_SHIFT 0 #define I40E_GLDCB_GENC_PCIRTT_MASK I40E_MASK(0xFFFF, I40E_GLDCB_GENC_PCIRTT_SHIFT) -- 2.17.1