From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 050C8A04B9; Mon, 7 Sep 2020 11:27:14 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 5BDA41C116; Mon, 7 Sep 2020 11:26:42 +0200 (CEST) Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by dpdk.org (Postfix) with ESMTP id 365341C10F for ; Mon, 7 Sep 2020 11:26:41 +0200 (CEST) IronPort-SDR: IpxMDilr2y13Hpk1kc52u0a1OIkMlcl0etVjyruQjY9xY5dHeXD8JKiKRq7EtD18Opg20fPDnJ DkiKhFJVfE0w== X-IronPort-AV: E=McAfee;i="6000,8403,9736"; a="157241158" X-IronPort-AV: E=Sophos;i="5.76,401,1592895600"; d="scan'208";a="157241158" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Sep 2020 02:26:40 -0700 IronPort-SDR: /oLvto6k+YyCvWdKj8aa7I9h01FG18zZBK2AHvuKbR+zZ4/lSdk5ps020CQwOWGsPfoRCpuY9k Pmk1Pf2P2Unw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.76,401,1592895600"; d="scan'208";a="406783321" Received: from unknown (HELO intel.sh.intel.com) ([10.239.255.60]) by fmsmga001.fm.intel.com with ESMTP; 07 Sep 2020 02:26:39 -0700 From: Junyu Jiang To: dev@dpdk.org Cc: Qi Zhang , Qiming Yang , Guinan Sun Date: Mon, 7 Sep 2020 09:17:10 +0000 Message-Id: <20200907091711.5980-5-junyux.jiang@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200907091711.5980-1-junyux.jiang@intel.com> References: <20200826075501.50052-1-guinanx.sun@intel.com> <20200907091711.5980-1-junyux.jiang@intel.com> Subject: [dpdk-dev] [PATCH v2 4/5] net/ice: support flow mark in SSE path X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Guinan Sun Support Flow Director mark ID parsing from Flex Rx descriptor in SSE path. Signed-off-by: Guinan Sun --- drivers/net/ice/ice_rxtx_vec_sse.c | 49 ++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/drivers/net/ice/ice_rxtx_vec_sse.c b/drivers/net/ice/ice_rxtx_vec_sse.c index fffb27138..965cd8b26 100644 --- a/drivers/net/ice/ice_rxtx_vec_sse.c +++ b/drivers/net/ice/ice_rxtx_vec_sse.c @@ -10,6 +10,25 @@ #pragma GCC diagnostic ignored "-Wcast-qual" #endif +static inline __m128i +ice_flex_rxd_to_fdir_flags_vec(const __m128i fdir_id0_3) +{ +#define FDID_MIS_MAGIC 0xFFFFFFFF + RTE_BUILD_BUG_ON(PKT_RX_FDIR != (1 << 2)); + RTE_BUILD_BUG_ON(PKT_RX_FDIR_ID != (1 << 13)); + const __m128i pkt_fdir_bit = _mm_set1_epi32(PKT_RX_FDIR | + PKT_RX_FDIR_ID); + /* desc->flow_id field == 0xFFFFFFFF means fdir mismatch */ + const __m128i fdir_mis_mask = _mm_set1_epi32(FDID_MIS_MAGIC); + __m128i fdir_mask = _mm_cmpeq_epi32(fdir_id0_3, + fdir_mis_mask); + /* this XOR op results to bit-reverse the fdir_mask */ + fdir_mask = _mm_xor_si128(fdir_mask, fdir_mis_mask); + const __m128i fdir_flags = _mm_and_si128(fdir_mask, pkt_fdir_bit); + + return fdir_flags; +} + static inline void ice_rxq_rearm(struct ice_rx_queue *rxq) { @@ -159,6 +178,36 @@ ice_rx_desc_to_olflags_v(struct ice_rx_queue *rxq, __m128i descs[4], /* merge the flags */ flags = _mm_or_si128(flags, rss_vlan); + if (rxq->fdir_enabled) { + const __m128i fdir_id0_1 = + _mm_unpackhi_epi32(descs[0], descs[1]); + + const __m128i fdir_id2_3 = + _mm_unpackhi_epi32(descs[2], descs[3]); + + const __m128i fdir_id0_3 = + _mm_unpackhi_epi64(fdir_id0_1, fdir_id2_3); + + const __m128i fdir_flags = + ice_flex_rxd_to_fdir_flags_vec(fdir_id0_3); + + /* merge with fdir_flags */ + flags = _mm_or_si128(flags, fdir_flags); + + /* write fdir_id to mbuf */ + rx_pkts[0]->hash.fdir.hi = + _mm_extract_epi32(fdir_id0_3, 0); + + rx_pkts[1]->hash.fdir.hi = + _mm_extract_epi32(fdir_id0_3, 1); + + rx_pkts[2]->hash.fdir.hi = + _mm_extract_epi32(fdir_id0_3, 2); + + rx_pkts[3]->hash.fdir.hi = + _mm_extract_epi32(fdir_id0_3, 3); + } /* if() on fdir_enabled */ + /** * At this point, we have the 4 sets of flags in the low 16-bits * of each 32-bit value in flags. -- 2.17.1