From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5AC93A04AA; Tue, 8 Sep 2020 12:10:37 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 3001E1C023; Tue, 8 Sep 2020 12:10:37 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) by dpdk.org (Postfix) with ESMTP id 228E81C023 for ; Tue, 8 Sep 2020 12:10:34 +0200 (CEST) Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 088A56u8020360; Tue, 8 Sep 2020 03:10:34 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=pfpt0220; bh=FSk+2ztx9EzZ1NrproOLbsYRm3EKlhfEoIRzWb3SW6E=; b=gfBja3L2L5UN50wBz0Q7gHcgtptM5IfAlwyqKuAggbIvW9A7fXsHq2fJAtMVyKo9Gnmm 2oXSrOVCArKattzaUkN+h7V3zmWbgeg5Gnk6f2XVknanI7oyGC612W4AoG1fEAJz8aeu WXGYYSeDi1zfE9z6Kxc8d4K2p3e2+awFPvvkK/Gm3cQyvC5hTyEK2reBFaYd/jq+TKzw 6HBGkc//DJknIO3VCaqvOZTH+kAckjig/u0IZ4QVN+Wc32HUTRMgaNqDw98YOE9nIhKh lbaKPTrKhBWGWLNY0EdSq6ejw70Ox0Pgqb/KUFdl0BcKRX4pBmAKwJr4f84g04ZVzR9b 4w== Received: from sc-exch03.marvell.com ([199.233.58.183]) by mx0a-0016f401.pphosted.com with ESMTP id 33c81pu21v-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Tue, 08 Sep 2020 03:10:34 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 8 Sep 2020 03:10:32 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 8 Sep 2020 03:10:31 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 8 Sep 2020 03:10:31 -0700 Received: from hyd1349.t110.caveonetworks.com (unknown [10.29.45.13]) by maili.marvell.com (Postfix) with ESMTP id D23713F703F; Tue, 8 Sep 2020 03:10:29 -0700 (PDT) From: Ankur Dwivedi To: CC: , , , , Ankur Dwivedi Date: Tue, 8 Sep 2020 15:39:54 +0530 Message-ID: <20200908100956.25868-2-adwivedi@marvell.com> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200908100956.25868-1-adwivedi@marvell.com> References: <20200908100956.25868-1-adwivedi@marvell.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-09-08_05:2020-09-08, 2020-09-08 signatures=0 Subject: [dpdk-dev] [PATCH 1/3] crypto/octeontx2: move functions to helper file X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Some functions are common across cryptodev pmd and the event crypto adapter. This patch moves them into a helper file. Signed-off-by: Ankur Dwivedi --- drivers/crypto/octeontx2/otx2_cryptodev_ops.c | 65 +--------------- .../octeontx2/otx2_cryptodev_ops_helper.h | 74 +++++++++++++++++++ 2 files changed, 75 insertions(+), 64 deletions(-) create mode 100644 drivers/crypto/octeontx2/otx2_cryptodev_ops_helper.h diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c index ccf566d5f..77842b4ad 100644 --- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c +++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c @@ -13,6 +13,7 @@ #include "otx2_cryptodev_hw_access.h" #include "otx2_cryptodev_mbox.h" #include "otx2_cryptodev_ops.h" +#include "otx2_cryptodev_ops_helper.h" #include "otx2_ipsec_po_ops.h" #include "otx2_mbox.h" #include "otx2_sec_idev.h" @@ -416,24 +417,6 @@ sym_session_configure(int driver_id, struct rte_crypto_sym_xform *xform, return -ENOTSUP; } -static void -sym_session_clear(int driver_id, struct rte_cryptodev_sym_session *sess) -{ - void *priv = get_sym_session_private_data(sess, driver_id); - struct rte_mempool *pool; - - if (priv == NULL) - return; - - memset(priv, 0, cpt_get_session_size()); - - pool = rte_mempool_from_obj(priv); - - set_sym_session_private_data(sess, driver_id, NULL); - - rte_mempool_put(pool, priv); -} - static __rte_always_inline int32_t __rte_hot otx2_cpt_enqueue_req(const struct otx2_cpt_qp *qp, struct pending_queue *pend_q, @@ -917,52 +900,6 @@ otx2_cpt_dequeue_post_process(struct otx2_cpt_qp *qp, struct rte_crypto_op *cop, } } -static __rte_always_inline uint8_t -otx2_cpt_compcode_get(struct cpt_request_info *req) -{ - volatile struct cpt_res_s_9s *res; - uint8_t ret; - - res = (volatile struct cpt_res_s_9s *)req->completion_addr; - - if (unlikely(res->compcode == CPT_9X_COMP_E_NOTDONE)) { - if (rte_get_timer_cycles() < req->time_out) - return ERR_REQ_PENDING; - - CPT_LOG_DP_ERR("Request timed out"); - return ERR_REQ_TIMEOUT; - } - - if (likely(res->compcode == CPT_9X_COMP_E_GOOD)) { - ret = NO_ERR; - if (unlikely(res->uc_compcode)) { - ret = res->uc_compcode; - CPT_LOG_DP_DEBUG("Request failed with microcode error"); - CPT_LOG_DP_DEBUG("MC completion code 0x%x", - res->uc_compcode); - } - } else { - CPT_LOG_DP_DEBUG("HW completion code 0x%x", res->compcode); - - ret = res->compcode; - switch (res->compcode) { - case CPT_9X_COMP_E_INSTERR: - CPT_LOG_DP_ERR("Request failed with instruction error"); - break; - case CPT_9X_COMP_E_FAULT: - CPT_LOG_DP_ERR("Request failed with DMA fault"); - break; - case CPT_9X_COMP_E_HWERR: - CPT_LOG_DP_ERR("Request failed with hardware error"); - break; - default: - CPT_LOG_DP_ERR("Request failed with unknown completion code"); - } - } - - return ret; -} - static uint16_t otx2_cpt_dequeue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops) { diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops_helper.h b/drivers/crypto/octeontx2/otx2_cryptodev_ops_helper.h new file mode 100644 index 000000000..764daadea --- /dev/null +++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops_helper.h @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (C) 2020 Marvell International Ltd. + */ + +#ifndef _OTX2_CRYPTODEV_OPS_HELPER_H_ +#define _OTX2_CRYPTODEV_OPS_HELPER_H_ + +#include "cpt_pmd_logs.h" + +static void +sym_session_clear(int driver_id, struct rte_cryptodev_sym_session *sess) +{ + void *priv = get_sym_session_private_data(sess, driver_id); + struct rte_mempool *pool; + + if (priv == NULL) + return; + + memset(priv, 0, cpt_get_session_size()); + + pool = rte_mempool_from_obj(priv); + + set_sym_session_private_data(sess, driver_id, NULL); + + rte_mempool_put(pool, priv); +} + +static __rte_always_inline uint8_t +otx2_cpt_compcode_get(struct cpt_request_info *req) +{ + volatile struct cpt_res_s_9s *res; + uint8_t ret; + + res = (volatile struct cpt_res_s_9s *)req->completion_addr; + + if (unlikely(res->compcode == CPT_9X_COMP_E_NOTDONE)) { + if (rte_get_timer_cycles() < req->time_out) + return ERR_REQ_PENDING; + + CPT_LOG_DP_ERR("Request timed out"); + return ERR_REQ_TIMEOUT; + } + + if (likely(res->compcode == CPT_9X_COMP_E_GOOD)) { + ret = NO_ERR; + if (unlikely(res->uc_compcode)) { + ret = res->uc_compcode; + CPT_LOG_DP_DEBUG("Request failed with microcode error"); + CPT_LOG_DP_DEBUG("MC completion code 0x%x", + res->uc_compcode); + } + } else { + CPT_LOG_DP_DEBUG("HW completion code 0x%x", res->compcode); + + ret = res->compcode; + switch (res->compcode) { + case CPT_9X_COMP_E_INSTERR: + CPT_LOG_DP_ERR("Request failed with instruction error"); + break; + case CPT_9X_COMP_E_FAULT: + CPT_LOG_DP_ERR("Request failed with DMA fault"); + break; + case CPT_9X_COMP_E_HWERR: + CPT_LOG_DP_ERR("Request failed with hardware error"); + break; + default: + CPT_LOG_DP_ERR("Request failed with unknown completion code"); + } + } + + return ret; +} + +#endif /* _OTX2_CRYPTODEV_OPS_HELPER_H_ */ -- 2.28.0