From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5AE06A04B5; Wed, 30 Sep 2020 15:11:33 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 0CCF51DB66; Wed, 30 Sep 2020 15:08:32 +0200 (CEST) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by dpdk.org (Postfix) with ESMTP id 4896D1DB0D for ; Wed, 30 Sep 2020 15:08:20 +0200 (CEST) IronPort-SDR: Jx12fLmssUqU+mpmasnd6xMpLSDXDNkxCfbRvcQ8yvt1pTH46clcZuAYJ/r3bz0ot/Lf3Y8lqL F7AAA7KFgw/A== X-IronPort-AV: E=McAfee;i="6000,8403,9759"; a="150223481" X-IronPort-AV: E=Sophos;i="5.77,322,1596524400"; d="scan'208";a="150223481" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Sep 2020 06:08:18 -0700 IronPort-SDR: 77qWGp/EGe00vvTXTB4MGJHnUwwL/rcvGMiA9Wd2KpwnCpI7+febh5ozWjitZwHF8H1jKHcVDY e5Mxyi+A5XOQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,322,1596524400"; d="scan'208";a="294603231" Received: from silpixa00399953.ir.intel.com (HELO silpixa00399953.ger.corp.intel.com) ([10.237.222.53]) by fmsmga008.fm.intel.com with ESMTP; 30 Sep 2020 06:08:17 -0700 From: Ciara Power To: dev@dpdk.org Cc: Ciara Power , Qiming Yang , Qi Zhang Date: Wed, 30 Sep 2020 14:04:06 +0100 Message-Id: <20200930130415.11211-11-ciara.power@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200930130415.11211-1-ciara.power@intel.com> References: <20200807155859.63888-1-ciara.power@intel.com> <20200930130415.11211-1-ciara.power@intel.com> Subject: [dpdk-dev] [PATCH v3 10/18] net/ice: add checks for max SIMD bitwidth X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" When choosing a vector path to take, an extra condition must be satisfied to ensure the max SIMD bitwidth allows for the CPU enabled path. Cc: Qiming Yang Cc: Qi Zhang Signed-off-by: Ciara Power --- drivers/net/ice/ice_rxtx.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/net/ice/ice_rxtx.c b/drivers/net/ice/ice_rxtx.c index fef6ad4544..5a29af743c 100644 --- a/drivers/net/ice/ice_rxtx.c +++ b/drivers/net/ice/ice_rxtx.c @@ -2936,7 +2936,9 @@ ice_set_rx_function(struct rte_eth_dev *dev) bool use_avx2 = false; if (rte_eal_process_type() == RTE_PROC_PRIMARY) { - if (!ice_rx_vec_dev_check(dev) && ad->rx_bulk_alloc_allowed) { + if (!ice_rx_vec_dev_check(dev) && ad->rx_bulk_alloc_allowed && + rte_get_max_simd_bitwidth() + >= RTE_MAX_128_SIMD) { ad->rx_vec_allowed = true; for (i = 0; i < dev->data->nb_rx_queues; i++) { rxq = dev->data->rx_queues[i]; @@ -2946,8 +2948,10 @@ ice_set_rx_function(struct rte_eth_dev *dev) } } - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 || - rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) + if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 || + rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) && + rte_get_max_simd_bitwidth() + >= RTE_MAX_256_SIMD) use_avx2 = true; } else { @@ -3114,7 +3118,9 @@ ice_set_tx_function(struct rte_eth_dev *dev) bool use_avx2 = false; if (rte_eal_process_type() == RTE_PROC_PRIMARY) { - if (!ice_tx_vec_dev_check(dev)) { + if (!ice_tx_vec_dev_check(dev) && + rte_get_max_simd_bitwidth() + >= RTE_MAX_128_SIMD) { ad->tx_vec_allowed = true; for (i = 0; i < dev->data->nb_tx_queues; i++) { txq = dev->data->tx_queues[i]; @@ -3124,8 +3130,10 @@ ice_set_tx_function(struct rte_eth_dev *dev) } } - if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 || - rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) + if ((rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 || + rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1) && + rte_get_max_simd_bitwidth() + >= RTE_MAX_256_SIMD) use_avx2 = true; } else { -- 2.17.1