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From: Ciara Power <ciara.power@intel.com>
To: dev@dpdk.org
Cc: Ciara Power <ciara.power@intel.com>,
Maxime Coquelin <maxime.coquelin@redhat.com>,
Chenbo Xia <chenbo.xia@intel.com>, Zhihong Wang <zhihong.wang@intel.com>
Date: Wed, 30 Sep 2020 14:04:09 +0100
Message-Id: <20200930130415.11211-14-ciara.power@intel.com>
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<20200930130415.11211-1-ciara.power@intel.com>
Subject: [dpdk-dev] [PATCH v3 13/18] net/virtio: add checks for max SIMD
bitwidth
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When choosing a vector path to take, an extra condition must be
satisfied to ensure the max SIMD bitwidth allows for the CPU enabled
path.
Cc: Maxime Coquelin <maxime.coquelin@redhat.com>
Cc: Chenbo Xia <chenbo.xia@intel.com>
Cc: Zhihong Wang <zhihong.wang@intel.com>
Signed-off-by: Ciara Power <ciara.power@intel.com>
---
v3: Moved max SIMD bitwidth check to configure function with other vec
support checks.
---
drivers/net/virtio/virtio_ethdev.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/net/virtio/virtio_ethdev.c b/drivers/net/virtio/virtio_ethdev.c
index 013a2904e6..f749e81405 100644
--- a/drivers/net/virtio/virtio_ethdev.c
+++ b/drivers/net/virtio/virtio_ethdev.c
@@ -2306,7 +2306,8 @@ virtio_dev_configure(struct rte_eth_dev *dev)
if ((hw->use_vec_rx || hw->use_vec_tx) &&
(!rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) ||
!vtpci_with_feature(hw, VIRTIO_F_IN_ORDER) ||
- !vtpci_with_feature(hw, VIRTIO_F_VERSION_1))) {
+ !vtpci_with_feature(hw, VIRTIO_F_VERSION_1) ||
+ rte_get_max_simd_bitwidth() < RTE_MAX_512_SIMD)) {
PMD_DRV_LOG(INFO,
"disabled packed ring vectorized path for requirements not met");
hw->use_vec_rx = 0;
@@ -2359,6 +2360,12 @@ virtio_dev_configure(struct rte_eth_dev *dev)
"disabled split ring vectorized rx for offloading enabled");
hw->use_vec_rx = 0;
}
+
+ if (rte_get_max_simd_bitwidth() < RTE_MAX_128_SIMD) {
+ PMD_DRV_LOG(INFO,
+ "disabled split ring vectorized rx, max SIMD bitwidth too low");
+ hw->use_vec_rx = 0;
+ }
}
}
--
2.17.1