From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 85808A04B1; Mon, 5 Oct 2020 14:21:54 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id F21081BEE7; Mon, 5 Oct 2020 14:09:39 +0200 (CEST) Received: from smtpbgeu2.qq.com (smtpbgeu2.qq.com [18.194.254.142]) by dpdk.org (Postfix) with ESMTP id C610E1BCDE for ; Mon, 5 Oct 2020 14:09:21 +0200 (CEST) X-QQ-mid: bizesmtp9t1601899757t806k0xrz Received: from localhost.localdomain.com (unknown [183.129.236.74]) by esmtp6.qq.com (ESMTP) with id ; Mon, 05 Oct 2020 20:09:17 +0800 (CST) X-QQ-SSF: 01400000002000C0C000B00A0000000 X-QQ-FEAT: l6IKqkG+NbkJu8oMYLvZ8DnjmG72aEIQ5qZ9pTrKFdbqDDfPT+PlZ0MU4ono8 p8eQOU4tPExklb0FrFR2tH0nKt1dpdJ8hIR52OSTH+sEdyyykeAKVDIsxCY+CuH2+Pfnuq8 /qEEl+3hseS8z1ANGABYnzhwJqbPus3Gnf+AiFxY0bA/DGjkLmlYrM7vMJE29t1C1RSc+Mt ioolZptRptiuhQG5XoyGB8qIiuFUyfj0xgEMkghdDed4bDQXJv1CoB3hipn3X69uQsHpOT4 kEfgtL0iroDpkSM4AUnrughJfqC7g+v7SMcl25SRWgdoIges1OoUUGbWWgai1pjPRhfIjeR g9ORBMxTke4TwLtz1neYegFQSDJAQ== X-QQ-GoodBg: 2 From: Jiawen Wu To: dev@dpdk.org Cc: jiawenwu Date: Mon, 5 Oct 2020 20:08:45 +0800 Message-Id: <20201005120910.189343-32-jiawenwu@trustnetic.com> X-Mailer: git-send-email 2.18.4 In-Reply-To: <20201005120910.189343-1-jiawenwu@trustnetic.com> References: <20201005120910.189343-1-jiawenwu@trustnetic.com> X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:trustnetic.com:qybgforeign:qybgforeign5 X-QQ-Bgrelay: 1 Subject: [dpdk-dev] [PATCH v2 31/56] net/txgbe: support RX interrupt X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: jiawenwu Support rx queue interrupt. Signed-off-by: jiawenwu --- doc/guides/nics/features/txgbe.ini | 1 + doc/guides/nics/txgbe.rst | 1 + drivers/net/txgbe/txgbe_ethdev.c | 43 ++++++++++++++++++++++++++++++ 3 files changed, 45 insertions(+) diff --git a/doc/guides/nics/features/txgbe.ini b/doc/guides/nics/features/txgbe.ini index c8cd58ce2..b2f5f832c 100644 --- a/doc/guides/nics/features/txgbe.ini +++ b/doc/guides/nics/features/txgbe.ini @@ -7,6 +7,7 @@ Speed capabilities = Y Link status = Y Link status event = Y +Rx interrupt = Y Queue start/stop = Y Jumbo frame = Y Scattered Rx = Y diff --git a/doc/guides/nics/txgbe.rst b/doc/guides/nics/txgbe.rst index 101765a6c..1bf4b6b6f 100644 --- a/doc/guides/nics/txgbe.rst +++ b/doc/guides/nics/txgbe.rst @@ -17,6 +17,7 @@ Features - TSO offload - Jumbo frames - Link state information +- Interrupt mode for RX - Scattered and gather for TX and RX - LRO diff --git a/drivers/net/txgbe/txgbe_ethdev.c b/drivers/net/txgbe/txgbe_ethdev.c index 11948389a..9afdf5997 100644 --- a/drivers/net/txgbe/txgbe_ethdev.c +++ b/drivers/net/txgbe/txgbe_ethdev.c @@ -1557,6 +1557,47 @@ txgbe_uc_all_hash_table_set(struct rte_eth_dev *dev, uint8_t on) return 0; } +static int +txgbe_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id) +{ + struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev); + struct rte_intr_handle *intr_handle = &pci_dev->intr_handle; + uint32_t mask; + struct txgbe_hw *hw = TXGBE_DEV_HW(dev); + + if (queue_id < 32) { + mask = rd32(hw, TXGBE_IMS(0)); + mask &= (1 << queue_id); + wr32(hw, TXGBE_IMS(0), mask); + } else if (queue_id < 64) { + mask = rd32(hw, TXGBE_IMS(1)); + mask &= (1 << (queue_id - 32)); + wr32(hw, TXGBE_IMS(1), mask); + } + rte_intr_enable(intr_handle); + + return 0; +} + +static int +txgbe_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id) +{ + uint32_t mask; + struct txgbe_hw *hw = TXGBE_DEV_HW(dev); + + if (queue_id < 32) { + mask = rd32(hw, TXGBE_IMS(0)); + mask &= ~(1 << queue_id); + wr32(hw, TXGBE_IMS(0), mask); + } else if (queue_id < 64) { + mask = rd32(hw, TXGBE_IMS(1)); + mask &= ~(1 << (queue_id - 32)); + wr32(hw, TXGBE_IMS(1), mask); + } + + return 0; +} + /** * set the IVAR registers, mapping interrupt causes to vectors * @param hw @@ -1688,6 +1729,8 @@ static const struct eth_dev_ops txgbe_eth_dev_ops = { .tx_queue_start = txgbe_dev_tx_queue_start, .tx_queue_stop = txgbe_dev_tx_queue_stop, .rx_queue_setup = txgbe_dev_rx_queue_setup, + .rx_queue_intr_enable = txgbe_dev_rx_queue_intr_enable, + .rx_queue_intr_disable = txgbe_dev_rx_queue_intr_disable, .rx_queue_release = txgbe_dev_rx_queue_release, .tx_queue_setup = txgbe_dev_tx_queue_setup, .tx_queue_release = txgbe_dev_tx_queue_release, -- 2.18.4