From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id E8AEDA04B1; Mon, 5 Oct 2020 21:30:18 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 546994C93; Mon, 5 Oct 2020 21:30:16 +0200 (CEST) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by dpdk.org (Postfix) with ESMTP id D67BD4C8E for ; Mon, 5 Oct 2020 21:30:14 +0200 (CEST) IronPort-SDR: MGtUy/jDu2Kxfe2Wq6awbl2+VS6s/Gm3NjJff0r0JjFIChWJRpIXwYH6e4BGimRHuRdxmifWvx JzEcdCkMsx6w== X-IronPort-AV: E=McAfee;i="6000,8403,9765"; a="181652889" X-IronPort-AV: E=Sophos;i="5.77,340,1596524400"; d="scan'208";a="181652889" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Oct 2020 12:28:04 -0700 IronPort-SDR: cUjeOl+yy5RpHtahRvpySVfQw9iT6CaE4/wasEb/JxlOkZ43RXrpRSlPqu8i4eOkAh7fntyrmn GO59jnlWAM+A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,340,1596524400"; d="scan'208";a="526625316" Received: from sivswdev08.ir.intel.com ([10.237.217.47]) by orsmga005.jf.intel.com with ESMTP; 05 Oct 2020 11:46:27 -0700 From: Konstantin Ananyev To: dev@dpdk.org Cc: jerinj@marvell.com, ruifeng.wang@arm.com, vladimir.medvedkin@intel.com, Konstantin Ananyev Date: Mon, 5 Oct 2020 19:45:21 +0100 Message-Id: <20201005184526.7465-10-konstantin.ananyev@intel.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20201005184526.7465-1-konstantin.ananyev@intel.com> References: <20200915165025.543-1-konstantin.ananyev@intel.com> <20201005184526.7465-1-konstantin.ananyev@intel.com> Subject: [dpdk-dev] [PATCH v3 09/14] acl: update default classify algorithm selection X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On supported platforms, set RTE_ACL_CLASSIFY_AVX512X16 as default ACL classify algorithm. Note that AVX512X16 implementation uses 256-bit registers/instincts only to avoid possibility of frequency drop. Signed-off-by: Konstantin Ananyev --- lib/librte_acl/rte_acl.c | 1 + 1 file changed, 1 insertion(+) diff --git a/lib/librte_acl/rte_acl.c b/lib/librte_acl/rte_acl.c index 1154f35107..245af672ee 100644 --- a/lib/librte_acl/rte_acl.c +++ b/lib/librte_acl/rte_acl.c @@ -228,6 +228,7 @@ acl_get_best_alg(void) #elif defined(RTE_ARCH_PPC_64) RTE_ACL_CLASSIFY_ALTIVEC, #elif defined(RTE_ARCH_X86) + RTE_ACL_CLASSIFY_AVX512X16, RTE_ACL_CLASSIFY_AVX2, RTE_ACL_CLASSIFY_SSE, #endif -- 2.17.1