From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id E7C43A04BB; Tue, 6 Oct 2020 17:11:39 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 2D5F51BB12; Tue, 6 Oct 2020 17:08:33 +0200 (CEST) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by dpdk.org (Postfix) with ESMTP id 440191BAC7 for ; Tue, 6 Oct 2020 17:08:29 +0200 (CEST) IronPort-SDR: Z2yKS2s8rcHdJ5Qo/lUC93r/5lwDvun0bKN3ARMANxWj9c1mdXaL70PYXprBZNoP4w4l+Xl1Uf RQneJNE3x2Fg== X-IronPort-AV: E=McAfee;i="6000,8403,9765"; a="143919648" X-IronPort-AV: E=Sophos;i="5.77,343,1596524400"; d="scan'208";a="143919648" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Oct 2020 08:03:47 -0700 IronPort-SDR: qHf9rDtmEES/fTucwXSa9bqq9bUckkdsm0rym4JA9qdMjmTCwFrA61wo0WCTiC1lXpHYzKSLn/ rng9F6vJfDVQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,343,1596524400"; d="scan'208";a="518315440" Received: from sivswdev08.ir.intel.com ([10.237.217.47]) by fmsmga005.fm.intel.com with ESMTP; 06 Oct 2020 08:03:46 -0700 From: Konstantin Ananyev To: dev@dpdk.org Cc: jerinj@marvell.com, ruifeng.wang@arm.com, vladimir.medvedkin@intel.com, Konstantin Ananyev Date: Tue, 6 Oct 2020 16:03:11 +0100 Message-Id: <20201006150316.5776-10-konstantin.ananyev@intel.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20201006150316.5776-1-konstantin.ananyev@intel.com> References: <20201005184526.7465-1-konstantin.ananyev@intel.com> <20201006150316.5776-1-konstantin.ananyev@intel.com> Subject: [dpdk-dev] [PATCH v4 09/14] acl: update default classify algorithm selection X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" On supported platforms, set RTE_ACL_CLASSIFY_AVX512X16 as default ACL classify algorithm. Note that AVX512X16 implementation uses 256-bit registers/instincts only to avoid possibility of frequency drop. Signed-off-by: Konstantin Ananyev --- lib/librte_acl/rte_acl.c | 1 + 1 file changed, 1 insertion(+) diff --git a/lib/librte_acl/rte_acl.c b/lib/librte_acl/rte_acl.c index 1154f35107..245af672ee 100644 --- a/lib/librte_acl/rte_acl.c +++ b/lib/librte_acl/rte_acl.c @@ -228,6 +228,7 @@ acl_get_best_alg(void) #elif defined(RTE_ARCH_PPC_64) RTE_ACL_CLASSIFY_ALTIVEC, #elif defined(RTE_ARCH_X86) + RTE_ACL_CLASSIFY_AVX512X16, RTE_ACL_CLASSIFY_AVX2, RTE_ACL_CLASSIFY_SSE, #endif -- 2.17.1